Lines Matching refs:op
624 #define uMIPS_RD(op) ((op >> 7) & 0x7)
625 #define uMIPS_RS(op) ((op >> 4) & 0x7)
626 #define uMIPS_RS2(op) uMIPS_RS(op)
627 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
628 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
629 #define uMIPS_RS5(op) (op & 0x1f)
632 #define SIMM(op, start, width) \
633 ((int32_t)(((op >> start) & ((~0U) >> (32 - width))) \
637 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32 - width)))
1627 uint32_t op, minor, minor2, mips32_op;
1639 op = (ctx->opcode >> 26) & 0x3f;
1640 switch (op) {
2643 /* Treat as no-op */
2650 /* Treat as no-op */
2670 /* Treat as no-op */
2977 uint32_t op;
2986 op = (ctx->opcode >> 10) & 0x3f;
2989 switch (op & 0x7) { /* MSB-3..MSB-5 */
3019 switch (op) {
3205 gen_compute_branch(ctx, op == BNEZ16 ? OPC_BNE : OPC_BEQ, 2,