242 static uint32_t emc_read(QTestState *qts, const EMCModule *mod,  in emc_read()  argument
245     return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t));  in emc_read()
249 static void emc_write(QTestState *qts, const EMCModule *mod,  in emc_write()  argument
252     qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value);  in emc_write()
255 static void emc_read_tx_desc(QTestState *qts, uint32_t addr,  in emc_read_tx_desc()  argument
258     qtest_memread(qts, addr, desc, sizeof(*desc));  in emc_read_tx_desc()
265 static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc,  in emc_write_tx_desc()  argument
274     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));  in emc_write_tx_desc()
277 static void emc_read_rx_desc(QTestState *qts, uint32_t addr,  in emc_read_rx_desc()  argument
280     qtest_memread(qts, addr, desc, sizeof(*desc));  in emc_read_rx_desc()
287 static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc,  in emc_write_rx_desc()  argument
296     qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc));  in emc_write_rx_desc()
303 static bool emc_soft_reset(QTestState *qts, const EMCModule *mod)  in emc_soft_reset()  argument
308     emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR);  in emc_soft_reset()
318         qtest_clock_step(qts, 100);  in emc_soft_reset()
319         val = emc_read(qts, mod, REG_FFTCR);  in emc_soft_reset()
323             qtest_clock_step(qts, 100);  in emc_soft_reset()
324             val = emc_read(qts, mod, REG_MCMDR);  in emc_soft_reset()
345     QTestState *qts = qtest_init("-machine quanta-gsj");  in test_init()  local
350     g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \  in test_init()
379         g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==,  in test_init()
381         g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==,  in test_init()
385     qtest_quit(qts);  in test_init()
389 static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step,  in emc_wait_irq()  argument
396         if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) {  in emc_wait_irq()
399         qtest_clock_step(qts, step);  in emc_wait_irq()
406 static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step,  in emc_wait_mista()  argument
413         uint32_t mista = emc_read(qts, mod, REG_MISTA);  in emc_wait_mista()
417         qtest_clock_step(qts, step);  in emc_wait_mista()
473 static void enable_tx(QTestState *qts, const EMCModule *mod,  in enable_tx()  argument
479         emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));  in enable_tx()
484     g_assert(emc_soft_reset(qts, mod));  in enable_tx()
485     emc_write(qts, mod, REG_TXDLSA, desc_addr);  in enable_tx()
486     emc_write(qts, mod, REG_CTXDSA, ~0);  in enable_tx()
487     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags);  in enable_tx()
489         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);  in enable_tx()
491         emc_write(qts, mod, REG_MCMDR, mcmdr);  in enable_tx()
495 static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd,  in emc_send_verify1()  argument
508     emc_read_tx_desc(qts, desc_addr, &result_desc);  in emc_send_verify1()
531 static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd,  in emc_send_verify()  argument
544     qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data));  in emc_send_verify()
545     qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data));  in emc_send_verify()
553     enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr,  in emc_send_verify()
557     emc_write(qts, mod, REG_TSDR, 1);  in emc_send_verify()
566             g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT,  in emc_send_verify()
569             g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT,  in emc_send_verify()
572         got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU);  in emc_send_verify()
575             emc_write(qts, mod, REG_MISTA,  in emc_send_verify()
576                       emc_read(qts, mod, REG_MISTA) & 0xffff0000);  in emc_send_verify()
581     g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr);  in emc_send_verify()
582     g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==,  in emc_send_verify()
585     emc_send_verify1(qts, mod, fd, with_irq,  in emc_send_verify()
588     emc_send_verify1(qts, mod, fd, with_irq,  in emc_send_verify()
613 static void enable_rx(QTestState *qts, const EMCModule *mod,  in enable_rx()  argument
624         emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc));  in enable_rx()
629     g_assert(emc_soft_reset(qts, mod));  in enable_rx()
630     emc_write(qts, mod, REG_RXDLSA, desc_addr);  in enable_rx()
631     emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags);  in enable_rx()
637     emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP);  in enable_rx()
638     emc_write(qts, mod, REG_CAMEN, 1 << 0);  in enable_rx()
640         uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR);  in enable_rx()
642         emc_write(qts, mod, REG_MCMDR, mcmdr);  in enable_rx()
646 static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd,  in emc_recv_verify()  argument
674     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,  in emc_recv_verify()
683         emc_write(qts, mod, REG_RSDR, 1);  in emc_recv_verify()
692         g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));  in emc_recv_verify()
694         g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD));  in emc_recv_verify()
697     g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==,  in emc_recv_verify()
704     g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask),  in emc_recv_verify()
708     emc_read_rx_desc(qts, desc_addr, &result_desc);  in emc_recv_verify()
724         qtest_memread(qts, data_addr, buffer, sizeof(buffer));  in emc_recv_verify()
729 static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd)  in emc_test_ptle()  argument
758     enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr,  in emc_test_ptle()
766     g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false));  in emc_test_ptle()
769     emc_read_rx_desc(qts, desc_addr, &result_desc);  in emc_test_ptle()
784         qtest_memread(qts, data_addr, buffer, sizeof(buffer));  in emc_test_ptle()
795     QTestState *qts = qtest_init(cmd_line->str);  in test_tx()  local
806     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");  in test_tx()
808     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false);  in test_tx()
809     emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true);  in test_tx()
811     qtest_quit(qts);  in test_tx()
820     QTestState *qts = qtest_init(cmd_line->str);  in test_rx()  local
831     qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");  in test_rx()
833     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,  in test_rx()
835     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false,  in test_rx()
837     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,  in test_rx()
839     emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true,  in test_rx()
841     emc_test_ptle(qts, td->module, test_sockets[0]);  in test_rx()
843     qtest_quit(qts);  in test_rx()