/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Global Instruction Selector for the ARM target *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_GLOBALISEL_PREDICATE_BITSET const unsigned MAX_SUBTARGET_PREDICATES = 72; using PredicateBitset = llvm::PredicateBitsetImpl; #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET #ifdef GET_GLOBALISEL_TEMPORARIES_DECL mutable MatcherState State; typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const; const ISelInfoTy ISelInfo; static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; const int64_t *getMatchTable() const override; bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL #ifdef GET_GLOBALISEL_TEMPORARIES_INIT , State(0), ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT #ifdef GET_GLOBALISEL_IMPL // Bits for subtarget features that participate in instruction matching. enum SubtargetFeatureBits : uint8_t { Feature_NoHonorSignDependentRoundingBit = 64, Feature_HasV4TBit = 6, Feature_NoV4TBit = 7, Feature_HasV5TBit = 8, Feature_NoV5TBit = 61, Feature_HasV5TEBit = 12, Feature_HasV6Bit = 0, Feature_NoV6Bit = 10, Feature_HasV6MBit = 29, Feature_HasV8MBaselineBit = 33, Feature_HasV8_1MMainlineBit = 59, Feature_HasMVEIntBit = 58, Feature_HasMVEFloatBit = 60, Feature_HasFPRegsBit = 39, Feature_HasFPRegs16Bit = 40, Feature_HasFPRegs64Bit = 49, Feature_HasV6T2Bit = 9, Feature_HasV6KBit = 19, Feature_HasV7Bit = 3, Feature_HasV8Bit = 15, Feature_PreV8Bit = 20, Feature_HasV8_1aBit = 66, Feature_HasV8_3aBit = 67, Feature_NoVFPBit = 23, Feature_HasVFP2Bit = 22, Feature_HasVFP3Bit = 50, Feature_HasVFP4Bit = 47, Feature_HasDPVFPBit = 41, Feature_HasFPARMv8Bit = 44, Feature_HasNEONBit = 51, Feature_HasCryptoBit = 52, Feature_HasDotProdBit = 53, Feature_HasCRCBit = 14, Feature_HasFP16Bit = 57, Feature_HasFullFP16Bit = 43, Feature_HasDivideInThumbBit = 35, Feature_HasDivideInARMBit = 13, Feature_HasDSPBit = 34, Feature_HasDBBit = 16, Feature_HasV7ClrexBit = 18, Feature_HasAcquireReleaseBit = 17, Feature_HasMPBit = 2, Feature_Has8MSecExtBit = 38, Feature_HasZCZBit = 54, Feature_UseNEONForFPBit = 70, Feature_DontUseNEONForFPBit = 42, Feature_IsThumbBit = 27, Feature_IsThumb1OnlyBit = 28, Feature_IsThumb2Bit = 32, Feature_IsNotMClassBit = 36, Feature_IsARMBit = 1, Feature_IsWindowsBit = 30, Feature_IsNotWindowsBit = 31, Feature_IsReadTPHardBit = 62, Feature_IsReadTPSoftBit = 21, Feature_UseNaClTrapBit = 4, Feature_DontUseNaClTrapBit = 5, Feature_UseMovtBit = 37, Feature_DontUseMovtBit = 24, Feature_UseMovtInPicBit = 25, Feature_DontUseMovtInPicBit = 26, Feature_UseFPVMLxBit = 46, Feature_UseMulOpsBit = 11, Feature_UseFusedMACBit = 48, Feature_HasFastVGETLNi32Bit = 55, Feature_HasSlowVGETLNi32Bit = 68, Feature_HasFastVDUP32Bit = 56, Feature_HasSlowVDUP32Bit = 69, Feature_UseVMOVSRBit = 45, Feature_DontUseVMOVSRBit = 71, Feature_IsLEBit = 63, Feature_IsBEBit = 65, }; PredicateBitset ARMInstructionSelector:: computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { PredicateBitset Features; if (!TM.Options.HonorSignDependentRoundingFPMath()) Features.set(Feature_NoHonorSignDependentRoundingBit); if (Subtarget->hasV4TOps()) Features.set(Feature_HasV4TBit); if (!Subtarget->hasV4TOps()) Features.set(Feature_NoV4TBit); if (Subtarget->hasV5TOps()) Features.set(Feature_HasV5TBit); if (!Subtarget->hasV5TOps()) Features.set(Feature_NoV5TBit); if (Subtarget->hasV5TEOps()) Features.set(Feature_HasV5TEBit); if (Subtarget->hasV6Ops()) Features.set(Feature_HasV6Bit); if (!Subtarget->hasV6Ops()) Features.set(Feature_NoV6Bit); if (Subtarget->hasV6MOps()) Features.set(Feature_HasV6MBit); if (Subtarget->hasV8MBaselineOps()) Features.set(Feature_HasV8MBaselineBit); if (Subtarget->hasV8_1MMainlineOps()) Features.set(Feature_HasV8_1MMainlineBit); if (Subtarget->hasMVEIntegerOps()) Features.set(Feature_HasMVEIntBit); if (Subtarget->hasMVEFloatOps()) Features.set(Feature_HasMVEFloatBit); if (Subtarget->hasFPRegs()) Features.set(Feature_HasFPRegsBit); if (Subtarget->hasFPRegs16()) Features.set(Feature_HasFPRegs16Bit); if (Subtarget->hasFPRegs64()) Features.set(Feature_HasFPRegs64Bit); if (Subtarget->hasV6T2Ops()) Features.set(Feature_HasV6T2Bit); if (Subtarget->hasV6KOps()) Features.set(Feature_HasV6KBit); if (Subtarget->hasV7Ops()) Features.set(Feature_HasV7Bit); if (Subtarget->hasV8Ops()) Features.set(Feature_HasV8Bit); if (!Subtarget->hasV8Ops()) Features.set(Feature_PreV8Bit); if (Subtarget->hasV8_1aOps()) Features.set(Feature_HasV8_1aBit); if (Subtarget->hasV8_3aOps()) Features.set(Feature_HasV8_3aBit); if (!Subtarget->hasVFP2Base()) Features.set(Feature_NoVFPBit); if (Subtarget->hasVFP2Base()) Features.set(Feature_HasVFP2Bit); if (Subtarget->hasVFP3Base()) Features.set(Feature_HasVFP3Bit); if (Subtarget->hasVFP4Base()) Features.set(Feature_HasVFP4Bit); if (Subtarget->hasFP64()) Features.set(Feature_HasDPVFPBit); if (Subtarget->hasFPARMv8Base()) Features.set(Feature_HasFPARMv8Bit); if (Subtarget->hasNEON()) Features.set(Feature_HasNEONBit); if (Subtarget->hasCrypto()) Features.set(Feature_HasCryptoBit); if (Subtarget->hasDotProd()) Features.set(Feature_HasDotProdBit); if (Subtarget->hasCRC()) Features.set(Feature_HasCRCBit); if (Subtarget->hasFP16()) Features.set(Feature_HasFP16Bit); if (Subtarget->hasFullFP16()) Features.set(Feature_HasFullFP16Bit); if (Subtarget->hasDivideInThumbMode()) Features.set(Feature_HasDivideInThumbBit); if (Subtarget->hasDivideInARMMode()) Features.set(Feature_HasDivideInARMBit); if (Subtarget->hasDSP()) Features.set(Feature_HasDSPBit); if (Subtarget->hasDataBarrier()) Features.set(Feature_HasDBBit); if (Subtarget->hasV7Clrex()) Features.set(Feature_HasV7ClrexBit); if (Subtarget->hasAcquireRelease()) Features.set(Feature_HasAcquireReleaseBit); if (Subtarget->hasMPExtension()) Features.set(Feature_HasMPBit); if (Subtarget->has8MSecExt()) Features.set(Feature_Has8MSecExtBit); if (Subtarget->hasZeroCycleZeroing()) Features.set(Feature_HasZCZBit); if (Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_UseNEONForFPBit); if (!Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_DontUseNEONForFPBit); if (Subtarget->isThumb()) Features.set(Feature_IsThumbBit); if (Subtarget->isThumb1Only()) Features.set(Feature_IsThumb1OnlyBit); if (Subtarget->isThumb2()) Features.set(Feature_IsThumb2Bit); if (!Subtarget->isMClass()) Features.set(Feature_IsNotMClassBit); if (!Subtarget->isThumb()) Features.set(Feature_IsARMBit); if (Subtarget->isTargetWindows()) Features.set(Feature_IsWindowsBit); if (!Subtarget->isTargetWindows()) Features.set(Feature_IsNotWindowsBit); if (Subtarget->isReadTPHard()) Features.set(Feature_IsReadTPHardBit); if (!Subtarget->isReadTPHard()) Features.set(Feature_IsReadTPSoftBit); if (Subtarget->useNaClTrap()) Features.set(Feature_UseNaClTrapBit); if (!Subtarget->useNaClTrap()) Features.set(Feature_DontUseNaClTrapBit); if (Subtarget->useMulOps()) Features.set(Feature_UseMulOpsBit); if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) Features.set(Feature_UseFusedMACBit); if (!Subtarget->hasSlowVGETLNi32()) Features.set(Feature_HasFastVGETLNi32Bit); if (Subtarget->hasSlowVGETLNi32()) Features.set(Feature_HasSlowVGETLNi32Bit); if (!Subtarget->hasSlowVDUP32()) Features.set(Feature_HasFastVDUP32Bit); if (Subtarget->hasSlowVDUP32()) Features.set(Feature_HasSlowVDUP32Bit); if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_UseVMOVSRBit); if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) Features.set(Feature_DontUseVMOVSRBit); return Features; } void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget*)&MF.getSubtarget(), &MF); } PredicateBitset ARMInstructionSelector:: computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { PredicateBitset Features; if (Subtarget->useMovt()) Features.set(Feature_UseMovtBit); if (!Subtarget->useMovt()) Features.set(Feature_DontUseMovtBit); if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) Features.set(Feature_UseMovtInPicBit); if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) Features.set(Feature_DontUseMovtInPicBit); if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) Features.set(Feature_UseFPVMLxBit); if (MF->getDataLayout().isLittleEndian()) Features.set(Feature_IsLEBit); if (MF->getDataLayout().isBigEndian()) Features.set(Feature_IsBEBit); return Features; } // LLT Objects. enum { GILLT_s16, GILLT_s32, GILLT_s64, GILLT_v2s32, GILLT_v2s64, GILLT_v4s1, GILLT_v4s16, GILLT_v4s32, GILLT_v4s64, GILLT_v8s1, GILLT_v8s8, GILLT_v8s16, GILLT_v8s64, GILLT_v16s1, GILLT_v16s8, }; const static size_t NumTypeObjects = 15; const static LLT TypeObjects[] = { LLT::scalar(16), LLT::scalar(32), LLT::scalar(64), LLT::vector(2, 32), LLT::vector(2, 64), LLT::vector(4, 1), LLT::vector(4, 16), LLT::vector(4, 32), LLT::vector(4, 64), LLT::vector(8, 1), LLT::vector(8, 8), LLT::vector(8, 16), LLT::vector(8, 64), LLT::vector(16, 1), LLT::vector(16, 8), }; // Feature bitsets. enum { GIFBS_Invalid, GIFBS_HasDotProd, GIFBS_HasFP16, GIFBS_HasFPARMv8, GIFBS_HasFPRegs, GIFBS_HasFullFP16, GIFBS_HasMVEFloat, GIFBS_HasMVEInt, GIFBS_HasNEON, GIFBS_HasVFP2, GIFBS_HasVFP3, GIFBS_HasVFP4, GIFBS_IsARM, GIFBS_IsThumb, GIFBS_IsThumb2, GIFBS_NoHonorSignDependentRounding, GIFBS_DontUseNEONForFP_HasVFP2, GIFBS_Has8MSecExt_IsThumb, GIFBS_HasCrypto_HasV8, GIFBS_HasDB_IsARM, GIFBS_HasDB_IsThumb, GIFBS_HasDPVFP_HasFPARMv8, GIFBS_HasDPVFP_HasVFP2, GIFBS_HasDPVFP_HasVFP3, GIFBS_HasDPVFP_HasVFP4, GIFBS_HasDPVFP_NoHonorSignDependentRounding, GIFBS_HasDSP_IsThumb2, GIFBS_HasDivideInARM_IsARM, GIFBS_HasFP16_HasNEON, GIFBS_HasFPRegs_UseVMOVSR, GIFBS_HasFullFP16_HasNEON, GIFBS_HasMVEInt_HasV8_1MMainline, GIFBS_HasMVEInt_IsBE, GIFBS_HasMVEInt_IsLE, GIFBS_HasNEON_HasV8, GIFBS_HasNEON_HasV8_3a, GIFBS_HasNEON_HasVFP4, GIFBS_HasNEON_IsBE, GIFBS_HasNEON_IsLE, GIFBS_HasV5T_IsARM, GIFBS_HasV5TE_IsARM, GIFBS_HasV6_IsARM, GIFBS_HasV6K_IsARM, GIFBS_HasV6M_IsThumb, GIFBS_HasV6T2_IsARM, GIFBS_HasV7_IsARM, GIFBS_HasV7Clrex_IsThumb, GIFBS_HasV8MBaseline_IsThumb, GIFBS_IsARM_NoV6, GIFBS_IsARM_PreV8, GIFBS_IsThumb_IsThumb1Only, GIFBS_IsThumb_IsWindows, GIFBS_IsThumb_UseMovt, GIFBS_IsThumb2_PreV8, GIFBS_IsThumb2_UseMulOps, GIFBS_HasCRC_HasV8_IsARM, GIFBS_HasCRC_HasV8_IsThumb2, GIFBS_HasDSP_IsThumb2_UseMulOps, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, GIFBS_HasFullFP16_HasNEON_HasV8, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIFBS_HasFullFP16_HasNEON_UseFPVMLx, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIFBS_HasV5TE_IsARM_UseMulOps, GIFBS_HasV6_IsARM_UseMulOps, GIFBS_HasV6_IsThumb_IsThumb1Only, GIFBS_HasV6T2_IsARM_UseMulOps, GIFBS_IsARM_NoV6_UseMulOps, }; const static PredicateBitset FeatureBitsets[] { {}, // GIFBS_Invalid {Feature_HasDotProdBit, }, {Feature_HasFP16Bit, }, {Feature_HasFPARMv8Bit, }, {Feature_HasFPRegsBit, }, {Feature_HasFullFP16Bit, }, {Feature_HasMVEFloatBit, }, {Feature_HasMVEIntBit, }, {Feature_HasNEONBit, }, {Feature_HasVFP2Bit, }, {Feature_HasVFP3Bit, }, {Feature_HasVFP4Bit, }, {Feature_IsARMBit, }, {Feature_IsThumbBit, }, {Feature_IsThumb2Bit, }, {Feature_NoHonorSignDependentRoundingBit, }, {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, {Feature_HasCryptoBit, Feature_HasV8Bit, }, {Feature_HasDBBit, Feature_IsARMBit, }, {Feature_HasDBBit, Feature_IsThumbBit, }, {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, {Feature_HasDSPBit, Feature_IsThumb2Bit, }, {Feature_HasDivideInARMBit, Feature_IsARMBit, }, {Feature_HasFP16Bit, Feature_HasNEONBit, }, {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, {Feature_HasMVEIntBit, Feature_IsBEBit, }, {Feature_HasMVEIntBit, Feature_IsLEBit, }, {Feature_HasNEONBit, Feature_HasV8Bit, }, {Feature_HasNEONBit, Feature_HasV8_3aBit, }, {Feature_HasNEONBit, Feature_HasVFP4Bit, }, {Feature_HasNEONBit, Feature_IsBEBit, }, {Feature_HasNEONBit, Feature_IsLEBit, }, {Feature_HasV5TBit, Feature_IsARMBit, }, {Feature_HasV5TEBit, Feature_IsARMBit, }, {Feature_HasV6Bit, Feature_IsARMBit, }, {Feature_HasV6KBit, Feature_IsARMBit, }, {Feature_HasV6MBit, Feature_IsThumbBit, }, {Feature_HasV6T2Bit, Feature_IsARMBit, }, {Feature_HasV7Bit, Feature_IsARMBit, }, {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, {Feature_IsARMBit, Feature_NoV6Bit, }, {Feature_IsARMBit, Feature_PreV8Bit, }, {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, {Feature_IsThumbBit, Feature_IsWindowsBit, }, {Feature_IsThumbBit, Feature_UseMovtBit, }, {Feature_IsThumb2Bit, Feature_PreV8Bit, }, {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, }, {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, }, {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, }; // ComplexPattern predicates. enum { GICP_Invalid, }; // See constructor for table contents // PatFrag predicates. enum { GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1, GIPFP_I64_Predicate_VectorIndex32, GIPFP_I64_Predicate_VectorIndex64, GIPFP_I64_Predicate_VectorIndex8, GIPFP_I64_Predicate_imm0_15, GIPFP_I64_Predicate_imm0_239, GIPFP_I64_Predicate_imm0_255, GIPFP_I64_Predicate_imm0_31, GIPFP_I64_Predicate_imm0_32, GIPFP_I64_Predicate_imm0_4095, GIPFP_I64_Predicate_imm0_63, GIPFP_I64_Predicate_imm0_65535, GIPFP_I64_Predicate_imm0_65535_neg, GIPFP_I64_Predicate_imm0_7, GIPFP_I64_Predicate_imm16, GIPFP_I64_Predicate_imm16_31, GIPFP_I64_Predicate_imm1_15, GIPFP_I64_Predicate_imm1_16, GIPFP_I64_Predicate_imm1_31, GIPFP_I64_Predicate_imm1_7, GIPFP_I64_Predicate_imm24b, GIPFP_I64_Predicate_imm256_510, GIPFP_I64_Predicate_imm32, GIPFP_I64_Predicate_imm8, GIPFP_I64_Predicate_imm8_255, GIPFP_I64_Predicate_imm8_or_16, GIPFP_I64_Predicate_imm_even, GIPFP_I64_Predicate_imm_odd, GIPFP_I64_Predicate_long_shift, GIPFP_I64_Predicate_mod_imm, GIPFP_I64_Predicate_pkh_asr_amt, GIPFP_I64_Predicate_pkh_lsl_amt, GIPFP_I64_Predicate_shr_imm16, GIPFP_I64_Predicate_shr_imm32, GIPFP_I64_Predicate_shr_imm64, GIPFP_I64_Predicate_shr_imm8, GIPFP_I64_Predicate_t2_so_imm, GIPFP_I64_Predicate_t2_so_imm_neg, }; bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { switch (PredicateID) { case GIPFP_I64_Predicate_VectorIndex16: { return ((uint64_t)Imm) < 4; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex32: { return ((uint64_t)Imm) < 2; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex64: { return ((uint64_t)Imm) < 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_VectorIndex8: { return ((uint64_t)Imm) < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_15: { return Imm >= 0 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_239: { return Imm >= 0 && Imm < 240; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_255: { return Imm >= 0 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_31: { return Imm >= 0 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_32: { return Imm >= 0 && Imm < 33; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_4095: { return Imm >= 0 && Imm < 4096; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_63: { return Imm >= 0 && Imm < 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_65535: { return Imm >= 0 && Imm < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_65535_neg: { return -Imm >= 0 && -Imm < 65536; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm0_7: { return Imm >= 0 && Imm < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm16: { return Imm == 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm16_31: { return (int32_t)Imm >= 16 && (int32_t)Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm1_15: { return Imm > 0 && Imm < 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm1_16: { return Imm > 0 && Imm <= 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm1_31: { return Imm > 0 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm1_7: { return Imm > 0 && Imm < 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm24b: { return Imm >= 0 && Imm <= 0xffffff; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm256_510: { return Imm >= 256 && Imm < 511; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm32: { return Imm == 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm8: { return Imm == 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm8_255: { return Imm >= 8 && Imm < 256; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm8_or_16: { return Imm == 8 || Imm == 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm_even: { return (Imm & 1) == 0; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_imm_odd: { return (Imm & 1) == 1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_long_shift: { return Imm > 0 && Imm <= 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_mod_imm: { return ARM_AM::getSOImmVal(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_pkh_asr_amt: { return Imm > 0 && Imm <= 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_pkh_lsl_amt: { return Imm >= 0 && Imm < 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_shr_imm16: { return Imm > 0 && Imm <= 16; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_shr_imm32: { return Imm > 0 && Imm <= 32; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_shr_imm64: { return Imm > 0 && Imm <= 64; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_shr_imm8: { return Imm > 0 && Imm <= 8; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_t2_so_imm: { return ARM_AM::getT2SOImmVal(Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } case GIPFP_I64_Predicate_t2_so_imm_neg: { return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1, }; bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { switch (PredicateID) { case GIPFP_APInt_Predicate_arm_i32imm: { if (Subtarget->useMovt()) return true; return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()); llvm_unreachable("ImmediateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } // PatFrag predicates. enum { GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1, GIPFP_MI_Predicate_vfp_f32imm, GIPFP_MI_Predicate_vfp_f64imm, }; bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); (void)MRI; switch (PredicateID) { case GIPFP_MI_Predicate_bf_inv_mask_imm: { // There's better methods of implementing this check. IntImmLeaf<> would be // equivalent and have less boilerplate but we need a test for C++ // predicates and this one causes new rules to be imported into GlobalISel // without requiring additional features first. const auto &MO = MI.getOperand(1); if (!MO.isCImm()) return false; return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_vfp_f32imm: { const auto &MO = MI.getOperand(1); if (!MO.isFPImm()) return false; return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; llvm_unreachable("GISelPredicateCode should have returned"); return false; } case GIPFP_MI_Predicate_vfp_f64imm: { const auto &MO = MI.getOperand(1); if (!MO.isFPImm()) return false; return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; llvm_unreachable("GISelPredicateCode should have returned"); return false; } } llvm_unreachable("Unknown predicate"); return false; } ARMInstructionSelector::ComplexMatcherMemFn ARMInstructionSelector::ComplexPredicateFns[] = { nullptr, // GICP_Invalid }; // Custom renderers. enum { GICR_Invalid, GICR_renderVFPF32Imm, GICR_renderVFPF64Imm, }; ARMInstructionSelector::CustomRendererFn ARMInstructionSelector::CustomRenderers[] = { nullptr, // GICR_Invalid &ARMInstructionSelector::renderVFPF32Imm, // gi_vfp_f32imm &ARMInstructionSelector::renderVFPF64Imm, // gi_vfp_f64imm }; bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { MachineFunction &MF = *I.getParent()->getParent(); MachineRegisterInfo &MRI = MF.getRegInfo(); const PredicateBitset AvailableFeatures = getAvailableFeatures(); NewMIVector OutMIs; State.MIs.clear(); State.MIs.push_back(&I); if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { return true; } return false; } const int64_t *ARMInstructionSelector::getMatchTable() const { constexpr static int64_t MatchTable0[] = { GIM_SwitchOpcode, /*MI*/0, /*[*/35, 171, /*)*//*default:*//*Label 53*/ 102487, /*TargetOpcode::G_ADD*//*Label 0*/ 141, /*TargetOpcode::G_SUB*//*Label 1*/ 7399, /*TargetOpcode::G_MUL*//*Label 2*/ 9654, /*TargetOpcode::G_SDIV*//*Label 3*/ 10486, /*TargetOpcode::G_UDIV*//*Label 4*/ 10588, 0, 0, /*TargetOpcode::G_AND*//*Label 5*/ 10690, /*TargetOpcode::G_OR*//*Label 6*/ 13033, /*TargetOpcode::G_XOR*//*Label 7*/ 17856, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 18957, 0, 0, /*TargetOpcode::G_BITCAST*//*Label 9*/ 19251, /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 28358, /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 28605, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_INTRINSIC*//*Label 12*/ 28804, /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 13*/ 78400, /*TargetOpcode::G_ANYEXT*//*Label 14*/ 86830, /*TargetOpcode::G_TRUNC*//*Label 15*/ 86965, /*TargetOpcode::G_CONSTANT*//*Label 16*/ 87244, /*TargetOpcode::G_FCONSTANT*//*Label 17*/ 87441, 0, 0, /*TargetOpcode::G_SEXT*//*Label 18*/ 87520, 0, /*TargetOpcode::G_ZEXT*//*Label 19*/ 87655, /*TargetOpcode::G_SHL*//*Label 20*/ 88177, /*TargetOpcode::G_LSHR*//*Label 21*/ 88286, /*TargetOpcode::G_ASHR*//*Label 22*/ 88346, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_SMULH*//*Label 23*/ 88564, /*TargetOpcode::G_FADD*//*Label 24*/ 88666, /*TargetOpcode::G_FSUB*//*Label 25*/ 89436, /*TargetOpcode::G_FMUL*//*Label 26*/ 90198, /*TargetOpcode::G_FMA*//*Label 27*/ 90915, 0, /*TargetOpcode::G_FDIV*//*Label 28*/ 92276, 0, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_FNEG*//*Label 29*/ 92442, /*TargetOpcode::G_FPEXT*//*Label 30*/ 93712, /*TargetOpcode::G_FPTRUNC*//*Label 31*/ 93872, /*TargetOpcode::G_FPTOSI*//*Label 32*/ 94036, /*TargetOpcode::G_FPTOUI*//*Label 33*/ 95151, /*TargetOpcode::G_SITOFP*//*Label 34*/ 96266, /*TargetOpcode::G_UITOFP*//*Label 35*/ 96717, /*TargetOpcode::G_FABS*//*Label 36*/ 97168, 0, 0, /*TargetOpcode::G_FMINNUM*//*Label 37*/ 97571, /*TargetOpcode::G_FMAXNUM*//*Label 38*/ 97934, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_SMIN*//*Label 39*/ 98297, /*TargetOpcode::G_SMAX*//*Label 40*/ 98808, /*TargetOpcode::G_UMIN*//*Label 41*/ 99319, /*TargetOpcode::G_UMAX*//*Label 42*/ 99830, /*TargetOpcode::G_BR*//*Label 43*/ 100341, 0, 0, 0, 0, 0, 0, /*TargetOpcode::G_CTLZ*//*Label 44*/ 100405, 0, /*TargetOpcode::G_CTPOP*//*Label 45*/ 100900, /*TargetOpcode::G_BSWAP*//*Label 46*/ 100992, /*TargetOpcode::G_BITREVERSE*//*Label 47*/ 101231, /*TargetOpcode::G_FCEIL*//*Label 48*/ 101582, 0, 0, /*TargetOpcode::G_FSQRT*//*Label 49*/ 101781, /*TargetOpcode::G_FFLOOR*//*Label 50*/ 101911, /*TargetOpcode::G_FRINT*//*Label 51*/ 102110, /*TargetOpcode::G_FNEARBYINT*//*Label 52*/ 102357, // Label 0: @141 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 63*/ 7398, /*GILLT_s32*//*Label 54*/ 161, /*GILLT_s64*//*Label 55*/ 2144, /*GILLT_v2s32*//*Label 56*/ 2196, /*GILLT_v2s64*//*Label 57*/ 2663, 0, /*GILLT_v4s16*//*Label 58*/ 3392, /*GILLT_v4s32*//*Label 59*/ 3859, 0, 0, /*GILLT_v8s8*//*Label 60*/ 5121, /*GILLT_v8s16*//*Label 61*/ 5588, 0, 0, /*GILLT_v16s8*//*Label 62*/ 6850, // Label 54: @161 GIM_Try, /*On fail goto*//*Label 64*/ 2143, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 65*/ 238, // Rule ID 4388 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4388, GIR_Done, // Label 65: @238 GIM_Try, /*On fail goto*//*Label 66*/ 305, // Rule ID 4389 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4389, GIR_Done, // Label 66: @305 GIM_Try, /*On fail goto*//*Label 67*/ 372, // Rule ID 4423 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4423, GIR_Done, // Label 67: @372 GIM_Try, /*On fail goto*//*Label 68*/ 439, // Rule ID 4424 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4424, GIR_Done, // Label 68: @439 GIM_Try, /*On fail goto*//*Label 69*/ 506, // Rule ID 1990 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1990, GIR_Done, // Label 69: @506 GIM_Try, /*On fail goto*//*Label 70*/ 573, // Rule ID 1991 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1991, GIR_Done, // Label 70: @573 GIM_Try, /*On fail goto*//*Label 71*/ 640, // Rule ID 2198 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2198, GIR_Done, // Label 71: @640 GIM_Try, /*On fail goto*//*Label 72*/ 707, // Rule ID 2199 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2199, GIR_Done, // Label 72: @707 GIM_Try, /*On fail goto*//*Label 73*/ 817, // Rule ID 4170 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4170, GIR_Done, // Label 73: @817 GIM_Try, /*On fail goto*//*Label 74*/ 927, // Rule ID 4207 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4207, GIR_Done, // Label 74: @927 GIM_Try, /*On fail goto*//*Label 75*/ 1037, // Rule ID 194 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 194, GIR_Done, // Label 75: @1037 GIM_Try, /*On fail goto*//*Label 76*/ 1147, // Rule ID 527 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 527, GIR_Done, // Label 76: @1147 GIM_Try, /*On fail goto*//*Label 77*/ 1201, // Rule ID 74 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 74, GIR_Done, // Label 77: @1201 GIM_Try, /*On fail goto*//*Label 78*/ 1255, // Rule ID 413 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 413, GIR_Done, // Label 78: @1255 GIM_Try, /*On fail goto*//*Label 79*/ 1305, // Rule ID 414 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 414, GIR_Done, // Label 79: @1305 GIM_Try, /*On fail goto*//*Label 80*/ 1377, // Rule ID 173 // GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 173, GIR_Done, // Label 80: @1377 GIM_Try, /*On fail goto*//*Label 81*/ 1449, // Rule ID 174 // GIM_CheckFeatures, GIFBS_IsARM_NoV6, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 174, GIR_Done, // Label 81: @1449 GIM_Try, /*On fail goto*//*Label 82*/ 1517, // Rule ID 509 // GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 509, GIR_Done, // Label 82: @1517 GIM_Try, /*On fail goto*//*Label 83*/ 1585, // Rule ID 182 // GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 182, GIR_Done, // Label 83: @1585 GIM_Try, /*On fail goto*//*Label 84*/ 1653, // Rule ID 515 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 515, GIR_Done, // Label 84: @1653 GIM_Try, /*On fail goto*//*Label 85*/ 1725, // Rule ID 4164 // GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4164, GIR_Done, // Label 85: @1725 GIM_Try, /*On fail goto*//*Label 86*/ 1797, // Rule ID 4165 // GIM_CheckFeatures, GIFBS_IsARM_NoV6, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4165, GIR_Done, // Label 86: @1797 GIM_Try, /*On fail goto*//*Label 87*/ 1865, // Rule ID 4202 // GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4202, GIR_Done, // Label 87: @1865 GIM_Try, /*On fail goto*//*Label 88*/ 1933, // Rule ID 4166 // GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4166, GIR_Done, // Label 88: @1933 GIM_Try, /*On fail goto*//*Label 89*/ 2001, // Rule ID 4203 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4203, GIR_Done, // Label 89: @2001 GIM_Try, /*On fail goto*//*Label 90*/ 2048, // Rule ID 75 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 75, GIR_Done, // Label 90: @2048 GIM_Try, /*On fail goto*//*Label 91*/ 2095, // Rule ID 415 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 415, GIR_Done, // Label 91: @2095 GIM_Try, /*On fail goto*//*Label 92*/ 2142, // Rule ID 4184 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4184, GIR_Done, // Label 92: @2142 GIM_Reject, // Label 64: @2143 GIM_Reject, // Label 55: @2144 GIM_Try, /*On fail goto*//*Label 93*/ 2195, // Rule ID 777 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 777, GIR_Done, // Label 93: @2195 GIM_Reject, // Label 56: @2196 GIM_Try, /*On fail goto*//*Label 94*/ 2662, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 95*/ 2281, // Rule ID 4320 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4320, GIR_Done, // Label 95: @2281 GIM_Try, /*On fail goto*//*Label 96*/ 2352, // Rule ID 4326 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4326, GIR_Done, // Label 96: @2352 GIM_Try, /*On fail goto*//*Label 97*/ 2423, // Rule ID 1169 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1169, GIR_Done, // Label 97: @2423 GIM_Try, /*On fail goto*//*Label 98*/ 2494, // Rule ID 1175 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1175, GIR_Done, // Label 98: @2494 GIM_Try, /*On fail goto*//*Label 99*/ 2558, // Rule ID 4250 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4250, GIR_Done, // Label 99: @2558 GIM_Try, /*On fail goto*//*Label 100*/ 2622, // Rule ID 892 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 892, GIR_Done, // Label 100: @2622 GIM_Try, /*On fail goto*//*Label 101*/ 2661, // Rule ID 773 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 773, GIR_Done, // Label 101: @2661 GIM_Reject, // Label 94: @2662 GIM_Reject, // Label 57: @2663 GIM_Try, /*On fail goto*//*Label 102*/ 3391, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 103*/ 2761, // Rule ID 4332 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4332, GIR_Done, // Label 103: @2761 GIM_Try, /*On fail goto*//*Label 104*/ 2845, // Rule ID 4335 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4335, GIR_Done, // Label 104: @2845 GIM_Try, /*On fail goto*//*Label 105*/ 2929, // Rule ID 1181 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1181, GIR_Done, // Label 105: @2929 GIM_Try, /*On fail goto*//*Label 106*/ 3013, // Rule ID 1184 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1184, GIR_Done, // Label 106: @3013 GIM_Try, /*On fail goto*//*Label 107*/ 3078, // Rule ID 785 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 785, GIR_Done, // Label 107: @3078 GIM_Try, /*On fail goto*//*Label 108*/ 3143, // Rule ID 788 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 788, GIR_Done, // Label 108: @3143 GIM_Try, /*On fail goto*//*Label 109*/ 3195, // Rule ID 4226 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4226, GIR_Done, // Label 109: @3195 GIM_Try, /*On fail goto*//*Label 110*/ 3247, // Rule ID 4229 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4229, GIR_Done, // Label 110: @3247 GIM_Try, /*On fail goto*//*Label 111*/ 3299, // Rule ID 791 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 791, GIR_Done, // Label 111: @3299 GIM_Try, /*On fail goto*//*Label 112*/ 3351, // Rule ID 794 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 794, GIR_Done, // Label 112: @3351 GIM_Try, /*On fail goto*//*Label 113*/ 3390, // Rule ID 778 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 778, GIR_Done, // Label 113: @3390 GIM_Reject, // Label 102: @3391 GIM_Reject, // Label 58: @3392 GIM_Try, /*On fail goto*//*Label 114*/ 3858, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 115*/ 3477, // Rule ID 4319 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4319, GIR_Done, // Label 115: @3477 GIM_Try, /*On fail goto*//*Label 116*/ 3548, // Rule ID 4325 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4325, GIR_Done, // Label 116: @3548 GIM_Try, /*On fail goto*//*Label 117*/ 3619, // Rule ID 1168 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1168, GIR_Done, // Label 117: @3619 GIM_Try, /*On fail goto*//*Label 118*/ 3690, // Rule ID 1174 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1174, GIR_Done, // Label 118: @3690 GIM_Try, /*On fail goto*//*Label 119*/ 3754, // Rule ID 4249 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4249, GIR_Done, // Label 119: @3754 GIM_Try, /*On fail goto*//*Label 120*/ 3818, // Rule ID 891 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 891, GIR_Done, // Label 120: @3818 GIM_Try, /*On fail goto*//*Label 121*/ 3857, // Rule ID 772 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 772, GIR_Done, // Label 121: @3857 GIM_Reject, // Label 114: @3858 GIM_Reject, // Label 59: @3859 GIM_Try, /*On fail goto*//*Label 122*/ 5120, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 123*/ 3957, // Rule ID 4331 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4331, GIR_Done, // Label 123: @3957 GIM_Try, /*On fail goto*//*Label 124*/ 4045, // Rule ID 4334 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4334, GIR_Done, // Label 124: @4045 GIM_Try, /*On fail goto*//*Label 125*/ 4133, // Rule ID 1180 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1180, GIR_Done, // Label 125: @4133 GIM_Try, /*On fail goto*//*Label 126*/ 4221, // Rule ID 1183 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1183, GIR_Done, // Label 126: @4221 GIM_Try, /*On fail goto*//*Label 127*/ 4296, // Rule ID 4323 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4323, GIR_Done, // Label 127: @4296 GIM_Try, /*On fail goto*//*Label 128*/ 4371, // Rule ID 4329 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4329, GIR_Done, // Label 128: @4371 GIM_Try, /*On fail goto*//*Label 129*/ 4446, // Rule ID 1172 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1172, GIR_Done, // Label 129: @4446 GIM_Try, /*On fail goto*//*Label 130*/ 4521, // Rule ID 1178 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1178, GIR_Done, // Label 130: @4521 GIM_Try, /*On fail goto*//*Label 131*/ 4590, // Rule ID 784 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 784, GIR_Done, // Label 131: @4590 GIM_Try, /*On fail goto*//*Label 132*/ 4659, // Rule ID 787 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 787, GIR_Done, // Label 132: @4659 GIM_Try, /*On fail goto*//*Label 133*/ 4727, // Rule ID 4253 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4253, GIR_Done, // Label 133: @4727 GIM_Try, /*On fail goto*//*Label 134*/ 4783, // Rule ID 4225 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4225, GIR_Done, // Label 134: @4783 GIM_Try, /*On fail goto*//*Label 135*/ 4839, // Rule ID 4228 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4228, GIR_Done, // Label 135: @4839 GIM_Try, /*On fail goto*//*Label 136*/ 4907, // Rule ID 895 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 895, GIR_Done, // Label 136: @4907 GIM_Try, /*On fail goto*//*Label 137*/ 4963, // Rule ID 790 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 790, GIR_Done, // Label 137: @4963 GIM_Try, /*On fail goto*//*Label 138*/ 5019, // Rule ID 793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 793, GIR_Done, // Label 138: @5019 GIM_Try, /*On fail goto*//*Label 139*/ 5062, // Rule ID 776 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 776, GIR_Done, // Label 139: @5062 GIM_Try, /*On fail goto*//*Label 140*/ 5119, // Rule ID 3020 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3020, GIR_Done, // Label 140: @5119 GIM_Reject, // Label 122: @5120 GIM_Reject, // Label 60: @5121 GIM_Try, /*On fail goto*//*Label 141*/ 5587, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 142*/ 5206, // Rule ID 4318 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4318, GIR_Done, // Label 142: @5206 GIM_Try, /*On fail goto*//*Label 143*/ 5277, // Rule ID 4324 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4324, GIR_Done, // Label 143: @5277 GIM_Try, /*On fail goto*//*Label 144*/ 5348, // Rule ID 1167 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1167, GIR_Done, // Label 144: @5348 GIM_Try, /*On fail goto*//*Label 145*/ 5419, // Rule ID 1173 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1173, GIR_Done, // Label 145: @5419 GIM_Try, /*On fail goto*//*Label 146*/ 5483, // Rule ID 4248 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4248, GIR_Done, // Label 146: @5483 GIM_Try, /*On fail goto*//*Label 147*/ 5547, // Rule ID 890 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 890, GIR_Done, // Label 147: @5547 GIM_Try, /*On fail goto*//*Label 148*/ 5586, // Rule ID 771 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 771, GIR_Done, // Label 148: @5586 GIM_Reject, // Label 141: @5587 GIM_Reject, // Label 61: @5588 GIM_Try, /*On fail goto*//*Label 149*/ 6849, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 150*/ 5686, // Rule ID 4330 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4330, GIR_Done, // Label 150: @5686 GIM_Try, /*On fail goto*//*Label 151*/ 5774, // Rule ID 4333 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4333, GIR_Done, // Label 151: @5774 GIM_Try, /*On fail goto*//*Label 152*/ 5862, // Rule ID 1179 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1179, GIR_Done, // Label 152: @5862 GIM_Try, /*On fail goto*//*Label 153*/ 5950, // Rule ID 1182 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/2, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1182, GIR_Done, // Label 153: @5950 GIM_Try, /*On fail goto*//*Label 154*/ 6025, // Rule ID 4322 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4322, GIR_Done, // Label 154: @6025 GIM_Try, /*On fail goto*//*Label 155*/ 6100, // Rule ID 4328 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4328, GIR_Done, // Label 155: @6100 GIM_Try, /*On fail goto*//*Label 156*/ 6175, // Rule ID 1171 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1171, GIR_Done, // Label 156: @6175 GIM_Try, /*On fail goto*//*Label 157*/ 6250, // Rule ID 1177 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1177, GIR_Done, // Label 157: @6250 GIM_Try, /*On fail goto*//*Label 158*/ 6319, // Rule ID 783 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 783, GIR_Done, // Label 158: @6319 GIM_Try, /*On fail goto*//*Label 159*/ 6388, // Rule ID 786 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 786, GIR_Done, // Label 159: @6388 GIM_Try, /*On fail goto*//*Label 160*/ 6456, // Rule ID 4252 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4252, GIR_Done, // Label 160: @6456 GIM_Try, /*On fail goto*//*Label 161*/ 6512, // Rule ID 4224 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4224, GIR_Done, // Label 161: @6512 GIM_Try, /*On fail goto*//*Label 162*/ 6568, // Rule ID 4227 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4227, GIR_Done, // Label 162: @6568 GIM_Try, /*On fail goto*//*Label 163*/ 6636, // Rule ID 894 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 894, GIR_Done, // Label 163: @6636 GIM_Try, /*On fail goto*//*Label 164*/ 6692, // Rule ID 789 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 789, GIR_Done, // Label 164: @6692 GIM_Try, /*On fail goto*//*Label 165*/ 6748, // Rule ID 792 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 792, GIR_Done, // Label 165: @6748 GIM_Try, /*On fail goto*//*Label 166*/ 6791, // Rule ID 775 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 775, GIR_Done, // Label 166: @6791 GIM_Try, /*On fail goto*//*Label 167*/ 6848, // Rule ID 3018 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3018, GIR_Done, // Label 167: @6848 GIM_Reject, // Label 149: @6849 GIM_Reject, // Label 62: @6850 GIM_Try, /*On fail goto*//*Label 168*/ 7397, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 169*/ 6935, // Rule ID 4321 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4321, GIR_Done, // Label 169: @6935 GIM_Try, /*On fail goto*//*Label 170*/ 7010, // Rule ID 4327 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4327, GIR_Done, // Label 170: @7010 GIM_Try, /*On fail goto*//*Label 171*/ 7085, // Rule ID 1170 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1170, GIR_Done, // Label 171: @7085 GIM_Try, /*On fail goto*//*Label 172*/ 7160, // Rule ID 1176 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1176, GIR_Done, // Label 172: @7160 GIM_Try, /*On fail goto*//*Label 173*/ 7228, // Rule ID 4251 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4251, GIR_Done, // Label 173: @7228 GIM_Try, /*On fail goto*//*Label 174*/ 7296, // Rule ID 893 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 893, GIR_Done, // Label 174: @7296 GIM_Try, /*On fail goto*//*Label 175*/ 7339, // Rule ID 774 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 774, GIR_Done, // Label 175: @7339 GIM_Try, /*On fail goto*//*Label 176*/ 7396, // Rule ID 3016 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3016, GIR_Done, // Label 176: @7396 GIM_Reject, // Label 168: @7397 GIM_Reject, // Label 63: @7398 GIM_Reject, // Label 1: @7399 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 186*/ 9653, /*GILLT_s32*//*Label 177*/ 7419, /*GILLT_s64*//*Label 178*/ 7927, /*GILLT_v2s32*//*Label 179*/ 7979, /*GILLT_v2s64*//*Label 180*/ 8094, 0, /*GILLT_v4s16*//*Label 181*/ 8383, /*GILLT_v4s32*//*Label 182*/ 8498, 0, 0, /*GILLT_v8s8*//*Label 183*/ 8928, /*GILLT_v8s16*//*Label 184*/ 9043, 0, 0, /*GILLT_v16s8*//*Label 185*/ 9473, // Label 177: @7419 GIM_Try, /*On fail goto*//*Label 187*/ 7926, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 188*/ 7483, // Rule ID 98 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 98, GIR_Done, // Label 188: @7483 GIM_Try, /*On fail goto*//*Label 189*/ 7537, // Rule ID 433 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 433, GIR_Done, // Label 189: @7537 GIM_Try, /*On fail goto*//*Label 190*/ 7591, // Rule ID 78 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 78, GIR_Done, // Label 190: @7591 GIM_Try, /*On fail goto*//*Label 191*/ 7645, // Rule ID 417 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 417, GIR_Done, // Label 191: @7645 GIM_Try, /*On fail goto*//*Label 192*/ 7695, // Rule ID 418 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 418, GIR_Done, // Label 192: @7695 GIM_Try, /*On fail goto*//*Label 193*/ 7763, // Rule ID 175 // GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 175, GIR_Done, // Label 193: @7763 GIM_Try, /*On fail goto*//*Label 194*/ 7831, // Rule ID 510 // GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 510, GIR_Done, // Label 194: @7831 GIM_Try, /*On fail goto*//*Label 195*/ 7878, // Rule ID 79 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 79, GIR_Done, // Label 195: @7878 GIM_Try, /*On fail goto*//*Label 196*/ 7925, // Rule ID 419 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 419, GIR_Done, // Label 196: @7925 GIM_Reject, // Label 187: @7926 GIM_Reject, // Label 178: @7927 GIM_Try, /*On fail goto*//*Label 197*/ 7978, // Rule ID 964 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 964, GIR_Done, // Label 197: @7978 GIM_Reject, // Label 179: @7979 GIM_Try, /*On fail goto*//*Label 198*/ 8093, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 199*/ 8057, // Rule ID 920 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 920, GIR_Done, // Label 199: @8057 GIM_Try, /*On fail goto*//*Label 200*/ 8092, // Rule ID 960 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 960, GIR_Done, // Label 200: @8092 GIM_Reject, // Label 198: @8093 GIM_Reject, // Label 180: @8094 GIM_Try, /*On fail goto*//*Label 201*/ 8382, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 202*/ 8173, // Rule ID 972 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 972, GIR_Done, // Label 202: @8173 GIM_Try, /*On fail goto*//*Label 203*/ 8238, // Rule ID 975 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 975, GIR_Done, // Label 203: @8238 GIM_Try, /*On fail goto*//*Label 204*/ 8290, // Rule ID 978 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 978, GIR_Done, // Label 204: @8290 GIM_Try, /*On fail goto*//*Label 205*/ 8342, // Rule ID 981 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 981, GIR_Done, // Label 205: @8342 GIM_Try, /*On fail goto*//*Label 206*/ 8381, // Rule ID 965 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 965, GIR_Done, // Label 206: @8381 GIM_Reject, // Label 201: @8382 GIM_Reject, // Label 181: @8383 GIM_Try, /*On fail goto*//*Label 207*/ 8497, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 208*/ 8461, // Rule ID 919 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 919, GIR_Done, // Label 208: @8461 GIM_Try, /*On fail goto*//*Label 209*/ 8496, // Rule ID 959 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 959, GIR_Done, // Label 209: @8496 GIM_Reject, // Label 207: @8497 GIM_Reject, // Label 182: @8498 GIM_Try, /*On fail goto*//*Label 210*/ 8927, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 211*/ 8577, // Rule ID 971 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 971, GIR_Done, // Label 211: @8577 GIM_Try, /*On fail goto*//*Label 212*/ 8646, // Rule ID 974 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 974, GIR_Done, // Label 212: @8646 GIM_Try, /*On fail goto*//*Label 213*/ 8714, // Rule ID 923 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 923, GIR_Done, // Label 213: @8714 GIM_Try, /*On fail goto*//*Label 214*/ 8770, // Rule ID 977 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 977, GIR_Done, // Label 214: @8770 GIM_Try, /*On fail goto*//*Label 215*/ 8826, // Rule ID 980 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 980, GIR_Done, // Label 215: @8826 GIM_Try, /*On fail goto*//*Label 216*/ 8869, // Rule ID 963 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 963, GIR_Done, // Label 216: @8869 GIM_Try, /*On fail goto*//*Label 217*/ 8926, // Rule ID 3026 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3026, GIR_Done, // Label 217: @8926 GIM_Reject, // Label 210: @8927 GIM_Reject, // Label 183: @8928 GIM_Try, /*On fail goto*//*Label 218*/ 9042, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 219*/ 9006, // Rule ID 918 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 918, GIR_Done, // Label 219: @9006 GIM_Try, /*On fail goto*//*Label 220*/ 9041, // Rule ID 958 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 958, GIR_Done, // Label 220: @9041 GIM_Reject, // Label 218: @9042 GIM_Reject, // Label 184: @9043 GIM_Try, /*On fail goto*//*Label 221*/ 9472, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 222*/ 9122, // Rule ID 970 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 970, GIR_Done, // Label 222: @9122 GIM_Try, /*On fail goto*//*Label 223*/ 9191, // Rule ID 973 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 973, GIR_Done, // Label 223: @9191 GIM_Try, /*On fail goto*//*Label 224*/ 9259, // Rule ID 922 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 922, GIR_Done, // Label 224: @9259 GIM_Try, /*On fail goto*//*Label 225*/ 9315, // Rule ID 976 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 976, GIR_Done, // Label 225: @9315 GIM_Try, /*On fail goto*//*Label 226*/ 9371, // Rule ID 979 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 979, GIR_Done, // Label 226: @9371 GIM_Try, /*On fail goto*//*Label 227*/ 9414, // Rule ID 962 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 962, GIR_Done, // Label 227: @9414 GIM_Try, /*On fail goto*//*Label 228*/ 9471, // Rule ID 3024 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3024, GIR_Done, // Label 228: @9471 GIM_Reject, // Label 221: @9472 GIM_Reject, // Label 185: @9473 GIM_Try, /*On fail goto*//*Label 229*/ 9652, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 230*/ 9551, // Rule ID 921 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 921, GIR_Done, // Label 230: @9551 GIM_Try, /*On fail goto*//*Label 231*/ 9594, // Rule ID 961 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 961, GIR_Done, // Label 231: @9594 GIM_Try, /*On fail goto*//*Label 232*/ 9651, // Rule ID 3022 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3022, GIR_Done, // Label 232: @9651 GIM_Reject, // Label 229: @9652 GIM_Reject, // Label 186: @9653 GIM_Reject, // Label 2: @9654 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 240*/ 10485, /*GILLT_s32*//*Label 233*/ 9674, 0, /*GILLT_v2s32*//*Label 234*/ 9993, 0, 0, /*GILLT_v4s16*//*Label 235*/ 10045, /*GILLT_v4s32*//*Label 236*/ 10097, 0, 0, /*GILLT_v8s8*//*Label 237*/ 10209, /*GILLT_v8s16*//*Label 238*/ 10261, 0, 0, /*GILLT_v16s8*//*Label 239*/ 10373, // Label 233: @9674 GIM_Try, /*On fail goto*//*Label 241*/ 9992, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 242*/ 9769, // Rule ID 188 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 188, GIR_Done, // Label 242: @9769 GIM_Try, /*On fail goto*//*Label 243*/ 9854, // Rule ID 521 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 521, GIR_Done, // Label 243: @9854 GIM_Try, /*On fail goto*//*Label 244*/ 9901, // Rule ID 171 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 171, GIR_Done, // Label 244: @9901 GIM_Try, /*On fail goto*//*Label 245*/ 9948, // Rule ID 172 // GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 172, GIR_Done, // Label 245: @9948 GIM_Try, /*On fail goto*//*Label 246*/ 9991, // Rule ID 508 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 508, GIR_Done, // Label 246: @9991 GIM_Reject, // Label 241: @9992 GIM_Reject, // Label 234: @9993 GIM_Try, /*On fail goto*//*Label 247*/ 10044, // Rule ID 840 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 840, GIR_Done, // Label 247: @10044 GIM_Reject, // Label 235: @10045 GIM_Try, /*On fail goto*//*Label 248*/ 10096, // Rule ID 839 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 839, GIR_Done, // Label 248: @10096 GIM_Reject, // Label 236: @10097 GIM_Try, /*On fail goto*//*Label 249*/ 10208, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 250*/ 10150, // Rule ID 843 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 843, GIR_Done, // Label 250: @10150 GIM_Try, /*On fail goto*//*Label 251*/ 10207, // Rule ID 3002 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3002, GIR_Done, // Label 251: @10207 GIM_Reject, // Label 249: @10208 GIM_Reject, // Label 237: @10209 GIM_Try, /*On fail goto*//*Label 252*/ 10260, // Rule ID 838 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 838, GIR_Done, // Label 252: @10260 GIM_Reject, // Label 238: @10261 GIM_Try, /*On fail goto*//*Label 253*/ 10372, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 254*/ 10314, // Rule ID 842 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 842, GIR_Done, // Label 254: @10314 GIM_Try, /*On fail goto*//*Label 255*/ 10371, // Rule ID 3000 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3000, GIR_Done, // Label 255: @10371 GIM_Reject, // Label 253: @10372 GIM_Reject, // Label 239: @10373 GIM_Try, /*On fail goto*//*Label 256*/ 10484, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 257*/ 10426, // Rule ID 841 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 841, GIR_Done, // Label 257: @10426 GIM_Try, /*On fail goto*//*Label 258*/ 10483, // Rule ID 2998 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2998, GIR_Done, // Label 258: @10483 GIM_Reject, // Label 256: @10484 GIM_Reject, // Label 240: @10485 GIM_Reject, // Label 3: @10486 GIM_Try, /*On fail goto*//*Label 259*/ 10587, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 260*/ 10543, // Rule ID 197 // GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 197, GIR_Done, // Label 260: @10543 GIM_Try, /*On fail goto*//*Label 261*/ 10586, // Rule ID 538 // GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 538, GIR_Done, // Label 261: @10586 GIM_Reject, // Label 259: @10587 GIM_Reject, // Label 4: @10588 GIM_Try, /*On fail goto*//*Label 262*/ 10689, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 263*/ 10645, // Rule ID 198 // GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 198, GIR_Done, // Label 263: @10645 GIM_Try, /*On fail goto*//*Label 264*/ 10688, // Rule ID 539 // GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 539, GIR_Done, // Label 264: @10688 GIM_Reject, // Label 262: @10689 GIM_Reject, // Label 5: @10690 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 274*/ 13032, /*GILLT_s32*//*Label 265*/ 10710, 0, /*GILLT_v2s32*//*Label 266*/ 12352, /*GILLT_v2s64*//*Label 267*/ 12404, /*GILLT_v4s1*//*Label 268*/ 12470, 0, /*GILLT_v4s32*//*Label 269*/ 12576, 0, /*GILLT_v8s1*//*Label 270*/ 12688, 0, /*GILLT_v8s16*//*Label 271*/ 12794, 0, /*GILLT_v16s1*//*Label 272*/ 12860, /*GILLT_v16s8*//*Label 273*/ 12966, // Label 265: @10710 GIM_Try, /*On fail goto*//*Label 275*/ 12351, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 276*/ 10783, // Rule ID 1868 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1868, GIR_Done, // Label 276: @10783 GIM_Try, /*On fail goto*//*Label 277*/ 10846, // Rule ID 2094 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2094, GIR_Done, // Label 277: @10846 GIM_Try, /*On fail goto*//*Label 278*/ 10888, // Rule ID 1987 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1987, GIR_Done, // Label 278: @10888 GIM_Try, /*On fail goto*//*Label 279*/ 10930, // Rule ID 1988 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1988, GIR_Done, // Label 279: @10930 GIM_Try, /*On fail goto*//*Label 280*/ 10972, // Rule ID 1989 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1989, GIR_Done, // Label 280: @10972 GIM_Try, /*On fail goto*//*Label 281*/ 11014, // Rule ID 2195 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2195, GIR_Done, // Label 281: @11014 GIM_Try, /*On fail goto*//*Label 282*/ 11056, // Rule ID 2196 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2196, GIR_Done, // Label 282: @11056 GIM_Try, /*On fail goto*//*Label 283*/ 11098, // Rule ID 2197 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2197, GIR_Done, // Label 283: @11098 GIM_Try, /*On fail goto*//*Label 284*/ 11173, // Rule ID 4160 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4160, GIR_Done, // Label 284: @11173 GIM_Try, /*On fail goto*//*Label 285*/ 11248, // Rule ID 4193 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4193, GIR_Done, // Label 285: @11248 GIM_Try, /*On fail goto*//*Label 286*/ 11323, // Rule ID 4159 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4159, GIR_Done, // Label 286: @11323 GIM_Try, /*On fail goto*//*Label 287*/ 11398, // Rule ID 4192 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4192, GIR_Done, // Label 287: @11398 GIM_Try, /*On fail goto*//*Label 288*/ 11473, // Rule ID 4158 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4158, GIR_Done, // Label 288: @11473 GIM_Try, /*On fail goto*//*Label 289*/ 11548, // Rule ID 4191 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4191, GIR_Done, // Label 289: @11548 GIM_Try, /*On fail goto*//*Label 290*/ 11623, // Rule ID 161 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 161, GIR_Done, // Label 290: @11623 GIM_Try, /*On fail goto*//*Label 291*/ 11698, // Rule ID 496 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 496, GIR_Done, // Label 291: @11698 GIM_Try, /*On fail goto*//*Label 292*/ 11766, // Rule ID 4161 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4161, GIR_Done, // Label 292: @11766 GIM_Try, /*On fail goto*//*Label 293*/ 11834, // Rule ID 4194 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4194, GIR_Done, // Label 293: @11834 GIM_Try, /*On fail goto*//*Label 294*/ 11902, // Rule ID 162 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 162, GIR_Done, // Label 294: @11902 GIM_Try, /*On fail goto*//*Label 295*/ 11970, // Rule ID 497 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 497, GIR_Done, // Label 295: @11970 GIM_Try, /*On fail goto*//*Label 296*/ 12009, // Rule ID 353 // GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 353, GIR_Done, // Label 296: @12009 GIM_Try, /*On fail goto*//*Label 297*/ 12048, // Rule ID 354 // GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 354, GIR_Done, // Label 297: @12048 GIM_Try, /*On fail goto*//*Label 298*/ 12102, // Rule ID 149 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 149, GIR_Done, // Label 298: @12102 GIM_Try, /*On fail goto*//*Label 299*/ 12156, // Rule ID 487 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 487, GIR_Done, // Label 299: @12156 GIM_Try, /*On fail goto*//*Label 300*/ 12206, // Rule ID 165 // GIM_CheckFeatures, GIFBS_HasV6T2_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 165, GIR_Done, // Label 300: @12206 GIM_Try, /*On fail goto*//*Label 301*/ 12256, // Rule ID 499 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 499, GIR_Done, // Label 301: @12256 GIM_Try, /*On fail goto*//*Label 302*/ 12303, // Rule ID 150 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 150, GIR_Done, // Label 302: @12303 GIM_Try, /*On fail goto*//*Label 303*/ 12350, // Rule ID 488 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 488, GIR_Done, // Label 303: @12350 GIM_Reject, // Label 275: @12351 GIM_Reject, // Label 266: @12352 GIM_Try, /*On fail goto*//*Label 304*/ 12403, // Rule ID 1119 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1119, GIR_Done, // Label 304: @12403 GIM_Reject, // Label 267: @12404 GIM_Try, /*On fail goto*//*Label 305*/ 12469, // Rule ID 2942 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2942, GIR_Done, // Label 305: @12469 GIM_Reject, // Label 268: @12470 GIM_Try, /*On fail goto*//*Label 306*/ 12575, // Rule ID 1847 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1847, GIR_Done, // Label 306: @12575 GIM_Reject, // Label 269: @12576 GIM_Try, /*On fail goto*//*Label 307*/ 12687, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 308*/ 12629, // Rule ID 1120 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1120, GIR_Done, // Label 308: @12629 GIM_Try, /*On fail goto*//*Label 309*/ 12686, // Rule ID 2940 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2940, GIR_Done, // Label 309: @12686 GIM_Reject, // Label 307: @12687 GIM_Reject, // Label 270: @12688 GIM_Try, /*On fail goto*//*Label 310*/ 12793, // Rule ID 1848 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1848, GIR_Done, // Label 310: @12793 GIM_Reject, // Label 271: @12794 GIM_Try, /*On fail goto*//*Label 311*/ 12859, // Rule ID 2938 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2938, GIR_Done, // Label 311: @12859 GIM_Reject, // Label 272: @12860 GIM_Try, /*On fail goto*//*Label 312*/ 12965, // Rule ID 1846 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1846, GIR_Done, // Label 312: @12965 GIM_Reject, // Label 273: @12966 GIM_Try, /*On fail goto*//*Label 313*/ 13031, // Rule ID 2936 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2936, GIR_Done, // Label 313: @13031 GIM_Reject, // Label 274: @13032 GIM_Reject, // Label 6: @13033 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 323*/ 17855, /*GILLT_s32*//*Label 314*/ 13053, 0, /*GILLT_v2s32*//*Label 315*/ 17175, /*GILLT_v2s64*//*Label 316*/ 17227, /*GILLT_v4s1*//*Label 317*/ 17293, 0, /*GILLT_v4s32*//*Label 318*/ 17399, 0, /*GILLT_v8s1*//*Label 319*/ 17511, 0, /*GILLT_v8s16*//*Label 320*/ 17617, 0, /*GILLT_v16s1*//*Label 321*/ 17683, /*GILLT_v16s8*//*Label 322*/ 17789, // Label 314: @13053 GIM_Try, /*On fail goto*//*Label 324*/ 17174, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 325*/ 13183, // Rule ID 4373 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4373, GIR_Done, // Label 325: @13183 GIM_Try, /*On fail goto*//*Label 326*/ 13303, // Rule ID 4415 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4415, GIR_Done, // Label 326: @13303 GIM_Try, /*On fail goto*//*Label 327*/ 13423, // Rule ID 1918 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1918, GIR_Done, // Label 327: @13423 GIM_Try, /*On fail goto*//*Label 328*/ 13543, // Rule ID 2168 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16, GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, // MIs[4] Rm GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2168, GIR_Done, // Label 328: @13543 GIM_Try, /*On fail goto*//*Label 329*/ 13660, // Rule ID 4174 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4174, GIR_Done, // Label 329: @13660 GIM_Try, /*On fail goto*//*Label 330*/ 13777, // Rule ID 4211 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4211, GIR_Done, // Label 330: @13777 GIM_Try, /*On fail goto*//*Label 331*/ 13894, // Rule ID 4378 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4378, GIR_Done, // Label 331: @13894 GIM_Try, /*On fail goto*//*Label 332*/ 14011, // Rule ID 4420 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4420, GIR_Done, // Label 332: @14011 GIM_Try, /*On fail goto*//*Label 333*/ 14128, // Rule ID 4173 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4173, GIR_Done, // Label 333: @14128 GIM_Try, /*On fail goto*//*Label 334*/ 14245, // Rule ID 4210 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt, // MIs[3] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND, GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4210, GIR_Done, // Label 334: @14245 GIM_Try, /*On fail goto*//*Label 335*/ 14362, // Rule ID 205 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 205, GIR_Done, // Label 335: @14362 GIM_Try, /*On fail goto*//*Label 336*/ 14479, // Rule ID 546 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 546, GIR_Done, // Label 336: @14479 GIM_Try, /*On fail goto*//*Label 337*/ 14596, // Rule ID 1923 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1923, GIR_Done, // Label 337: @14596 GIM_Try, /*On fail goto*//*Label 338*/ 14713, // Rule ID 2173 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2173, GIR_Done, // Label 338: @14713 GIM_Try, /*On fail goto*//*Label 339*/ 14830, // Rule ID 204 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 204, GIR_Done, // Label 339: @14830 GIM_Try, /*On fail goto*//*Label 340*/ 14947, // Rule ID 545 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt, // MIs[4] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, GIM_CheckIsSafeToFold, /*InsnID*/4, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 545, GIR_Done, // Label 340: @14947 GIM_Try, /*On fail goto*//*Label 341*/ 15035, // Rule ID 1919 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1919, GIR_Done, // Label 341: @15035 GIM_Try, /*On fail goto*//*Label 342*/ 15123, // Rule ID 2169 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2169, GIR_Done, // Label 342: @15123 GIM_Try, /*On fail goto*//*Label 343*/ 15211, // Rule ID 4374 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4374, GIR_Done, // Label 343: @15211 GIM_Try, /*On fail goto*//*Label 344*/ 15299, // Rule ID 4416 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4416, GIR_Done, // Label 344: @15299 GIM_Try, /*On fail goto*//*Label 345*/ 15395, // Rule ID 1922 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1922, GIR_Done, // Label 345: @15395 GIM_Try, /*On fail goto*//*Label 346*/ 15491, // Rule ID 2172 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2172, GIR_Done, // Label 346: @15491 GIM_Try, /*On fail goto*//*Label 347*/ 15587, // Rule ID 1921 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1921, GIR_Done, // Label 347: @15587 GIM_Try, /*On fail goto*//*Label 348*/ 15683, // Rule ID 2171 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2171, GIR_Done, // Label 348: @15683 GIM_Try, /*On fail goto*//*Label 349*/ 15779, // Rule ID 1920 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1920, GIR_Done, // Label 349: @15779 GIM_Try, /*On fail goto*//*Label 350*/ 15875, // Rule ID 2170 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[3] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2170, GIR_Done, // Label 350: @15875 GIM_Try, /*On fail goto*//*Label 351*/ 15971, // Rule ID 4377 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4377, GIR_Done, // Label 351: @15971 GIM_Try, /*On fail goto*//*Label 352*/ 16067, // Rule ID 4419 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4419, GIR_Done, // Label 352: @16067 GIM_Try, /*On fail goto*//*Label 353*/ 16163, // Rule ID 4376 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4376, GIR_Done, // Label 353: @16163 GIM_Try, /*On fail goto*//*Label 354*/ 16259, // Rule ID 4418 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4418, GIR_Done, // Label 354: @16259 GIM_Try, /*On fail goto*//*Label 355*/ 16355, // Rule ID 4375 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4375, GIR_Done, // Label 355: @16355 GIM_Try, /*On fail goto*//*Label 356*/ 16451, // Rule ID 4417 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31, // MIs[2] Operand 1 // No operand predicates GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, GIM_CheckIsSafeToFold, /*InsnID*/3, // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<>:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4417, GIR_Done, // Label 356: @16451 GIM_Try, /*On fail goto*//*Label 357*/ 16526, // Rule ID 4198 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4198, GIR_Done, // Label 357: @16526 GIM_Try, /*On fail goto*//*Label 358*/ 16601, // Rule ID 4197 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4197, GIR_Done, // Label 358: @16601 GIM_Try, /*On fail goto*//*Label 359*/ 16676, // Rule ID 4196 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4196, GIR_Done, // Label 359: @16676 GIM_Try, /*On fail goto*//*Label 360*/ 16751, // Rule ID 502 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[2] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 502, GIR_Done, // Label 360: @16751 GIM_Try, /*On fail goto*//*Label 361*/ 16819, // Rule ID 4199 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4199, GIR_Done, // Label 361: @16819 GIM_Try, /*On fail goto*//*Label 362*/ 16887, // Rule ID 503 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 503, GIR_Done, // Label 362: @16887 GIM_Try, /*On fail goto*//*Label 363*/ 16929, // Rule ID 1861 // GIM_CheckFeatures, GIFBS_HasV6T2_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760, // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/65535, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1861, GIR_Done, // Label 363: @16929 GIM_Try, /*On fail goto*//*Label 364*/ 16971, // Rule ID 2076 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/65535, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2076, GIR_Done, // Label 364: @16971 GIM_Try, /*On fail goto*//*Label 365*/ 17025, // Rule ID 153 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 153, GIR_Done, // Label 365: @17025 GIM_Try, /*On fail goto*//*Label 366*/ 17079, // Rule ID 490 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 490, GIR_Done, // Label 366: @17079 GIM_Try, /*On fail goto*//*Label 367*/ 17126, // Rule ID 154 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 154, GIR_Done, // Label 367: @17126 GIM_Try, /*On fail goto*//*Label 368*/ 17173, // Rule ID 491 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 491, GIR_Done, // Label 368: @17173 GIM_Reject, // Label 324: @17174 GIM_Reject, // Label 315: @17175 GIM_Try, /*On fail goto*//*Label 369*/ 17226, // Rule ID 1123 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1123, GIR_Done, // Label 369: @17226 GIM_Reject, // Label 316: @17227 GIM_Try, /*On fail goto*//*Label 370*/ 17292, // Rule ID 2950 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2950, GIR_Done, // Label 370: @17292 GIM_Reject, // Label 317: @17293 GIM_Try, /*On fail goto*//*Label 371*/ 17398, // Rule ID 1853 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1853, GIR_Done, // Label 371: @17398 GIM_Reject, // Label 318: @17399 GIM_Try, /*On fail goto*//*Label 372*/ 17510, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 373*/ 17452, // Rule ID 1124 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1124, GIR_Done, // Label 373: @17452 GIM_Try, /*On fail goto*//*Label 374*/ 17509, // Rule ID 2948 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2948, GIR_Done, // Label 374: @17509 GIM_Reject, // Label 372: @17510 GIM_Reject, // Label 319: @17511 GIM_Try, /*On fail goto*//*Label 375*/ 17616, // Rule ID 1854 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1854, GIR_Done, // Label 375: @17616 GIM_Reject, // Label 320: @17617 GIM_Try, /*On fail goto*//*Label 376*/ 17682, // Rule ID 2946 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2946, GIR_Done, // Label 376: @17682 GIM_Reject, // Label 321: @17683 GIM_Try, /*On fail goto*//*Label 377*/ 17788, // Rule ID 1852 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1852, GIR_Done, // Label 377: @17788 GIM_Reject, // Label 322: @17789 GIM_Try, /*On fail goto*//*Label 378*/ 17854, // Rule ID 2944 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2944, GIR_Done, // Label 378: @17854 GIM_Reject, // Label 323: @17855 GIM_Reject, // Label 7: @17856 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 388*/ 18956, /*GILLT_s32*//*Label 379*/ 17876, 0, /*GILLT_v2s32*//*Label 380*/ 18276, /*GILLT_v2s64*//*Label 381*/ 18328, /*GILLT_v4s1*//*Label 382*/ 18394, 0, /*GILLT_v4s32*//*Label 383*/ 18500, 0, /*GILLT_v8s1*//*Label 384*/ 18612, 0, /*GILLT_v8s16*//*Label 385*/ 18718, 0, /*GILLT_v16s1*//*Label 386*/ 18784, /*GILLT_v16s8*//*Label 387*/ 18890, // Label 379: @17876 GIM_Try, /*On fail goto*//*Label 389*/ 18275, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 390*/ 17936, // Rule ID 4201 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, -1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4201, GIR_Done, // Label 390: @17936 GIM_Try, /*On fail goto*//*Label 391*/ 17986, // Rule ID 505 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } (imm:{ *:[i32] })<>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 505, GIR_Done, // Label 391: @17986 GIM_Try, /*On fail goto*//*Label 392*/ 18029, // Rule ID 506 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 506, GIR_Done, // Label 392: @18029 GIM_Try, /*On fail goto*//*Label 393*/ 18072, // Rule ID 167 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 167, GIR_Done, // Label 393: @18072 GIM_Try, /*On fail goto*//*Label 394*/ 18126, // Rule ID 157 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 157, GIR_Done, // Label 394: @18126 GIM_Try, /*On fail goto*//*Label 395*/ 18180, // Rule ID 493 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 493, GIR_Done, // Label 395: @18180 GIM_Try, /*On fail goto*//*Label 396*/ 18227, // Rule ID 158 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 158, GIR_Done, // Label 396: @18227 GIM_Try, /*On fail goto*//*Label 397*/ 18274, // Rule ID 494 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 494, GIR_Done, // Label 397: @18274 GIM_Reject, // Label 389: @18275 GIM_Reject, // Label 380: @18276 GIM_Try, /*On fail goto*//*Label 398*/ 18327, // Rule ID 1121 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1121, GIR_Done, // Label 398: @18327 GIM_Reject, // Label 381: @18328 GIM_Try, /*On fail goto*//*Label 399*/ 18393, // Rule ID 2958 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2958, GIR_Done, // Label 399: @18393 GIM_Reject, // Label 382: @18394 GIM_Try, /*On fail goto*//*Label 400*/ 18499, // Rule ID 1850 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1850, GIR_Done, // Label 400: @18499 GIM_Reject, // Label 383: @18500 GIM_Try, /*On fail goto*//*Label 401*/ 18611, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 402*/ 18553, // Rule ID 1122 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1122, GIR_Done, // Label 402: @18553 GIM_Try, /*On fail goto*//*Label 403*/ 18610, // Rule ID 2956 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2956, GIR_Done, // Label 403: @18610 GIM_Reject, // Label 401: @18611 GIM_Reject, // Label 384: @18612 GIM_Try, /*On fail goto*//*Label 404*/ 18717, // Rule ID 1851 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1851, GIR_Done, // Label 404: @18717 GIM_Reject, // Label 385: @18718 GIM_Try, /*On fail goto*//*Label 405*/ 18783, // Rule ID 2954 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2954, GIR_Done, // Label 405: @18783 GIM_Reject, // Label 386: @18784 GIM_Try, /*On fail goto*//*Label 406*/ 18889, // Rule ID 1849 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID, // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VCCR*/32, // GIR_Coverage, 1849, GIR_Done, // Label 406: @18889 GIM_Reject, // Label 387: @18890 GIM_Try, /*On fail goto*//*Label 407*/ 18955, // Rule ID 2952 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2952, GIR_Done, // Label 407: @18955 GIM_Reject, // Label 388: @18956 GIM_Reject, // Label 8: @18957 GIM_Try, /*On fail goto*//*Label 408*/ 19250, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 15, /*)*//*default:*//*Label 413*/ 19249, /*GILLT_v2s64*//*Label 409*/ 18979, 0, 0, /*GILLT_v4s32*//*Label 410*/ 19030, 0, 0, 0, /*GILLT_v8s16*//*Label 411*/ 19114, 0, 0, /*GILLT_v16s8*//*Label 412*/ 19198, // Label 409: @18979 GIM_Try, /*On fail goto*//*Label 414*/ 19029, // Rule ID 2793 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2793, GIR_Done, // Label 414: @19029 GIM_Reject, // Label 410: @19030 GIM_Try, /*On fail goto*//*Label 415*/ 19113, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 416*/ 19082, // Rule ID 2794 // GIM_CheckFeatures, GIFBS_HasNEON, // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2794, GIR_Done, // Label 416: @19082 GIM_Try, /*On fail goto*//*Label 417*/ 19112, // Rule ID 2797 // GIM_CheckFeatures, GIFBS_HasNEON, // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2797, GIR_Done, // Label 417: @19112 GIM_Reject, // Label 415: @19113 GIM_Reject, // Label 411: @19114 GIM_Try, /*On fail goto*//*Label 418*/ 19197, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 419*/ 19166, // Rule ID 2795 // GIM_CheckFeatures, GIFBS_HasNEON, // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2795, GIR_Done, // Label 419: @19166 GIM_Try, /*On fail goto*//*Label 420*/ 19196, // Rule ID 2798 // GIM_CheckFeatures, GIFBS_HasNEON, // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2798, GIR_Done, // Label 420: @19196 GIM_Reject, // Label 418: @19197 GIM_Reject, // Label 412: @19198 GIM_Try, /*On fail goto*//*Label 421*/ 19248, // Rule ID 2796 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2796, GIR_Done, // Label 421: @19248 GIM_Reject, // Label 413: @19249 GIM_Reject, // Label 408: @19250 GIM_Reject, // Label 9: @19251 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 431*/ 28357, /*GILLT_s32*//*Label 422*/ 19271, /*GILLT_s64*//*Label 423*/ 19349, /*GILLT_v2s32*//*Label 424*/ 20148, /*GILLT_v2s64*//*Label 425*/ 20947, 0, /*GILLT_v4s16*//*Label 426*/ 22684, /*GILLT_v4s32*//*Label 427*/ 23483, 0, 0, /*GILLT_v8s8*//*Label 428*/ 25220, /*GILLT_v8s16*//*Label 429*/ 25659, 0, 0, /*GILLT_v16s8*//*Label 430*/ 27396, // Label 422: @19271 GIM_Try, /*On fail goto*//*Label 432*/ 19348, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 433*/ 19312, // Rule ID 702 // GIM_CheckFeatures, GIFBS_HasFPRegs, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 702, GIR_Done, // Label 433: @19312 GIM_Try, /*On fail goto*//*Label 434*/ 19347, // Rule ID 703 // GIM_CheckFeatures, GIFBS_HasFPRegs_UseVMOVSR, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 703, GIR_Done, // Label 434: @19347 GIM_Reject, // Label 432: @19348 GIM_Reject, // Label 423: @19349 GIM_Try, /*On fail goto*//*Label 435*/ 19383, // Rule ID 2587 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2587, GIR_Done, // Label 435: @19383 GIM_Try, /*On fail goto*//*Label 436*/ 19417, // Rule ID 2588 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2588, GIR_Done, // Label 436: @19417 GIM_Try, /*On fail goto*//*Label 437*/ 19451, // Rule ID 2599 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2599, GIR_Done, // Label 437: @19451 GIM_Try, /*On fail goto*//*Label 438*/ 19485, // Rule ID 2600 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2600, GIR_Done, // Label 438: @19485 GIM_Try, /*On fail goto*//*Label 439*/ 19519, // Rule ID 2601 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2601, GIR_Done, // Label 439: @19519 GIM_Try, /*On fail goto*//*Label 440*/ 19553, // Rule ID 2602 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2602, GIR_Done, // Label 440: @19553 GIM_Try, /*On fail goto*//*Label 441*/ 19587, // Rule ID 2603 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2603, GIR_Done, // Label 441: @19587 GIM_Try, /*On fail goto*//*Label 442*/ 19621, // Rule ID 2604 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2604, GIR_Done, // Label 442: @19621 GIM_Try, /*On fail goto*//*Label 443*/ 19655, // Rule ID 2605 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2605, GIR_Done, // Label 443: @19655 GIM_Try, /*On fail goto*//*Label 444*/ 19689, // Rule ID 2606 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2606, GIR_Done, // Label 444: @19689 GIM_Try, /*On fail goto*//*Label 445*/ 19723, // Rule ID 2607 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2607, GIR_Done, // Label 445: @19723 GIM_Try, /*On fail goto*//*Label 446*/ 19757, // Rule ID 2608 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2608, GIR_Done, // Label 446: @19757 GIM_Try, /*On fail goto*//*Label 447*/ 19796, // Rule ID 2671 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2671, GIR_Done, // Label 447: @19796 GIM_Try, /*On fail goto*//*Label 448*/ 19835, // Rule ID 2672 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2672, GIR_Done, // Label 448: @19835 GIM_Try, /*On fail goto*//*Label 449*/ 19874, // Rule ID 2673 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2673, GIR_Done, // Label 449: @19874 GIM_Try, /*On fail goto*//*Label 450*/ 19913, // Rule ID 2674 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2674, GIR_Done, // Label 450: @19913 GIM_Try, /*On fail goto*//*Label 451*/ 19952, // Rule ID 2675 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2675, GIR_Done, // Label 451: @19952 GIM_Try, /*On fail goto*//*Label 452*/ 19991, // Rule ID 2676 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2676, GIR_Done, // Label 452: @19991 GIM_Try, /*On fail goto*//*Label 453*/ 20030, // Rule ID 2677 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2677, GIR_Done, // Label 453: @20030 GIM_Try, /*On fail goto*//*Label 454*/ 20069, // Rule ID 2678 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2678, GIR_Done, // Label 454: @20069 GIM_Try, /*On fail goto*//*Label 455*/ 20108, // Rule ID 2679 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2679, GIR_Done, // Label 455: @20108 GIM_Try, /*On fail goto*//*Label 456*/ 20147, // Rule ID 2680 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2680, GIR_Done, // Label 456: @20147 GIM_Reject, // Label 424: @20148 GIM_Try, /*On fail goto*//*Label 457*/ 20182, // Rule ID 2589 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2589, GIR_Done, // Label 457: @20182 GIM_Try, /*On fail goto*//*Label 458*/ 20216, // Rule ID 2590 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2590, GIR_Done, // Label 458: @20216 GIM_Try, /*On fail goto*//*Label 459*/ 20250, // Rule ID 2609 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2609, GIR_Done, // Label 459: @20250 GIM_Try, /*On fail goto*//*Label 460*/ 20284, // Rule ID 2610 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2610, GIR_Done, // Label 460: @20284 GIM_Try, /*On fail goto*//*Label 461*/ 20318, // Rule ID 2611 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2611, GIR_Done, // Label 461: @20318 GIM_Try, /*On fail goto*//*Label 462*/ 20352, // Rule ID 2612 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2612, GIR_Done, // Label 462: @20352 GIM_Try, /*On fail goto*//*Label 463*/ 20386, // Rule ID 2613 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2613, GIR_Done, // Label 463: @20386 GIM_Try, /*On fail goto*//*Label 464*/ 20420, // Rule ID 2614 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2614, GIR_Done, // Label 464: @20420 GIM_Try, /*On fail goto*//*Label 465*/ 20454, // Rule ID 2615 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2615, GIR_Done, // Label 465: @20454 GIM_Try, /*On fail goto*//*Label 466*/ 20488, // Rule ID 2616 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2616, GIR_Done, // Label 466: @20488 GIM_Try, /*On fail goto*//*Label 467*/ 20522, // Rule ID 2617 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2617, GIR_Done, // Label 467: @20522 GIM_Try, /*On fail goto*//*Label 468*/ 20556, // Rule ID 2618 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2618, GIR_Done, // Label 468: @20556 GIM_Try, /*On fail goto*//*Label 469*/ 20595, // Rule ID 2681 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2681, GIR_Done, // Label 469: @20595 GIM_Try, /*On fail goto*//*Label 470*/ 20634, // Rule ID 2682 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2682, GIR_Done, // Label 470: @20634 GIM_Try, /*On fail goto*//*Label 471*/ 20673, // Rule ID 2683 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2683, GIR_Done, // Label 471: @20673 GIM_Try, /*On fail goto*//*Label 472*/ 20712, // Rule ID 2684 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2684, GIR_Done, // Label 472: @20712 GIM_Try, /*On fail goto*//*Label 473*/ 20751, // Rule ID 2685 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2685, GIR_Done, // Label 473: @20751 GIM_Try, /*On fail goto*//*Label 474*/ 20790, // Rule ID 2686 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2686, GIR_Done, // Label 474: @20790 GIM_Try, /*On fail goto*//*Label 475*/ 20829, // Rule ID 2687 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2687, GIR_Done, // Label 475: @20829 GIM_Try, /*On fail goto*//*Label 476*/ 20868, // Rule ID 2688 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2688, GIR_Done, // Label 476: @20868 GIM_Try, /*On fail goto*//*Label 477*/ 20907, // Rule ID 2689 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2689, GIR_Done, // Label 477: @20907 GIM_Try, /*On fail goto*//*Label 478*/ 20946, // Rule ID 2690 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2690, GIR_Done, // Label 478: @20946 GIM_Reject, // Label 425: @20947 GIM_Try, /*On fail goto*//*Label 479*/ 20981, // Rule ID 2593 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2593, GIR_Done, // Label 479: @20981 GIM_Try, /*On fail goto*//*Label 480*/ 21015, // Rule ID 2594 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2594, GIR_Done, // Label 480: @21015 GIM_Try, /*On fail goto*//*Label 481*/ 21049, // Rule ID 2635 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2635, GIR_Done, // Label 481: @21049 GIM_Try, /*On fail goto*//*Label 482*/ 21083, // Rule ID 2636 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2636, GIR_Done, // Label 482: @21083 GIM_Try, /*On fail goto*//*Label 483*/ 21117, // Rule ID 2637 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2637, GIR_Done, // Label 483: @21117 GIM_Try, /*On fail goto*//*Label 484*/ 21151, // Rule ID 2638 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2638, GIR_Done, // Label 484: @21151 GIM_Try, /*On fail goto*//*Label 485*/ 21185, // Rule ID 2639 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2639, GIR_Done, // Label 485: @21185 GIM_Try, /*On fail goto*//*Label 486*/ 21219, // Rule ID 2640 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2640, GIR_Done, // Label 486: @21219 GIM_Try, /*On fail goto*//*Label 487*/ 21253, // Rule ID 2641 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2641, GIR_Done, // Label 487: @21253 GIM_Try, /*On fail goto*//*Label 488*/ 21287, // Rule ID 2642 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2642, GIR_Done, // Label 488: @21287 GIM_Try, /*On fail goto*//*Label 489*/ 21321, // Rule ID 2643 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2643, GIR_Done, // Label 489: @21321 GIM_Try, /*On fail goto*//*Label 490*/ 21355, // Rule ID 2644 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2644, GIR_Done, // Label 490: @21355 GIM_Try, /*On fail goto*//*Label 491*/ 21394, // Rule ID 2707 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2707, GIR_Done, // Label 491: @21394 GIM_Try, /*On fail goto*//*Label 492*/ 21433, // Rule ID 2708 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2708, GIR_Done, // Label 492: @21433 GIM_Try, /*On fail goto*//*Label 493*/ 21472, // Rule ID 2709 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2709, GIR_Done, // Label 493: @21472 GIM_Try, /*On fail goto*//*Label 494*/ 21511, // Rule ID 2710 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2710, GIR_Done, // Label 494: @21511 GIM_Try, /*On fail goto*//*Label 495*/ 21550, // Rule ID 2711 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2711, GIR_Done, // Label 495: @21550 GIM_Try, /*On fail goto*//*Label 496*/ 21589, // Rule ID 2712 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2712, GIR_Done, // Label 496: @21589 GIM_Try, /*On fail goto*//*Label 497*/ 21628, // Rule ID 2713 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2713, GIR_Done, // Label 497: @21628 GIM_Try, /*On fail goto*//*Label 498*/ 21667, // Rule ID 2714 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2714, GIR_Done, // Label 498: @21667 GIM_Try, /*On fail goto*//*Label 499*/ 21706, // Rule ID 2715 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2715, GIR_Done, // Label 499: @21706 GIM_Try, /*On fail goto*//*Label 500*/ 21745, // Rule ID 2716 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2716, GIR_Done, // Label 500: @21745 GIM_Try, /*On fail goto*//*Label 501*/ 21779, // Rule ID 4065 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4065, GIR_Done, // Label 501: @21779 GIM_Try, /*On fail goto*//*Label 502*/ 21813, // Rule ID 4066 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4066, GIR_Done, // Label 502: @21813 GIM_Try, /*On fail goto*//*Label 503*/ 21847, // Rule ID 4071 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4071, GIR_Done, // Label 503: @21847 GIM_Try, /*On fail goto*//*Label 504*/ 21881, // Rule ID 4072 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4072, GIR_Done, // Label 504: @21881 GIM_Try, /*On fail goto*//*Label 505*/ 21915, // Rule ID 4073 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4073, GIR_Done, // Label 505: @21915 GIM_Try, /*On fail goto*//*Label 506*/ 21949, // Rule ID 4074 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4074, GIR_Done, // Label 506: @21949 GIM_Try, /*On fail goto*//*Label 507*/ 21983, // Rule ID 4075 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4075, GIR_Done, // Label 507: @21983 GIM_Try, /*On fail goto*//*Label 508*/ 22017, // Rule ID 4076 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4076, GIR_Done, // Label 508: @22017 GIM_Try, /*On fail goto*//*Label 509*/ 22051, // Rule ID 4077 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4077, GIR_Done, // Label 509: @22051 GIM_Try, /*On fail goto*//*Label 510*/ 22085, // Rule ID 4078 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4078, GIR_Done, // Label 510: @22085 GIM_Try, /*On fail goto*//*Label 511*/ 22119, // Rule ID 4079 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4079, GIR_Done, // Label 511: @22119 GIM_Try, /*On fail goto*//*Label 512*/ 22153, // Rule ID 4080 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4080, GIR_Done, // Label 512: @22153 GIM_Try, /*On fail goto*//*Label 513*/ 22206, // Rule ID 4107 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4107, GIR_Done, // Label 513: @22206 GIM_Try, /*On fail goto*//*Label 514*/ 22259, // Rule ID 4108 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4108, GIR_Done, // Label 514: @22259 GIM_Try, /*On fail goto*//*Label 515*/ 22312, // Rule ID 4109 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4109, GIR_Done, // Label 515: @22312 GIM_Try, /*On fail goto*//*Label 516*/ 22365, // Rule ID 4110 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4110, GIR_Done, // Label 516: @22365 GIM_Try, /*On fail goto*//*Label 517*/ 22418, // Rule ID 4111 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4111, GIR_Done, // Label 517: @22418 GIM_Try, /*On fail goto*//*Label 518*/ 22471, // Rule ID 4112 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4112, GIR_Done, // Label 518: @22471 GIM_Try, /*On fail goto*//*Label 519*/ 22524, // Rule ID 4113 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4113, GIR_Done, // Label 519: @22524 GIM_Try, /*On fail goto*//*Label 520*/ 22577, // Rule ID 4114 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4114, GIR_Done, // Label 520: @22577 GIM_Try, /*On fail goto*//*Label 521*/ 22630, // Rule ID 4115 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4115, GIR_Done, // Label 521: @22630 GIM_Try, /*On fail goto*//*Label 522*/ 22683, // Rule ID 4116 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4116, GIR_Done, // Label 522: @22683 GIM_Reject, // Label 426: @22684 GIM_Try, /*On fail goto*//*Label 523*/ 22718, // Rule ID 2591 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2591, GIR_Done, // Label 523: @22718 GIM_Try, /*On fail goto*//*Label 524*/ 22752, // Rule ID 2592 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2592, GIR_Done, // Label 524: @22752 GIM_Try, /*On fail goto*//*Label 525*/ 22786, // Rule ID 2619 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2619, GIR_Done, // Label 525: @22786 GIM_Try, /*On fail goto*//*Label 526*/ 22820, // Rule ID 2620 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2620, GIR_Done, // Label 526: @22820 GIM_Try, /*On fail goto*//*Label 527*/ 22854, // Rule ID 2621 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2621, GIR_Done, // Label 527: @22854 GIM_Try, /*On fail goto*//*Label 528*/ 22888, // Rule ID 2622 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2622, GIR_Done, // Label 528: @22888 GIM_Try, /*On fail goto*//*Label 529*/ 22922, // Rule ID 2623 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2623, GIR_Done, // Label 529: @22922 GIM_Try, /*On fail goto*//*Label 530*/ 22956, // Rule ID 2624 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2624, GIR_Done, // Label 530: @22956 GIM_Try, /*On fail goto*//*Label 531*/ 22990, // Rule ID 2625 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2625, GIR_Done, // Label 531: @22990 GIM_Try, /*On fail goto*//*Label 532*/ 23024, // Rule ID 2626 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2626, GIR_Done, // Label 532: @23024 GIM_Try, /*On fail goto*//*Label 533*/ 23058, // Rule ID 2627 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2627, GIR_Done, // Label 533: @23058 GIM_Try, /*On fail goto*//*Label 534*/ 23092, // Rule ID 2628 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2628, GIR_Done, // Label 534: @23092 GIM_Try, /*On fail goto*//*Label 535*/ 23131, // Rule ID 2691 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2691, GIR_Done, // Label 535: @23131 GIM_Try, /*On fail goto*//*Label 536*/ 23170, // Rule ID 2692 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2692, GIR_Done, // Label 536: @23170 GIM_Try, /*On fail goto*//*Label 537*/ 23209, // Rule ID 2693 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2693, GIR_Done, // Label 537: @23209 GIM_Try, /*On fail goto*//*Label 538*/ 23248, // Rule ID 2694 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2694, GIR_Done, // Label 538: @23248 GIM_Try, /*On fail goto*//*Label 539*/ 23287, // Rule ID 2695 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2695, GIR_Done, // Label 539: @23287 GIM_Try, /*On fail goto*//*Label 540*/ 23326, // Rule ID 2696 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2696, GIR_Done, // Label 540: @23326 GIM_Try, /*On fail goto*//*Label 541*/ 23365, // Rule ID 2697 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2697, GIR_Done, // Label 541: @23365 GIM_Try, /*On fail goto*//*Label 542*/ 23404, // Rule ID 2698 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2698, GIR_Done, // Label 542: @23404 GIM_Try, /*On fail goto*//*Label 543*/ 23443, // Rule ID 2699 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2699, GIR_Done, // Label 543: @23443 GIM_Try, /*On fail goto*//*Label 544*/ 23482, // Rule ID 2700 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2700, GIR_Done, // Label 544: @23482 GIM_Reject, // Label 427: @23483 GIM_Try, /*On fail goto*//*Label 545*/ 23517, // Rule ID 2595 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2595, GIR_Done, // Label 545: @23517 GIM_Try, /*On fail goto*//*Label 546*/ 23551, // Rule ID 2596 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2596, GIR_Done, // Label 546: @23551 GIM_Try, /*On fail goto*//*Label 547*/ 23585, // Rule ID 2645 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2645, GIR_Done, // Label 547: @23585 GIM_Try, /*On fail goto*//*Label 548*/ 23619, // Rule ID 2646 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2646, GIR_Done, // Label 548: @23619 GIM_Try, /*On fail goto*//*Label 549*/ 23653, // Rule ID 2647 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2647, GIR_Done, // Label 549: @23653 GIM_Try, /*On fail goto*//*Label 550*/ 23687, // Rule ID 2648 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2648, GIR_Done, // Label 550: @23687 GIM_Try, /*On fail goto*//*Label 551*/ 23721, // Rule ID 2649 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2649, GIR_Done, // Label 551: @23721 GIM_Try, /*On fail goto*//*Label 552*/ 23755, // Rule ID 2650 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2650, GIR_Done, // Label 552: @23755 GIM_Try, /*On fail goto*//*Label 553*/ 23789, // Rule ID 2651 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2651, GIR_Done, // Label 553: @23789 GIM_Try, /*On fail goto*//*Label 554*/ 23823, // Rule ID 2652 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2652, GIR_Done, // Label 554: @23823 GIM_Try, /*On fail goto*//*Label 555*/ 23857, // Rule ID 2653 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2653, GIR_Done, // Label 555: @23857 GIM_Try, /*On fail goto*//*Label 556*/ 23891, // Rule ID 2654 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2654, GIR_Done, // Label 556: @23891 GIM_Try, /*On fail goto*//*Label 557*/ 23930, // Rule ID 2717 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2717, GIR_Done, // Label 557: @23930 GIM_Try, /*On fail goto*//*Label 558*/ 23969, // Rule ID 2718 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2718, GIR_Done, // Label 558: @23969 GIM_Try, /*On fail goto*//*Label 559*/ 24008, // Rule ID 2719 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2719, GIR_Done, // Label 559: @24008 GIM_Try, /*On fail goto*//*Label 560*/ 24047, // Rule ID 2720 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2720, GIR_Done, // Label 560: @24047 GIM_Try, /*On fail goto*//*Label 561*/ 24086, // Rule ID 2721 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2721, GIR_Done, // Label 561: @24086 GIM_Try, /*On fail goto*//*Label 562*/ 24125, // Rule ID 2722 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2722, GIR_Done, // Label 562: @24125 GIM_Try, /*On fail goto*//*Label 563*/ 24164, // Rule ID 2723 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2723, GIR_Done, // Label 563: @24164 GIM_Try, /*On fail goto*//*Label 564*/ 24203, // Rule ID 2724 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2724, GIR_Done, // Label 564: @24203 GIM_Try, /*On fail goto*//*Label 565*/ 24242, // Rule ID 2725 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2725, GIR_Done, // Label 565: @24242 GIM_Try, /*On fail goto*//*Label 566*/ 24281, // Rule ID 2726 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2726, GIR_Done, // Label 566: @24281 GIM_Try, /*On fail goto*//*Label 567*/ 24315, // Rule ID 4067 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4067, GIR_Done, // Label 567: @24315 GIM_Try, /*On fail goto*//*Label 568*/ 24349, // Rule ID 4068 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4068, GIR_Done, // Label 568: @24349 GIM_Try, /*On fail goto*//*Label 569*/ 24383, // Rule ID 4081 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4081, GIR_Done, // Label 569: @24383 GIM_Try, /*On fail goto*//*Label 570*/ 24417, // Rule ID 4082 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4082, GIR_Done, // Label 570: @24417 GIM_Try, /*On fail goto*//*Label 571*/ 24451, // Rule ID 4083 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4083, GIR_Done, // Label 571: @24451 GIM_Try, /*On fail goto*//*Label 572*/ 24485, // Rule ID 4084 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4084, GIR_Done, // Label 572: @24485 GIM_Try, /*On fail goto*//*Label 573*/ 24519, // Rule ID 4085 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4085, GIR_Done, // Label 573: @24519 GIM_Try, /*On fail goto*//*Label 574*/ 24553, // Rule ID 4086 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4086, GIR_Done, // Label 574: @24553 GIM_Try, /*On fail goto*//*Label 575*/ 24587, // Rule ID 4087 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4087, GIR_Done, // Label 575: @24587 GIM_Try, /*On fail goto*//*Label 576*/ 24621, // Rule ID 4088 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4088, GIR_Done, // Label 576: @24621 GIM_Try, /*On fail goto*//*Label 577*/ 24655, // Rule ID 4089 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4089, GIR_Done, // Label 577: @24655 GIM_Try, /*On fail goto*//*Label 578*/ 24689, // Rule ID 4090 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4090, GIR_Done, // Label 578: @24689 GIM_Try, /*On fail goto*//*Label 579*/ 24742, // Rule ID 4117 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4117, GIR_Done, // Label 579: @24742 GIM_Try, /*On fail goto*//*Label 580*/ 24795, // Rule ID 4118 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4118, GIR_Done, // Label 580: @24795 GIM_Try, /*On fail goto*//*Label 581*/ 24848, // Rule ID 4119 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4119, GIR_Done, // Label 581: @24848 GIM_Try, /*On fail goto*//*Label 582*/ 24901, // Rule ID 4120 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4120, GIR_Done, // Label 582: @24901 GIM_Try, /*On fail goto*//*Label 583*/ 24954, // Rule ID 4121 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4121, GIR_Done, // Label 583: @24954 GIM_Try, /*On fail goto*//*Label 584*/ 25007, // Rule ID 4122 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4122, GIR_Done, // Label 584: @25007 GIM_Try, /*On fail goto*//*Label 585*/ 25060, // Rule ID 4123 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4123, GIR_Done, // Label 585: @25060 GIM_Try, /*On fail goto*//*Label 586*/ 25113, // Rule ID 4124 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4124, GIR_Done, // Label 586: @25113 GIM_Try, /*On fail goto*//*Label 587*/ 25166, // Rule ID 4125 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4125, GIR_Done, // Label 587: @25166 GIM_Try, /*On fail goto*//*Label 588*/ 25219, // Rule ID 4126 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4126, GIR_Done, // Label 588: @25219 GIM_Reject, // Label 428: @25220 GIM_Try, /*On fail goto*//*Label 589*/ 25254, // Rule ID 2629 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2629, GIR_Done, // Label 589: @25254 GIM_Try, /*On fail goto*//*Label 590*/ 25288, // Rule ID 2630 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2630, GIR_Done, // Label 590: @25288 GIM_Try, /*On fail goto*//*Label 591*/ 25322, // Rule ID 2631 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2631, GIR_Done, // Label 591: @25322 GIM_Try, /*On fail goto*//*Label 592*/ 25356, // Rule ID 2632 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2632, GIR_Done, // Label 592: @25356 GIM_Try, /*On fail goto*//*Label 593*/ 25390, // Rule ID 2633 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2633, GIR_Done, // Label 593: @25390 GIM_Try, /*On fail goto*//*Label 594*/ 25424, // Rule ID 2634 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/36, // GIR_Coverage, 2634, GIR_Done, // Label 594: @25424 GIM_Try, /*On fail goto*//*Label 595*/ 25463, // Rule ID 2701 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2701, GIR_Done, // Label 595: @25463 GIM_Try, /*On fail goto*//*Label 596*/ 25502, // Rule ID 2702 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2702, GIR_Done, // Label 596: @25502 GIM_Try, /*On fail goto*//*Label 597*/ 25541, // Rule ID 2703 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2703, GIR_Done, // Label 597: @25541 GIM_Try, /*On fail goto*//*Label 598*/ 25580, // Rule ID 2704 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2704, GIR_Done, // Label 598: @25580 GIM_Try, /*On fail goto*//*Label 599*/ 25619, // Rule ID 2705 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2705, GIR_Done, // Label 599: @25619 GIM_Try, /*On fail goto*//*Label 600*/ 25658, // Rule ID 2706 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2706, GIR_Done, // Label 600: @25658 GIM_Reject, // Label 429: @25659 GIM_Try, /*On fail goto*//*Label 601*/ 25693, // Rule ID 2597 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2597, GIR_Done, // Label 601: @25693 GIM_Try, /*On fail goto*//*Label 602*/ 25727, // Rule ID 2598 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2598, GIR_Done, // Label 602: @25727 GIM_Try, /*On fail goto*//*Label 603*/ 25761, // Rule ID 2655 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2655, GIR_Done, // Label 603: @25761 GIM_Try, /*On fail goto*//*Label 604*/ 25795, // Rule ID 2656 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2656, GIR_Done, // Label 604: @25795 GIM_Try, /*On fail goto*//*Label 605*/ 25829, // Rule ID 2657 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2657, GIR_Done, // Label 605: @25829 GIM_Try, /*On fail goto*//*Label 606*/ 25863, // Rule ID 2658 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2658, GIR_Done, // Label 606: @25863 GIM_Try, /*On fail goto*//*Label 607*/ 25897, // Rule ID 2659 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2659, GIR_Done, // Label 607: @25897 GIM_Try, /*On fail goto*//*Label 608*/ 25931, // Rule ID 2660 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2660, GIR_Done, // Label 608: @25931 GIM_Try, /*On fail goto*//*Label 609*/ 25965, // Rule ID 2661 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2661, GIR_Done, // Label 609: @25965 GIM_Try, /*On fail goto*//*Label 610*/ 25999, // Rule ID 2662 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2662, GIR_Done, // Label 610: @25999 GIM_Try, /*On fail goto*//*Label 611*/ 26033, // Rule ID 2663 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2663, GIR_Done, // Label 611: @26033 GIM_Try, /*On fail goto*//*Label 612*/ 26067, // Rule ID 2664 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2664, GIR_Done, // Label 612: @26067 GIM_Try, /*On fail goto*//*Label 613*/ 26106, // Rule ID 2727 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2727, GIR_Done, // Label 613: @26106 GIM_Try, /*On fail goto*//*Label 614*/ 26145, // Rule ID 2728 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2728, GIR_Done, // Label 614: @26145 GIM_Try, /*On fail goto*//*Label 615*/ 26184, // Rule ID 2729 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2729, GIR_Done, // Label 615: @26184 GIM_Try, /*On fail goto*//*Label 616*/ 26223, // Rule ID 2730 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2730, GIR_Done, // Label 616: @26223 GIM_Try, /*On fail goto*//*Label 617*/ 26262, // Rule ID 2731 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2731, GIR_Done, // Label 617: @26262 GIM_Try, /*On fail goto*//*Label 618*/ 26301, // Rule ID 2732 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2732, GIR_Done, // Label 618: @26301 GIM_Try, /*On fail goto*//*Label 619*/ 26340, // Rule ID 2733 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2733, GIR_Done, // Label 619: @26340 GIM_Try, /*On fail goto*//*Label 620*/ 26379, // Rule ID 2734 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2734, GIR_Done, // Label 620: @26379 GIM_Try, /*On fail goto*//*Label 621*/ 26418, // Rule ID 2735 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2735, GIR_Done, // Label 621: @26418 GIM_Try, /*On fail goto*//*Label 622*/ 26457, // Rule ID 2736 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2736, GIR_Done, // Label 622: @26457 GIM_Try, /*On fail goto*//*Label 623*/ 26491, // Rule ID 4069 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4069, GIR_Done, // Label 623: @26491 GIM_Try, /*On fail goto*//*Label 624*/ 26525, // Rule ID 4070 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4070, GIR_Done, // Label 624: @26525 GIM_Try, /*On fail goto*//*Label 625*/ 26559, // Rule ID 4091 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4091, GIR_Done, // Label 625: @26559 GIM_Try, /*On fail goto*//*Label 626*/ 26593, // Rule ID 4092 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4092, GIR_Done, // Label 626: @26593 GIM_Try, /*On fail goto*//*Label 627*/ 26627, // Rule ID 4093 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4093, GIR_Done, // Label 627: @26627 GIM_Try, /*On fail goto*//*Label 628*/ 26661, // Rule ID 4094 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4094, GIR_Done, // Label 628: @26661 GIM_Try, /*On fail goto*//*Label 629*/ 26695, // Rule ID 4095 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4095, GIR_Done, // Label 629: @26695 GIM_Try, /*On fail goto*//*Label 630*/ 26729, // Rule ID 4096 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4096, GIR_Done, // Label 630: @26729 GIM_Try, /*On fail goto*//*Label 631*/ 26763, // Rule ID 4097 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4097, GIR_Done, // Label 631: @26763 GIM_Try, /*On fail goto*//*Label 632*/ 26797, // Rule ID 4098 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4098, GIR_Done, // Label 632: @26797 GIM_Try, /*On fail goto*//*Label 633*/ 26831, // Rule ID 4099 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4099, GIR_Done, // Label 633: @26831 GIM_Try, /*On fail goto*//*Label 634*/ 26865, // Rule ID 4100 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4100, GIR_Done, // Label 634: @26865 GIM_Try, /*On fail goto*//*Label 635*/ 26918, // Rule ID 4127 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4127, GIR_Done, // Label 635: @26918 GIM_Try, /*On fail goto*//*Label 636*/ 26971, // Rule ID 4128 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4128, GIR_Done, // Label 636: @26971 GIM_Try, /*On fail goto*//*Label 637*/ 27024, // Rule ID 4129 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4129, GIR_Done, // Label 637: @27024 GIM_Try, /*On fail goto*//*Label 638*/ 27077, // Rule ID 4130 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4130, GIR_Done, // Label 638: @27077 GIM_Try, /*On fail goto*//*Label 639*/ 27130, // Rule ID 4131 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4131, GIR_Done, // Label 639: @27130 GIM_Try, /*On fail goto*//*Label 640*/ 27183, // Rule ID 4132 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4132, GIR_Done, // Label 640: @27183 GIM_Try, /*On fail goto*//*Label 641*/ 27236, // Rule ID 4133 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4133, GIR_Done, // Label 641: @27236 GIM_Try, /*On fail goto*//*Label 642*/ 27289, // Rule ID 4134 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4134, GIR_Done, // Label 642: @27289 GIM_Try, /*On fail goto*//*Label 643*/ 27342, // Rule ID 4135 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4135, GIR_Done, // Label 643: @27342 GIM_Try, /*On fail goto*//*Label 644*/ 27395, // Rule ID 4136 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4136, GIR_Done, // Label 644: @27395 GIM_Reject, // Label 430: @27396 GIM_Try, /*On fail goto*//*Label 645*/ 27430, // Rule ID 2665 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2665, GIR_Done, // Label 645: @27430 GIM_Try, /*On fail goto*//*Label 646*/ 27464, // Rule ID 2666 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2666, GIR_Done, // Label 646: @27464 GIM_Try, /*On fail goto*//*Label 647*/ 27498, // Rule ID 2667 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2667, GIR_Done, // Label 647: @27498 GIM_Try, /*On fail goto*//*Label 648*/ 27532, // Rule ID 2668 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2668, GIR_Done, // Label 648: @27532 GIM_Try, /*On fail goto*//*Label 649*/ 27566, // Rule ID 2669 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2669, GIR_Done, // Label 649: @27566 GIM_Try, /*On fail goto*//*Label 650*/ 27600, // Rule ID 2670 // GIM_CheckFeatures, GIFBS_HasNEON_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/54, // GIR_Coverage, 2670, GIR_Done, // Label 650: @27600 GIM_Try, /*On fail goto*//*Label 651*/ 27639, // Rule ID 2737 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2737, GIR_Done, // Label 651: @27639 GIM_Try, /*On fail goto*//*Label 652*/ 27678, // Rule ID 2738 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2738, GIR_Done, // Label 652: @27678 GIM_Try, /*On fail goto*//*Label 653*/ 27717, // Rule ID 2739 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2739, GIR_Done, // Label 653: @27717 GIM_Try, /*On fail goto*//*Label 654*/ 27756, // Rule ID 2740 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2740, GIR_Done, // Label 654: @27756 GIM_Try, /*On fail goto*//*Label 655*/ 27795, // Rule ID 2741 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2741, GIR_Done, // Label 655: @27795 GIM_Try, /*On fail goto*//*Label 656*/ 27834, // Rule ID 2742 // GIM_CheckFeatures, GIFBS_HasNEON_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2742, GIR_Done, // Label 656: @27834 GIM_Try, /*On fail goto*//*Label 657*/ 27868, // Rule ID 4101 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4101, GIR_Done, // Label 657: @27868 GIM_Try, /*On fail goto*//*Label 658*/ 27902, // Rule ID 4102 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4102, GIR_Done, // Label 658: @27902 GIM_Try, /*On fail goto*//*Label 659*/ 27936, // Rule ID 4103 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4103, GIR_Done, // Label 659: @27936 GIM_Try, /*On fail goto*//*Label 660*/ 27970, // Rule ID 4104 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4104, GIR_Done, // Label 660: @27970 GIM_Try, /*On fail goto*//*Label 661*/ 28004, // Rule ID 4105 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4105, GIR_Done, // Label 661: @28004 GIM_Try, /*On fail goto*//*Label 662*/ 28038, // Rule ID 4106 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MQPR*/57, // GIR_Coverage, 4106, GIR_Done, // Label 662: @28038 GIM_Try, /*On fail goto*//*Label 663*/ 28091, // Rule ID 4137 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4137, GIR_Done, // Label 663: @28091 GIM_Try, /*On fail goto*//*Label 664*/ 28144, // Rule ID 4138 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4138, GIR_Done, // Label 664: @28144 GIM_Try, /*On fail goto*//*Label 665*/ 28197, // Rule ID 4139 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4139, GIR_Done, // Label 665: @28197 GIM_Try, /*On fail goto*//*Label 666*/ 28250, // Rule ID 4140 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4140, GIR_Done, // Label 666: @28250 GIM_Try, /*On fail goto*//*Label 667*/ 28303, // Rule ID 4141 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4141, GIR_Done, // Label 667: @28303 GIM_Try, /*On fail goto*//*Label 668*/ 28356, // Rule ID 4142 // GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4142, GIR_Done, // Label 668: @28356 GIM_Reject, // Label 431: @28357 GIM_Reject, // Label 10: @28358 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 674*/ 28604, /*GILLT_s16*//*Label 669*/ 28376, /*GILLT_s32*//*Label 670*/ 28416, /*GILLT_s64*//*Label 671*/ 28456, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 672*/ 28496, 0, 0, 0, /*GILLT_v8s16*//*Label 673*/ 28550, // Label 669: @28376 GIM_Try, /*On fail goto*//*Label 675*/ 28415, // Rule ID 678 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 678, GIR_Done, // Label 675: @28415 GIM_Reject, // Label 670: @28416 GIM_Try, /*On fail goto*//*Label 676*/ 28455, // Rule ID 679 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 679, GIR_Done, // Label 676: @28455 GIM_Reject, // Label 671: @28456 GIM_Try, /*On fail goto*//*Label 677*/ 28495, // Rule ID 680 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 680, GIR_Done, // Label 677: @28495 GIM_Reject, // Label 672: @28496 GIM_Try, /*On fail goto*//*Label 678*/ 28549, // Rule ID 3366 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32Z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3366, GIR_Done, // Label 678: @28549 GIM_Reject, // Label 673: @28550 GIM_Try, /*On fail goto*//*Label 679*/ 28603, // Rule ID 3367 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16Z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3367, GIR_Done, // Label 679: @28603 GIM_Reject, // Label 674: @28604 GIM_Reject, // Label 11: @28605 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 685*/ 28803, /*GILLT_s16*//*Label 680*/ 28623, /*GILLT_s32*//*Label 681*/ 28647, /*GILLT_s64*//*Label 682*/ 28671, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 683*/ 28695, 0, 0, 0, /*GILLT_v8s16*//*Label 684*/ 28749, // Label 680: @28623 GIM_Try, /*On fail goto*//*Label 686*/ 28646, // Rule ID 687 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 687, GIR_Done, // Label 686: @28646 GIM_Reject, // Label 681: @28647 GIM_Try, /*On fail goto*//*Label 687*/ 28670, // Rule ID 688 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAS, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 688, GIR_Done, // Label 687: @28670 GIM_Reject, // Label 682: @28671 GIM_Try, /*On fail goto*//*Label 688*/ 28694, // Rule ID 689 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAD, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 689, GIR_Done, // Label 688: @28694 GIM_Reject, // Label 683: @28695 GIM_Try, /*On fail goto*//*Label 689*/ 28748, // Rule ID 3364 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32A, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3364, GIR_Done, // Label 689: @28748 GIM_Reject, // Label 684: @28749 GIM_Try, /*On fail goto*//*Label 690*/ 28802, // Rule ID 3365 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16A, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3365, GIR_Done, // Label 690: @28802 GIM_Reject, // Label 685: @28803 GIM_Reject, // Label 12: @28804 GIM_Try, /*On fail goto*//*Label 691*/ 34505, GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, GIM_Try, /*On fail goto*//*Label 692*/ 28859, // Rule ID 1869 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1861:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1869, GIR_Done, // Label 692: @28859 GIM_Try, /*On fail goto*//*Label 693*/ 28909, // Rule ID 2092 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1861:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2092, GIR_Done, // Label 693: @28909 GIM_Try, /*On fail goto*//*Label 694*/ 28949, // Rule ID 690 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (intrinsic_wo_chain:{ *:[f16] } 1747:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 690, GIR_Done, // Label 694: @28949 GIM_Try, /*On fail goto*//*Label 695*/ 28989, // Rule ID 691 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (intrinsic_wo_chain:{ *:[f32] } 1747:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 691, GIR_Done, // Label 695: @28989 GIM_Try, /*On fail goto*//*Label 696*/ 29029, // Rule ID 692 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[f64] } 1747:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 692, GIR_Done, // Label 696: @29029 GIM_Try, /*On fail goto*//*Label 697*/ 29076, // Rule ID 708 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[f32] } 1862:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 708, GIR_Done, // Label 697: @29076 GIM_Try, /*On fail goto*//*Label 698*/ 29123, // Rule ID 709 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (intrinsic_wo_chain:{ *:[f32] } 1862:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 709, GIR_Done, // Label 698: @29123 GIM_Try, /*On fail goto*//*Label 699*/ 29170, // Rule ID 710 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[f32] } 1863:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 710, GIR_Done, // Label 699: @29170 GIM_Try, /*On fail goto*//*Label 700*/ 29217, // Rule ID 711 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (intrinsic_wo_chain:{ *:[f32] } 1863:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 711, GIR_Done, // Label 700: @29217 GIM_Try, /*On fail goto*//*Label 701*/ 29264, // Rule ID 1230 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1715:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1230, GIR_Done, // Label 701: @29264 GIM_Try, /*On fail goto*//*Label 702*/ 29311, // Rule ID 1231 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1715:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1231, GIR_Done, // Label 702: @29311 GIM_Try, /*On fail goto*//*Label 703*/ 29358, // Rule ID 1232 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1715:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1232, GIR_Done, // Label 703: @29358 GIM_Try, /*On fail goto*//*Label 704*/ 29405, // Rule ID 1233 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1715:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1233, GIR_Done, // Label 704: @29405 GIM_Try, /*On fail goto*//*Label 705*/ 29452, // Rule ID 1234 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1715:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1234, GIR_Done, // Label 705: @29452 GIM_Try, /*On fail goto*//*Label 706*/ 29499, // Rule ID 1235 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1715:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1235, GIR_Done, // Label 706: @29499 GIM_Try, /*On fail goto*//*Label 707*/ 29546, // Rule ID 1236 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1716:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1236, GIR_Done, // Label 707: @29546 GIM_Try, /*On fail goto*//*Label 708*/ 29593, // Rule ID 1237 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1716:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1237, GIR_Done, // Label 708: @29593 GIM_Try, /*On fail goto*//*Label 709*/ 29640, // Rule ID 1238 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1716:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1238, GIR_Done, // Label 709: @29640 GIM_Try, /*On fail goto*//*Label 710*/ 29687, // Rule ID 1239 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1716:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1239, GIR_Done, // Label 710: @29687 GIM_Try, /*On fail goto*//*Label 711*/ 29734, // Rule ID 1240 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1716:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1240, GIR_Done, // Label 711: @29734 GIM_Try, /*On fail goto*//*Label 712*/ 29781, // Rule ID 1241 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1716:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1241, GIR_Done, // Label 712: @29781 GIM_Try, /*On fail goto*//*Label 713*/ 29828, // Rule ID 1270 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1741:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1270, GIR_Done, // Label 713: @29828 GIM_Try, /*On fail goto*//*Label 714*/ 29875, // Rule ID 1271 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1741:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1271, GIR_Done, // Label 714: @29875 GIM_Try, /*On fail goto*//*Label 715*/ 29922, // Rule ID 1272 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1741:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1272, GIR_Done, // Label 715: @29922 GIM_Try, /*On fail goto*//*Label 716*/ 29969, // Rule ID 1273 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1741:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1273, GIR_Done, // Label 716: @29969 GIM_Try, /*On fail goto*//*Label 717*/ 30016, // Rule ID 1274 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1741:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1274, GIR_Done, // Label 717: @30016 GIM_Try, /*On fail goto*//*Label 718*/ 30063, // Rule ID 1275 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1741:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1275, GIR_Done, // Label 718: @30063 GIM_Try, /*On fail goto*//*Label 719*/ 30110, // Rule ID 1280 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1754:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1280, GIR_Done, // Label 719: @30110 GIM_Try, /*On fail goto*//*Label 720*/ 30157, // Rule ID 1281 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1754:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1281, GIR_Done, // Label 720: @30157 GIM_Try, /*On fail goto*//*Label 721*/ 30204, // Rule ID 1282 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1754:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1282, GIR_Done, // Label 721: @30204 GIM_Try, /*On fail goto*//*Label 722*/ 30251, // Rule ID 1283 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1754:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1283, GIR_Done, // Label 722: @30251 GIM_Try, /*On fail goto*//*Label 723*/ 30298, // Rule ID 1284 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1754:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1284, GIR_Done, // Label 723: @30298 GIM_Try, /*On fail goto*//*Label 724*/ 30345, // Rule ID 1285 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1754:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1285, GIR_Done, // Label 724: @30345 GIM_Try, /*On fail goto*//*Label 725*/ 30392, // Rule ID 1506 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1721:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1506, GIR_Done, // Label 725: @30392 GIM_Try, /*On fail goto*//*Label 726*/ 30439, // Rule ID 1507 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1721:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1507, GIR_Done, // Label 726: @30439 GIM_Try, /*On fail goto*//*Label 727*/ 30486, // Rule ID 1508 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1721:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1508, GIR_Done, // Label 727: @30486 GIM_Try, /*On fail goto*//*Label 728*/ 30533, // Rule ID 1509 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1721:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1509, GIR_Done, // Label 728: @30533 GIM_Try, /*On fail goto*//*Label 729*/ 30580, // Rule ID 1510 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1721:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1510, GIR_Done, // Label 729: @30580 GIM_Try, /*On fail goto*//*Label 730*/ 30627, // Rule ID 1511 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1721:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1511, GIR_Done, // Label 730: @30627 GIM_Try, /*On fail goto*//*Label 731*/ 30674, // Rule ID 1522 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1727:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1522, GIR_Done, // Label 731: @30674 GIM_Try, /*On fail goto*//*Label 732*/ 30721, // Rule ID 1523 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1727:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1523, GIR_Done, // Label 732: @30721 GIM_Try, /*On fail goto*//*Label 733*/ 30768, // Rule ID 1524 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1727:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1524, GIR_Done, // Label 733: @30768 GIM_Try, /*On fail goto*//*Label 734*/ 30815, // Rule ID 1525 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1727:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1525, GIR_Done, // Label 734: @30815 GIM_Try, /*On fail goto*//*Label 735*/ 30862, // Rule ID 1526 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1727:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1526, GIR_Done, // Label 735: @30862 GIM_Try, /*On fail goto*//*Label 736*/ 30909, // Rule ID 1527 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1727:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1527, GIR_Done, // Label 736: @30909 GIM_Try, /*On fail goto*//*Label 737*/ 30956, // Rule ID 1528 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1670:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1528, GIR_Done, // Label 737: @30956 GIM_Try, /*On fail goto*//*Label 738*/ 31003, // Rule ID 1529 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1670:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1529, GIR_Done, // Label 738: @31003 GIM_Try, /*On fail goto*//*Label 739*/ 31050, // Rule ID 1530 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1670:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1530, GIR_Done, // Label 739: @31050 GIM_Try, /*On fail goto*//*Label 740*/ 31097, // Rule ID 1531 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1670:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1531, GIR_Done, // Label 740: @31097 GIM_Try, /*On fail goto*//*Label 741*/ 31144, // Rule ID 1532 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1670:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1532, GIR_Done, // Label 741: @31144 GIM_Try, /*On fail goto*//*Label 742*/ 31191, // Rule ID 1533 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1670:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1533, GIR_Done, // Label 742: @31191 GIM_Try, /*On fail goto*//*Label 743*/ 31238, // Rule ID 1577 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1724:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1577, GIR_Done, // Label 743: @31238 GIM_Try, /*On fail goto*//*Label 744*/ 31285, // Rule ID 1578 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1724:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1578, GIR_Done, // Label 744: @31285 GIM_Try, /*On fail goto*//*Label 745*/ 31332, // Rule ID 1579 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1724:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1579, GIR_Done, // Label 745: @31332 GIM_Try, /*On fail goto*//*Label 746*/ 31379, // Rule ID 1580 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1726:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1580, GIR_Done, // Label 746: @31379 GIM_Try, /*On fail goto*//*Label 747*/ 31426, // Rule ID 1581 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1726:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1581, GIR_Done, // Label 747: @31426 GIM_Try, /*On fail goto*//*Label 748*/ 31473, // Rule ID 1582 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1726:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1582, GIR_Done, // Label 748: @31473 GIM_Try, /*On fail goto*//*Label 749*/ 31520, // Rule ID 1583 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1725:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1583, GIR_Done, // Label 749: @31520 GIM_Try, /*On fail goto*//*Label 750*/ 31567, // Rule ID 1584 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1725:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1584, GIR_Done, // Label 750: @31567 GIM_Try, /*On fail goto*//*Label 751*/ 31614, // Rule ID 1585 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1725:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1585, GIR_Done, // Label 751: @31614 GIM_Try, /*On fail goto*//*Label 752*/ 31654, // Rule ID 1608 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1671:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1608, GIR_Done, // Label 752: @31654 GIM_Try, /*On fail goto*//*Label 753*/ 31694, // Rule ID 1609 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1671:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1609, GIR_Done, // Label 753: @31694 GIM_Try, /*On fail goto*//*Label 754*/ 31734, // Rule ID 1610 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1672:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1610, GIR_Done, // Label 754: @31734 GIM_Try, /*On fail goto*//*Label 755*/ 31774, // Rule ID 1611 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1672:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1611, GIR_Done, // Label 755: @31774 GIM_Try, /*On fail goto*//*Label 756*/ 31814, // Rule ID 1612 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1671:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1612, GIR_Done, // Label 756: @31814 GIM_Try, /*On fail goto*//*Label 757*/ 31854, // Rule ID 1613 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1671:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1613, GIR_Done, // Label 757: @31854 GIM_Try, /*On fail goto*//*Label 758*/ 31894, // Rule ID 1614 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1672:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1614, GIR_Done, // Label 758: @31894 GIM_Try, /*On fail goto*//*Label 759*/ 31934, // Rule ID 1615 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1672:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1615, GIR_Done, // Label 759: @31934 GIM_Try, /*On fail goto*//*Label 760*/ 31974, // Rule ID 1616 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1681:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1616, GIR_Done, // Label 760: @31974 GIM_Try, /*On fail goto*//*Label 761*/ 32014, // Rule ID 1617 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1681:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1617, GIR_Done, // Label 761: @32014 GIM_Try, /*On fail goto*//*Label 762*/ 32054, // Rule ID 1618 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1682:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1618, GIR_Done, // Label 762: @32054 GIM_Try, /*On fail goto*//*Label 763*/ 32094, // Rule ID 1619 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1682:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1619, GIR_Done, // Label 763: @32094 GIM_Try, /*On fail goto*//*Label 764*/ 32134, // Rule ID 1620 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1681:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1620, GIR_Done, // Label 764: @32134 GIM_Try, /*On fail goto*//*Label 765*/ 32174, // Rule ID 1621 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1681:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1621, GIR_Done, // Label 765: @32174 GIM_Try, /*On fail goto*//*Label 766*/ 32214, // Rule ID 1622 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1682:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1622, GIR_Done, // Label 766: @32214 GIM_Try, /*On fail goto*//*Label 767*/ 32254, // Rule ID 1623 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1682:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1623, GIR_Done, // Label 767: @32254 GIM_Try, /*On fail goto*//*Label 768*/ 32294, // Rule ID 1624 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1683:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1624, GIR_Done, // Label 768: @32294 GIM_Try, /*On fail goto*//*Label 769*/ 32334, // Rule ID 1625 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1683:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1625, GIR_Done, // Label 769: @32334 GIM_Try, /*On fail goto*//*Label 770*/ 32374, // Rule ID 1626 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1684:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1626, GIR_Done, // Label 770: @32374 GIM_Try, /*On fail goto*//*Label 771*/ 32414, // Rule ID 1627 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1684:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1627, GIR_Done, // Label 771: @32414 GIM_Try, /*On fail goto*//*Label 772*/ 32454, // Rule ID 1628 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1683:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1628, GIR_Done, // Label 772: @32454 GIM_Try, /*On fail goto*//*Label 773*/ 32494, // Rule ID 1629 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1683:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1629, GIR_Done, // Label 773: @32494 GIM_Try, /*On fail goto*//*Label 774*/ 32534, // Rule ID 1630 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1684:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1630, GIR_Done, // Label 774: @32534 GIM_Try, /*On fail goto*//*Label 775*/ 32574, // Rule ID 1631 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1684:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1631, GIR_Done, // Label 775: @32574 GIM_Try, /*On fail goto*//*Label 776*/ 32614, // Rule ID 1632 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1679:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1632, GIR_Done, // Label 776: @32614 GIM_Try, /*On fail goto*//*Label 777*/ 32654, // Rule ID 1633 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1679:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1633, GIR_Done, // Label 777: @32654 GIM_Try, /*On fail goto*//*Label 778*/ 32694, // Rule ID 1634 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1680:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1634, GIR_Done, // Label 778: @32694 GIM_Try, /*On fail goto*//*Label 779*/ 32734, // Rule ID 1635 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1680:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1635, GIR_Done, // Label 779: @32734 GIM_Try, /*On fail goto*//*Label 780*/ 32774, // Rule ID 1636 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1679:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1636, GIR_Done, // Label 780: @32774 GIM_Try, /*On fail goto*//*Label 781*/ 32814, // Rule ID 1637 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1679:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1637, GIR_Done, // Label 781: @32814 GIM_Try, /*On fail goto*//*Label 782*/ 32854, // Rule ID 1638 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1680:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1638, GIR_Done, // Label 782: @32854 GIM_Try, /*On fail goto*//*Label 783*/ 32894, // Rule ID 1639 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1680:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1639, GIR_Done, // Label 783: @32894 GIM_Try, /*On fail goto*//*Label 784*/ 32941, // Rule ID 1656 // GIM_CheckFeatures, GIFBS_HasFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2hf, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1675:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1656, GIR_Done, // Label 784: @32941 GIM_Try, /*On fail goto*//*Label 785*/ 32988, // Rule ID 1657 // GIM_CheckFeatures, GIFBS_HasFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvthf2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1678:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1657, GIR_Done, // Label 785: @32988 GIM_Try, /*On fail goto*//*Label 786*/ 33028, // Rule ID 1679 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1747:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1679, GIR_Done, // Label 786: @33028 GIM_Try, /*On fail goto*//*Label 787*/ 33068, // Rule ID 1680 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1747:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1680, GIR_Done, // Label 787: @33068 GIM_Try, /*On fail goto*//*Label 788*/ 33108, // Rule ID 1681 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1747:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1681, GIR_Done, // Label 788: @33108 GIM_Try, /*On fail goto*//*Label 789*/ 33148, // Rule ID 1682 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1747:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1682, GIR_Done, // Label 789: @33148 GIM_Try, /*On fail goto*//*Label 790*/ 33188, // Rule ID 1683 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1749:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1683, GIR_Done, // Label 790: @33188 GIM_Try, /*On fail goto*//*Label 791*/ 33228, // Rule ID 1684 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1749:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1684, GIR_Done, // Label 791: @33228 GIM_Try, /*On fail goto*//*Label 792*/ 33268, // Rule ID 1685 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1749:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1685, GIR_Done, // Label 792: @33268 GIM_Try, /*On fail goto*//*Label 793*/ 33308, // Rule ID 1686 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1749:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1686, GIR_Done, // Label 793: @33308 GIM_Try, /*On fail goto*//*Label 794*/ 33348, // Rule ID 1687 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1745:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1687, GIR_Done, // Label 794: @33348 GIM_Try, /*On fail goto*//*Label 795*/ 33388, // Rule ID 1688 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1745:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1688, GIR_Done, // Label 795: @33388 GIM_Try, /*On fail goto*//*Label 796*/ 33428, // Rule ID 1689 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1745:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1689, GIR_Done, // Label 796: @33428 GIM_Try, /*On fail goto*//*Label 797*/ 33468, // Rule ID 1690 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1745:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1690, GIR_Done, // Label 797: @33468 GIM_Try, /*On fail goto*//*Label 798*/ 33508, // Rule ID 1691 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1750:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1691, GIR_Done, // Label 798: @33508 GIM_Try, /*On fail goto*//*Label 799*/ 33548, // Rule ID 1692 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1750:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1692, GIR_Done, // Label 799: @33548 GIM_Try, /*On fail goto*//*Label 800*/ 33588, // Rule ID 1693 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1750:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1693, GIR_Done, // Label 800: @33588 GIM_Try, /*On fail goto*//*Label 801*/ 33628, // Rule ID 1694 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1750:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1694, GIR_Done, // Label 801: @33628 GIM_Try, /*On fail goto*//*Label 802*/ 33668, // Rule ID 1695 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1746:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1695, GIR_Done, // Label 802: @33668 GIM_Try, /*On fail goto*//*Label 803*/ 33708, // Rule ID 1696 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1746:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1696, GIR_Done, // Label 803: @33708 GIM_Try, /*On fail goto*//*Label 804*/ 33748, // Rule ID 1697 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1746:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1697, GIR_Done, // Label 804: @33748 GIM_Try, /*On fail goto*//*Label 805*/ 33788, // Rule ID 1698 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1746:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1698, GIR_Done, // Label 805: @33788 GIM_Try, /*On fail goto*//*Label 806*/ 33828, // Rule ID 1699 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1748:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1699, GIR_Done, // Label 806: @33828 GIM_Try, /*On fail goto*//*Label 807*/ 33868, // Rule ID 1700 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1748:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1700, GIR_Done, // Label 807: @33868 GIM_Try, /*On fail goto*//*Label 808*/ 33908, // Rule ID 1701 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1748:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1701, GIR_Done, // Label 808: @33908 GIM_Try, /*On fail goto*//*Label 809*/ 33948, // Rule ID 1702 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1748:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1702, GIR_Done, // Label 809: @33948 GIM_Try, /*On fail goto*//*Label 810*/ 33988, // Rule ID 1705 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesimc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1648:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1705, GIR_Done, // Label 810: @33988 GIM_Try, /*On fail goto*//*Label 811*/ 34028, // Rule ID 1706 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesmc, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1649:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1706, GIR_Done, // Label 811: @34028 GIM_Try, /*On fail goto*//*Label 812*/ 34078, // Rule ID 1864 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1836:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1864, GIR_Done, // Label 812: @34078 GIM_Try, /*On fail goto*//*Label 813*/ 34128, // Rule ID 2081 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1836:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2081, GIR_Done, // Label 813: @34128 GIM_Try, /*On fail goto*//*Label 814*/ 34175, // Rule ID 3684 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i1] } 1594:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3684, GIR_Done, // Label 814: @34175 GIM_Try, /*On fail goto*//*Label 815*/ 34222, // Rule ID 3686 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i1] } 1591:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3686, GIR_Done, // Label 815: @34222 GIM_Try, /*On fail goto*//*Label 816*/ 34269, // Rule ID 3688 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp32, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i1] } 1592:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3688, GIR_Done, // Label 816: @34269 GIM_Try, /*On fail goto*//*Label 817*/ 34316, // Rule ID 3690 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp64, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i1] } 1593:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3690, GIR_Done, // Label 817: @34316 GIM_Try, /*On fail goto*//*Label 818*/ 34363, // Rule ID 614 // GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1503:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 614, GIR_Done, // Label 818: @34363 GIM_Try, /*On fail goto*//*Label 819*/ 34410, // Rule ID 615 // GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1506:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 615, GIR_Done, // Label 819: @34410 GIM_Try, /*On fail goto*//*Label 820*/ 34457, // Rule ID 616 // GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tta, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1504:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTA, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 616, GIR_Done, // Label 820: @34457 GIM_Try, /*On fail goto*//*Label 821*/ 34504, // Rule ID 617 // GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttat, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Rn GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1505:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTAT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 617, GIR_Done, // Label 821: @34504 GIM_Reject, // Label 691: @34505 GIM_Try, /*On fail goto*//*Label 822*/ 54837, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 823*/ 34572, // Rule ID 2099 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1860:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2099, GIR_Done, // Label 823: @34572 GIM_Try, /*On fail goto*//*Label 824*/ 34656, // Rule ID 111 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // MIs[1] Rm GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Rn) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 111, GIR_Done, // Label 824: @34656 GIM_Try, /*On fail goto*//*Label 825*/ 34740, // Rule ID 2117 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // MIs[1] Rm GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Rn) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2117, GIR_Done, // Label 825: @34740 GIM_Try, /*On fail goto*//*Label 826*/ 34824, // Rule ID 112 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // MIs[1] Rn GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 112, GIR_Done, // Label 826: @34824 GIM_Try, /*On fail goto*//*Label 827*/ 34908, // Rule ID 2118 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // MIs[1] Rn GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2118, GIR_Done, // Label 827: @34908 GIM_Try, /*On fail goto*//*Label 828*/ 34992, // Rule ID 4151 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, // MIs[1] Rm GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4151, GIR_Done, // Label 828: @34992 GIM_Try, /*On fail goto*//*Label 829*/ 35076, // Rule ID 4405 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // MIs[1] Rm GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4405, GIR_Done, // Label 829: @35076 GIM_Try, /*On fail goto*//*Label 830*/ 35145, // Rule ID 1894 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1855:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1894, GIR_Done, // Label 830: @35145 GIM_Try, /*On fail goto*//*Label 831*/ 35211, // Rule ID 1898 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1856:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<>:$pos, GPRnopc:{ *:[i32] }:$a) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1898, GIR_Done, // Label 831: @35211 GIM_Try, /*On fail goto*//*Label 832*/ 35280, // Rule ID 2130 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1855:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2130, GIR_Done, // Label 832: @35280 GIM_Try, /*On fail goto*//*Label 833*/ 35346, // Rule ID 2132 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1856:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<>:$pos, GPR:{ *:[i32] }:$a) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2132, GIR_Done, // Label 833: @35346 GIM_Try, /*On fail goto*//*Label 834*/ 35424, // Rule ID 3326 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1618:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3326, GIR_Done, // Label 834: @35424 GIM_Try, /*On fail goto*//*Label 835*/ 35502, // Rule ID 3328 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1618:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3328, GIR_Done, // Label 835: @35502 GIM_Try, /*On fail goto*//*Label 836*/ 35580, // Rule ID 3330 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1618:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3330, GIR_Done, // Label 836: @35580 GIM_Try, /*On fail goto*//*Label 837*/ 35643, // Rule ID 1640 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 1673:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1640, GIR_Done, // Label 837: @35643 GIM_Try, /*On fail goto*//*Label 838*/ 35706, // Rule ID 1641 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2i32] } 1674:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1641, GIR_Done, // Label 838: @35706 GIM_Try, /*On fail goto*//*Label 839*/ 35769, // Rule ID 1642 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 1676:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1642, GIR_Done, // Label 839: @35769 GIM_Try, /*On fail goto*//*Label 840*/ 35832, // Rule ID 1643 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v2f32] } 1677:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1643, GIR_Done, // Label 840: @35832 GIM_Try, /*On fail goto*//*Label 841*/ 35895, // Rule ID 1644 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 1673:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1644, GIR_Done, // Label 841: @35895 GIM_Try, /*On fail goto*//*Label 842*/ 35958, // Rule ID 1645 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i16] } 1674:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1645, GIR_Done, // Label 842: @35958 GIM_Try, /*On fail goto*//*Label 843*/ 36021, // Rule ID 1646 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 1676:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1646, GIR_Done, // Label 843: @36021 GIM_Try, /*On fail goto*//*Label 844*/ 36084, // Rule ID 1647 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f16] } 1677:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1647, GIR_Done, // Label 844: @36084 GIM_Try, /*On fail goto*//*Label 845*/ 36147, // Rule ID 1648 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1673:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1648, GIR_Done, // Label 845: @36147 GIM_Try, /*On fail goto*//*Label 846*/ 36210, // Rule ID 1649 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1674:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1649, GIR_Done, // Label 846: @36210 GIM_Try, /*On fail goto*//*Label 847*/ 36273, // Rule ID 1650 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 1676:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1650, GIR_Done, // Label 847: @36273 GIM_Try, /*On fail goto*//*Label 848*/ 36336, // Rule ID 1651 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 1677:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1651, GIR_Done, // Label 848: @36336 GIM_Try, /*On fail goto*//*Label 849*/ 36399, // Rule ID 1652 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1673:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1652, GIR_Done, // Label 849: @36399 GIM_Try, /*On fail goto*//*Label 850*/ 36462, // Rule ID 1653 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1674:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1653, GIR_Done, // Label 850: @36462 GIM_Try, /*On fail goto*//*Label 851*/ 36525, // Rule ID 1654 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 1676:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1654, GIR_Done, // Label 851: @36525 GIM_Try, /*On fail goto*//*Label 852*/ 36588, // Rule ID 1655 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 1677:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1655, GIR_Done, // Label 852: @36588 GIM_Try, /*On fail goto*//*Label 853*/ 36651, // Rule ID 1713 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1569:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQSHL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1713, GIR_Done, // Label 853: @36651 GIM_Try, /*On fail goto*//*Label 854*/ 36714, // Rule ID 1714 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_srshr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1571:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SRSHR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1714, GIR_Done, // Label 854: @36714 GIM_Try, /*On fail goto*//*Label 855*/ 36777, // Rule ID 1715 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1576:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQSHL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1715, GIR_Done, // Label 855: @36777 GIM_Try, /*On fail goto*//*Label 856*/ 36840, // Rule ID 1716 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_urshr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[i32] } 1578:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_URSHR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1716, GIR_Done, // Label 856: @36840 GIM_Try, /*On fail goto*//*Label 857*/ 36899, // Rule ID 107 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1780:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 107, GIR_Done, // Label 857: @36899 GIM_Try, /*On fail goto*//*Label 858*/ 36958, // Rule ID 108 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1779:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 108, GIR_Done, // Label 858: @36958 GIM_Try, /*On fail goto*//*Label 859*/ 37017, // Rule ID 109 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1784:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 109, GIR_Done, // Label 859: @37017 GIM_Try, /*On fail goto*//*Label 860*/ 37076, // Rule ID 110 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1785:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 110, GIR_Done, // Label 860: @37076 GIM_Try, /*On fail goto*//*Label 861*/ 37135, // Rule ID 113 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 113, GIR_Done, // Label 861: @37135 GIM_Try, /*On fail goto*//*Label 862*/ 37194, // Rule ID 114 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 114, GIR_Done, // Label 862: @37194 GIM_Try, /*On fail goto*//*Label 863*/ 37253, // Rule ID 115 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1847:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 115, GIR_Done, // Label 863: @37253 GIM_Try, /*On fail goto*//*Label 864*/ 37312, // Rule ID 116 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1848:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 116, GIR_Done, // Label 864: @37312 GIM_Try, /*On fail goto*//*Label 865*/ 37371, // Rule ID 117 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1851:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 117, GIR_Done, // Label 865: @37371 GIM_Try, /*On fail goto*//*Label 866*/ 37430, // Rule ID 118 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1852:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 118, GIR_Done, // Label 866: @37430 GIM_Try, /*On fail goto*//*Label 867*/ 37489, // Rule ID 119 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1781:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 119, GIR_Done, // Label 867: @37489 GIM_Try, /*On fail goto*//*Label 868*/ 37548, // Rule ID 120 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1782:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 120, GIR_Done, // Label 868: @37548 GIM_Try, /*On fail goto*//*Label 869*/ 37607, // Rule ID 121 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1849:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 121, GIR_Done, // Label 869: @37607 GIM_Try, /*On fail goto*//*Label 870*/ 37666, // Rule ID 122 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1850:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 122, GIR_Done, // Label 870: @37666 GIM_Try, /*On fail goto*//*Label 871*/ 37725, // Rule ID 135 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1793:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 135, GIR_Done, // Label 871: @37725 GIM_Try, /*On fail goto*//*Label 872*/ 37784, // Rule ID 136 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1791:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 136, GIR_Done, // Label 872: @37784 GIM_Try, /*On fail goto*//*Label 873*/ 37843, // Rule ID 137 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 137, GIR_Done, // Label 873: @37843 GIM_Try, /*On fail goto*//*Label 874*/ 37902, // Rule ID 138 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1794:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 138, GIR_Done, // Label 874: @37902 GIM_Try, /*On fail goto*//*Label 875*/ 37961, // Rule ID 139 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1795:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 139, GIR_Done, // Label 875: @37961 GIM_Try, /*On fail goto*//*Label 876*/ 38020, // Rule ID 140 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1796:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 140, GIR_Done, // Label 876: @38020 GIM_Try, /*On fail goto*//*Label 877*/ 38079, // Rule ID 141 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1842:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 141, GIR_Done, // Label 877: @38079 GIM_Try, /*On fail goto*//*Label 878*/ 38138, // Rule ID 142 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1840:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 142, GIR_Done, // Label 878: @38138 GIM_Try, /*On fail goto*//*Label 879*/ 38197, // Rule ID 143 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1841:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 143, GIR_Done, // Label 879: @38197 GIM_Try, /*On fail goto*//*Label 880*/ 38256, // Rule ID 144 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1843:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 144, GIR_Done, // Label 880: @38256 GIM_Try, /*On fail goto*//*Label 881*/ 38315, // Rule ID 145 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1844:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 145, GIR_Done, // Label 881: @38315 GIM_Try, /*On fail goto*//*Label 882*/ 38374, // Rule ID 146 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1845:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 146, GIR_Done, // Label 882: @38374 GIM_Try, /*On fail goto*//*Label 883*/ 38433, // Rule ID 147 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1853:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 147, GIR_Done, // Label 883: @38433 GIM_Try, /*On fail goto*//*Label 884*/ 38485, // Rule ID 206 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1507:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 206, GIR_Done, // Label 884: @38485 GIM_Try, /*On fail goto*//*Label 885*/ 38537, // Rule ID 207 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1508:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 207, GIR_Done, // Label 885: @38537 GIM_Try, /*On fail goto*//*Label 886*/ 38589, // Rule ID 208 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1511:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 208, GIR_Done, // Label 886: @38589 GIM_Try, /*On fail goto*//*Label 887*/ 38641, // Rule ID 209 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1509:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 209, GIR_Done, // Label 887: @38641 GIM_Try, /*On fail goto*//*Label 888*/ 38693, // Rule ID 210 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1512:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 210, GIR_Done, // Label 888: @38693 GIM_Try, /*On fail goto*//*Label 889*/ 38745, // Rule ID 211 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1510:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 211, GIR_Done, // Label 889: @38745 GIM_Try, /*On fail goto*//*Label 890*/ 38804, // Rule ID 438 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1779:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 438, GIR_Done, // Label 890: @38804 GIM_Try, /*On fail goto*//*Label 891*/ 38863, // Rule ID 439 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1780:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 439, GIR_Done, // Label 891: @38863 GIM_Try, /*On fail goto*//*Label 892*/ 38922, // Rule ID 440 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1781:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 440, GIR_Done, // Label 892: @38922 GIM_Try, /*On fail goto*//*Label 893*/ 38981, // Rule ID 441 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1852:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 441, GIR_Done, // Label 893: @38981 GIM_Try, /*On fail goto*//*Label 894*/ 39040, // Rule ID 442 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 442, GIR_Done, // Label 894: @39040 GIM_Try, /*On fail goto*//*Label 895*/ 39099, // Rule ID 443 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 443, GIR_Done, // Label 895: @39099 GIM_Try, /*On fail goto*//*Label 896*/ 39158, // Rule ID 444 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 444, GIR_Done, // Label 896: @39158 GIM_Try, /*On fail goto*//*Label 897*/ 39217, // Rule ID 445 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1847:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 445, GIR_Done, // Label 897: @39217 GIM_Try, /*On fail goto*//*Label 898*/ 39276, // Rule ID 446 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1848:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 446, GIR_Done, // Label 898: @39276 GIM_Try, /*On fail goto*//*Label 899*/ 39335, // Rule ID 447 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1849:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 447, GIR_Done, // Label 899: @39335 GIM_Try, /*On fail goto*//*Label 900*/ 39394, // Rule ID 448 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1850:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 448, GIR_Done, // Label 900: @39394 GIM_Try, /*On fail goto*//*Label 901*/ 39453, // Rule ID 449 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1851:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 449, GIR_Done, // Label 901: @39453 GIM_Try, /*On fail goto*//*Label 902*/ 39512, // Rule ID 462 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 462, GIR_Done, // Label 902: @39512 GIM_Try, /*On fail goto*//*Label 903*/ 39571, // Rule ID 463 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1791:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 463, GIR_Done, // Label 903: @39571 GIM_Try, /*On fail goto*//*Label 904*/ 39630, // Rule ID 464 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 464, GIR_Done, // Label 904: @39630 GIM_Try, /*On fail goto*//*Label 905*/ 39689, // Rule ID 465 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1794:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 465, GIR_Done, // Label 905: @39689 GIM_Try, /*On fail goto*//*Label 906*/ 39748, // Rule ID 466 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1795:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 466, GIR_Done, // Label 906: @39748 GIM_Try, /*On fail goto*//*Label 907*/ 39807, // Rule ID 467 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1796:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 467, GIR_Done, // Label 907: @39807 GIM_Try, /*On fail goto*//*Label 908*/ 39866, // Rule ID 468 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1842:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 468, GIR_Done, // Label 908: @39866 GIM_Try, /*On fail goto*//*Label 909*/ 39925, // Rule ID 469 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1840:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 469, GIR_Done, // Label 909: @39925 GIM_Try, /*On fail goto*//*Label 910*/ 39984, // Rule ID 470 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1841:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 470, GIR_Done, // Label 910: @39984 GIM_Try, /*On fail goto*//*Label 911*/ 40043, // Rule ID 471 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1843:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 471, GIR_Done, // Label 911: @40043 GIM_Try, /*On fail goto*//*Label 912*/ 40102, // Rule ID 472 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1844:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 472, GIR_Done, // Label 912: @40102 GIM_Try, /*On fail goto*//*Label 913*/ 40161, // Rule ID 473 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1845:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 473, GIR_Done, // Label 913: @40161 GIM_Try, /*On fail goto*//*Label 914*/ 40220, // Rule ID 474 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1853:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 474, GIR_Done, // Label 914: @40220 GIM_Try, /*On fail goto*//*Label 915*/ 40279, // Rule ID 530 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1811:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 530, GIR_Done, // Label 915: @40279 GIM_Try, /*On fail goto*//*Label 916*/ 40338, // Rule ID 531 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1812:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 531, GIR_Done, // Label 916: @40338 GIM_Try, /*On fail goto*//*Label 917*/ 40397, // Rule ID 532 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1819:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 532, GIR_Done, // Label 917: @40397 GIM_Try, /*On fail goto*//*Label 918*/ 40456, // Rule ID 533 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1820:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 533, GIR_Done, // Label 918: @40456 GIM_Try, /*On fail goto*//*Label 919*/ 40508, // Rule ID 547 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1507:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 547, GIR_Done, // Label 919: @40508 GIM_Try, /*On fail goto*//*Label 920*/ 40560, // Rule ID 548 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1508:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 548, GIR_Done, // Label 920: @40560 GIM_Try, /*On fail goto*//*Label 921*/ 40612, // Rule ID 549 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1511:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 549, GIR_Done, // Label 921: @40612 GIM_Try, /*On fail goto*//*Label 922*/ 40664, // Rule ID 550 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1509:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 550, GIR_Done, // Label 922: @40664 GIM_Try, /*On fail goto*//*Label 923*/ 40716, // Rule ID 551 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1512:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 551, GIR_Done, // Label 923: @40716 GIM_Try, /*On fail goto*//*Label 924*/ 40768, // Rule ID 552 // GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1510:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 552, GIR_Done, // Label 924: @40768 GIM_Try, /*On fail goto*//*Label 925*/ 40827, // Rule ID 795 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1685:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 795, GIR_Done, // Label 925: @40827 GIM_Try, /*On fail goto*//*Label 926*/ 40886, // Rule ID 796 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1685:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 796, GIR_Done, // Label 926: @40886 GIM_Try, /*On fail goto*//*Label 927*/ 40945, // Rule ID 797 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1685:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 797, GIR_Done, // Label 927: @40945 GIM_Try, /*On fail goto*//*Label 928*/ 41004, // Rule ID 798 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1685:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 798, GIR_Done, // Label 928: @41004 GIM_Try, /*On fail goto*//*Label 929*/ 41063, // Rule ID 799 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1685:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 799, GIR_Done, // Label 929: @41063 GIM_Try, /*On fail goto*//*Label 930*/ 41122, // Rule ID 800 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1685:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 800, GIR_Done, // Label 930: @41122 GIM_Try, /*On fail goto*//*Label 931*/ 41181, // Rule ID 801 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1686:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 801, GIR_Done, // Label 931: @41181 GIM_Try, /*On fail goto*//*Label 932*/ 41240, // Rule ID 802 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1686:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 802, GIR_Done, // Label 932: @41240 GIM_Try, /*On fail goto*//*Label 933*/ 41299, // Rule ID 803 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1686:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 803, GIR_Done, // Label 933: @41299 GIM_Try, /*On fail goto*//*Label 934*/ 41358, // Rule ID 804 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1686:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 804, GIR_Done, // Label 934: @41358 GIM_Try, /*On fail goto*//*Label 935*/ 41417, // Rule ID 805 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1686:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 805, GIR_Done, // Label 935: @41417 GIM_Try, /*On fail goto*//*Label 936*/ 41476, // Rule ID 806 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1686:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 806, GIR_Done, // Label 936: @41476 GIM_Try, /*On fail goto*//*Label 937*/ 41535, // Rule ID 807 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1743:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 807, GIR_Done, // Label 937: @41535 GIM_Try, /*On fail goto*//*Label 938*/ 41594, // Rule ID 808 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1743:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 808, GIR_Done, // Label 938: @41594 GIM_Try, /*On fail goto*//*Label 939*/ 41653, // Rule ID 809 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1743:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 809, GIR_Done, // Label 939: @41653 GIM_Try, /*On fail goto*//*Label 940*/ 41712, // Rule ID 810 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1743:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 810, GIR_Done, // Label 940: @41712 GIM_Try, /*On fail goto*//*Label 941*/ 41771, // Rule ID 811 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1743:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 811, GIR_Done, // Label 941: @41771 GIM_Try, /*On fail goto*//*Label 942*/ 41830, // Rule ID 812 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1743:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 812, GIR_Done, // Label 942: @41830 GIM_Try, /*On fail goto*//*Label 943*/ 41889, // Rule ID 813 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1744:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 813, GIR_Done, // Label 943: @41889 GIM_Try, /*On fail goto*//*Label 944*/ 41948, // Rule ID 814 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1744:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 814, GIR_Done, // Label 944: @41948 GIM_Try, /*On fail goto*//*Label 945*/ 42007, // Rule ID 815 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1744:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 815, GIR_Done, // Label 945: @42007 GIM_Try, /*On fail goto*//*Label 946*/ 42066, // Rule ID 816 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1744:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 816, GIR_Done, // Label 946: @42066 GIM_Try, /*On fail goto*//*Label 947*/ 42125, // Rule ID 817 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1744:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 817, GIR_Done, // Label 947: @42125 GIM_Try, /*On fail goto*//*Label 948*/ 42184, // Rule ID 818 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1744:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 818, GIR_Done, // Label 948: @42184 GIM_Try, /*On fail goto*//*Label 949*/ 42243, // Rule ID 835 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1740:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 835, GIR_Done, // Label 949: @42243 GIM_Try, /*On fail goto*//*Label 950*/ 42302, // Rule ID 836 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1740:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 836, GIR_Done, // Label 950: @42302 GIM_Try, /*On fail goto*//*Label 951*/ 42361, // Rule ID 837 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1740:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 837, GIR_Done, // Label 951: @42361 GIM_Try, /*On fail goto*//*Label 952*/ 42420, // Rule ID 844 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1711:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 844, GIR_Done, // Label 952: @42420 GIM_Try, /*On fail goto*//*Label 953*/ 42479, // Rule ID 845 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1711:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 845, GIR_Done, // Label 953: @42479 GIM_Try, /*On fail goto*//*Label 954*/ 42538, // Rule ID 858 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1722:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 858, GIR_Done, // Label 954: @42538 GIM_Try, /*On fail goto*//*Label 955*/ 42597, // Rule ID 859 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1722:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 859, GIR_Done, // Label 955: @42597 GIM_Try, /*On fail goto*//*Label 956*/ 42656, // Rule ID 860 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1722:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 860, GIR_Done, // Label 956: @42656 GIM_Try, /*On fail goto*//*Label 957*/ 42715, // Rule ID 861 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1722:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 861, GIR_Done, // Label 957: @42715 GIM_Try, /*On fail goto*//*Label 958*/ 42774, // Rule ID 866 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1728:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 866, GIR_Done, // Label 958: @42774 GIM_Try, /*On fail goto*//*Label 959*/ 42833, // Rule ID 867 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1728:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 867, GIR_Done, // Label 959: @42833 GIM_Try, /*On fail goto*//*Label 960*/ 42892, // Rule ID 868 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1728:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 868, GIR_Done, // Label 960: @42892 GIM_Try, /*On fail goto*//*Label 961*/ 42951, // Rule ID 869 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1728:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 869, GIR_Done, // Label 961: @42951 GIM_Try, /*On fail goto*//*Label 962*/ 43010, // Rule ID 880 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1708:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 880, GIR_Done, // Label 962: @43010 GIM_Try, /*On fail goto*//*Label 963*/ 43062, // Rule ID 881 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1708:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 881, GIR_Done, // Label 963: @43062 GIM_Try, /*On fail goto*//*Label 964*/ 43121, // Rule ID 886 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1723:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 886, GIR_Done, // Label 964: @43121 GIM_Try, /*On fail goto*//*Label 965*/ 43180, // Rule ID 887 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1723:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 887, GIR_Done, // Label 965: @43180 GIM_Try, /*On fail goto*//*Label 966*/ 43239, // Rule ID 982 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1687:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 982, GIR_Done, // Label 966: @43239 GIM_Try, /*On fail goto*//*Label 967*/ 43298, // Rule ID 983 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1687:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 983, GIR_Done, // Label 967: @43298 GIM_Try, /*On fail goto*//*Label 968*/ 43357, // Rule ID 984 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1687:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 984, GIR_Done, // Label 968: @43357 GIM_Try, /*On fail goto*//*Label 969*/ 43416, // Rule ID 985 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1687:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 985, GIR_Done, // Label 969: @43416 GIM_Try, /*On fail goto*//*Label 970*/ 43475, // Rule ID 986 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1687:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 986, GIR_Done, // Label 970: @43475 GIM_Try, /*On fail goto*//*Label 971*/ 43534, // Rule ID 987 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1687:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 987, GIR_Done, // Label 971: @43534 GIM_Try, /*On fail goto*//*Label 972*/ 43593, // Rule ID 988 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1688:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 988, GIR_Done, // Label 972: @43593 GIM_Try, /*On fail goto*//*Label 973*/ 43652, // Rule ID 989 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1688:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 989, GIR_Done, // Label 973: @43652 GIM_Try, /*On fail goto*//*Label 974*/ 43711, // Rule ID 990 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1688:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 990, GIR_Done, // Label 974: @43711 GIM_Try, /*On fail goto*//*Label 975*/ 43770, // Rule ID 991 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1688:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 991, GIR_Done, // Label 975: @43770 GIM_Try, /*On fail goto*//*Label 976*/ 43829, // Rule ID 992 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1688:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 992, GIR_Done, // Label 976: @43829 GIM_Try, /*On fail goto*//*Label 977*/ 43888, // Rule ID 993 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1688:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 993, GIR_Done, // Label 977: @43888 GIM_Try, /*On fail goto*//*Label 978*/ 43947, // Rule ID 1010 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1756:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1010, GIR_Done, // Label 978: @43947 GIM_Try, /*On fail goto*//*Label 979*/ 44006, // Rule ID 1011 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1756:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1011, GIR_Done, // Label 979: @44006 GIM_Try, /*On fail goto*//*Label 980*/ 44065, // Rule ID 1012 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1756:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1012, GIR_Done, // Label 980: @44065 GIM_Try, /*On fail goto*//*Label 981*/ 44124, // Rule ID 1105 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1665:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1105, GIR_Done, // Label 981: @44124 GIM_Try, /*On fail goto*//*Label 982*/ 44183, // Rule ID 1106 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1665:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1106, GIR_Done, // Label 982: @44183 GIM_Try, /*On fail goto*//*Label 983*/ 44242, // Rule ID 1107 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1665:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1107, GIR_Done, // Label 983: @44242 GIM_Try, /*On fail goto*//*Label 984*/ 44301, // Rule ID 1108 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1665:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1108, GIR_Done, // Label 984: @44301 GIM_Try, /*On fail goto*//*Label 985*/ 44360, // Rule ID 1109 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1666:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1109, GIR_Done, // Label 985: @44360 GIM_Try, /*On fail goto*//*Label 986*/ 44419, // Rule ID 1110 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1666:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1110, GIR_Done, // Label 986: @44419 GIM_Try, /*On fail goto*//*Label 987*/ 44478, // Rule ID 1111 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1666:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1111, GIR_Done, // Label 987: @44478 GIM_Try, /*On fail goto*//*Label 988*/ 44537, // Rule ID 1112 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1666:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1112, GIR_Done, // Label 988: @44537 GIM_Try, /*On fail goto*//*Label 989*/ 44596, // Rule ID 1145 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1145, GIR_Done, // Label 989: @44596 GIM_Try, /*On fail goto*//*Label 990*/ 44655, // Rule ID 1146 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1146, GIR_Done, // Label 990: @44655 GIM_Try, /*On fail goto*//*Label 991*/ 44714, // Rule ID 1147 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1147, GIR_Done, // Label 991: @44714 GIM_Try, /*On fail goto*//*Label 992*/ 44773, // Rule ID 1148 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1148, GIR_Done, // Label 992: @44773 GIM_Try, /*On fail goto*//*Label 993*/ 44832, // Rule ID 1149 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1149, GIR_Done, // Label 993: @44832 GIM_Try, /*On fail goto*//*Label 994*/ 44891, // Rule ID 1150 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1662:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1150, GIR_Done, // Label 994: @44891 GIM_Try, /*On fail goto*//*Label 995*/ 44950, // Rule ID 1151 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1151, GIR_Done, // Label 995: @44950 GIM_Try, /*On fail goto*//*Label 996*/ 45009, // Rule ID 1152 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1152, GIR_Done, // Label 996: @45009 GIM_Try, /*On fail goto*//*Label 997*/ 45068, // Rule ID 1153 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1663:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1153, GIR_Done, // Label 997: @45068 GIM_Try, /*On fail goto*//*Label 998*/ 45127, // Rule ID 1154 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1663:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1154, GIR_Done, // Label 998: @45127 GIM_Try, /*On fail goto*//*Label 999*/ 45186, // Rule ID 1155 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1155, GIR_Done, // Label 999: @45186 GIM_Try, /*On fail goto*//*Label 1000*/ 45245, // Rule ID 1156 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1663:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1156, GIR_Done, // Label 1000: @45245 GIM_Try, /*On fail goto*//*Label 1001*/ 45304, // Rule ID 1157 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1157, GIR_Done, // Label 1001: @45304 GIM_Try, /*On fail goto*//*Label 1002*/ 45363, // Rule ID 1158 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1662:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1158, GIR_Done, // Label 1002: @45363 GIM_Try, /*On fail goto*//*Label 1003*/ 45422, // Rule ID 1159 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1159, GIR_Done, // Label 1003: @45422 GIM_Try, /*On fail goto*//*Label 1004*/ 45481, // Rule ID 1160 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1662:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1160, GIR_Done, // Label 1004: @45481 GIM_Try, /*On fail goto*//*Label 1005*/ 45540, // Rule ID 1225 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1714:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1225, GIR_Done, // Label 1005: @45540 GIM_Try, /*On fail goto*//*Label 1006*/ 45599, // Rule ID 1226 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1714:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1226, GIR_Done, // Label 1006: @45599 GIM_Try, /*On fail goto*//*Label 1007*/ 45658, // Rule ID 1227 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1714:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1227, GIR_Done, // Label 1007: @45658 GIM_Try, /*On fail goto*//*Label 1008*/ 45717, // Rule ID 1228 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1714:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1228, GIR_Done, // Label 1008: @45717 GIM_Try, /*On fail goto*//*Label 1009*/ 45776, // Rule ID 1229 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1714:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1229, GIR_Done, // Label 1009: @45776 GIM_Try, /*On fail goto*//*Label 1010*/ 45835, // Rule ID 1242 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1712:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1242, GIR_Done, // Label 1010: @45835 GIM_Try, /*On fail goto*//*Label 1011*/ 45894, // Rule ID 1243 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1712:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1243, GIR_Done, // Label 1011: @45894 GIM_Try, /*On fail goto*//*Label 1012*/ 45953, // Rule ID 1244 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1712:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1244, GIR_Done, // Label 1012: @45953 GIM_Try, /*On fail goto*//*Label 1013*/ 46012, // Rule ID 1245 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1712:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1245, GIR_Done, // Label 1013: @46012 GIM_Try, /*On fail goto*//*Label 1014*/ 46071, // Rule ID 1246 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1712:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1246, GIR_Done, // Label 1014: @46071 GIM_Try, /*On fail goto*//*Label 1015*/ 46130, // Rule ID 1247 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1712:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1247, GIR_Done, // Label 1015: @46130 GIM_Try, /*On fail goto*//*Label 1016*/ 46189, // Rule ID 1248 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1713:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1248, GIR_Done, // Label 1016: @46189 GIM_Try, /*On fail goto*//*Label 1017*/ 46248, // Rule ID 1249 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1713:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1249, GIR_Done, // Label 1017: @46248 GIM_Try, /*On fail goto*//*Label 1018*/ 46307, // Rule ID 1250 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1713:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1250, GIR_Done, // Label 1018: @46307 GIM_Try, /*On fail goto*//*Label 1019*/ 46366, // Rule ID 1251 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1713:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1251, GIR_Done, // Label 1019: @46366 GIM_Try, /*On fail goto*//*Label 1020*/ 46425, // Rule ID 1252 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1713:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1252, GIR_Done, // Label 1020: @46425 GIM_Try, /*On fail goto*//*Label 1021*/ 46484, // Rule ID 1253 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1713:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1253, GIR_Done, // Label 1021: @46484 GIM_Try, /*On fail goto*//*Label 1022*/ 46543, // Rule ID 1254 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1717:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1254, GIR_Done, // Label 1022: @46543 GIM_Try, /*On fail goto*//*Label 1023*/ 46602, // Rule ID 1255 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1717:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1255, GIR_Done, // Label 1023: @46602 GIM_Try, /*On fail goto*//*Label 1024*/ 46661, // Rule ID 1256 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1717:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1256, GIR_Done, // Label 1024: @46661 GIM_Try, /*On fail goto*//*Label 1025*/ 46720, // Rule ID 1257 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1718:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1257, GIR_Done, // Label 1025: @46720 GIM_Try, /*On fail goto*//*Label 1026*/ 46779, // Rule ID 1258 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1718:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1258, GIR_Done, // Label 1026: @46779 GIM_Try, /*On fail goto*//*Label 1027*/ 46838, // Rule ID 1259 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1718:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1259, GIR_Done, // Label 1027: @46838 GIM_Try, /*On fail goto*//*Label 1028*/ 46897, // Rule ID 1260 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1717:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1260, GIR_Done, // Label 1028: @46897 GIM_Try, /*On fail goto*//*Label 1029*/ 46956, // Rule ID 1261 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1717:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1261, GIR_Done, // Label 1029: @46956 GIM_Try, /*On fail goto*//*Label 1030*/ 47015, // Rule ID 1262 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1719:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1262, GIR_Done, // Label 1030: @47015 GIM_Try, /*On fail goto*//*Label 1031*/ 47074, // Rule ID 1263 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1719:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1263, GIR_Done, // Label 1031: @47074 GIM_Try, /*On fail goto*//*Label 1032*/ 47133, // Rule ID 1264 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1719:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1264, GIR_Done, // Label 1032: @47133 GIM_Try, /*On fail goto*//*Label 1033*/ 47192, // Rule ID 1265 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1720:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1265, GIR_Done, // Label 1033: @47192 GIM_Try, /*On fail goto*//*Label 1034*/ 47251, // Rule ID 1266 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1720:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1266, GIR_Done, // Label 1034: @47251 GIM_Try, /*On fail goto*//*Label 1035*/ 47310, // Rule ID 1267 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1720:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1267, GIR_Done, // Label 1035: @47310 GIM_Try, /*On fail goto*//*Label 1036*/ 47369, // Rule ID 1268 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1719:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1268, GIR_Done, // Label 1036: @47369 GIM_Try, /*On fail goto*//*Label 1037*/ 47428, // Rule ID 1269 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1719:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1269, GIR_Done, // Label 1037: @47428 GIM_Try, /*On fail goto*//*Label 1038*/ 47487, // Rule ID 1276 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1742:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1276, GIR_Done, // Label 1038: @47487 GIM_Try, /*On fail goto*//*Label 1039*/ 47546, // Rule ID 1277 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1742:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1277, GIR_Done, // Label 1039: @47546 GIM_Try, /*On fail goto*//*Label 1040*/ 47605, // Rule ID 1278 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1742:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1278, GIR_Done, // Label 1040: @47605 GIM_Try, /*On fail goto*//*Label 1041*/ 47664, // Rule ID 1279 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1742:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1279, GIR_Done, // Label 1041: @47664 GIM_Try, /*On fail goto*//*Label 1042*/ 47723, // Rule ID 1286 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1755:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1286, GIR_Done, // Label 1042: @47723 GIM_Try, /*On fail goto*//*Label 1043*/ 47782, // Rule ID 1287 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1755:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1287, GIR_Done, // Label 1043: @47782 GIM_Try, /*On fail goto*//*Label 1044*/ 47841, // Rule ID 1288 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1755:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1288, GIR_Done, // Label 1044: @47841 GIM_Try, /*On fail goto*//*Label 1045*/ 47900, // Rule ID 1289 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1755:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1289, GIR_Done, // Label 1045: @47900 GIM_Try, /*On fail goto*//*Label 1046*/ 47959, // Rule ID 1290 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1758:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1290, GIR_Done, // Label 1046: @47959 GIM_Try, /*On fail goto*//*Label 1047*/ 48018, // Rule ID 1291 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1758:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1291, GIR_Done, // Label 1047: @48018 GIM_Try, /*On fail goto*//*Label 1048*/ 48077, // Rule ID 1292 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1758:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1292, GIR_Done, // Label 1048: @48077 GIM_Try, /*On fail goto*//*Label 1049*/ 48136, // Rule ID 1293 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1758:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1293, GIR_Done, // Label 1049: @48136 GIM_Try, /*On fail goto*//*Label 1050*/ 48195, // Rule ID 1294 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1758:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1294, GIR_Done, // Label 1050: @48195 GIM_Try, /*On fail goto*//*Label 1051*/ 48254, // Rule ID 1295 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1758:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1295, GIR_Done, // Label 1051: @48254 GIM_Try, /*On fail goto*//*Label 1052*/ 48313, // Rule ID 1296 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1758:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1296, GIR_Done, // Label 1052: @48313 GIM_Try, /*On fail goto*//*Label 1053*/ 48372, // Rule ID 1297 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1758:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1297, GIR_Done, // Label 1053: @48372 GIM_Try, /*On fail goto*//*Label 1054*/ 48431, // Rule ID 1298 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1759:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1298, GIR_Done, // Label 1054: @48431 GIM_Try, /*On fail goto*//*Label 1055*/ 48490, // Rule ID 1299 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1759:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1299, GIR_Done, // Label 1055: @48490 GIM_Try, /*On fail goto*//*Label 1056*/ 48549, // Rule ID 1300 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1759:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1300, GIR_Done, // Label 1056: @48549 GIM_Try, /*On fail goto*//*Label 1057*/ 48608, // Rule ID 1301 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1759:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1301, GIR_Done, // Label 1057: @48608 GIM_Try, /*On fail goto*//*Label 1058*/ 48667, // Rule ID 1302 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1759:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1302, GIR_Done, // Label 1058: @48667 GIM_Try, /*On fail goto*//*Label 1059*/ 48726, // Rule ID 1303 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1759:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1303, GIR_Done, // Label 1059: @48726 GIM_Try, /*On fail goto*//*Label 1060*/ 48785, // Rule ID 1304 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1759:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1304, GIR_Done, // Label 1060: @48785 GIM_Try, /*On fail goto*//*Label 1061*/ 48844, // Rule ID 1305 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1759:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1305, GIR_Done, // Label 1061: @48844 GIM_Try, /*On fail goto*//*Label 1062*/ 48903, // Rule ID 1339 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1752:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1339, GIR_Done, // Label 1062: @48903 GIM_Try, /*On fail goto*//*Label 1063*/ 48962, // Rule ID 1340 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1752:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1340, GIR_Done, // Label 1063: @48962 GIM_Try, /*On fail goto*//*Label 1064*/ 49021, // Rule ID 1341 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1752:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1341, GIR_Done, // Label 1064: @49021 GIM_Try, /*On fail goto*//*Label 1065*/ 49080, // Rule ID 1342 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1752:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1342, GIR_Done, // Label 1065: @49080 GIM_Try, /*On fail goto*//*Label 1066*/ 49139, // Rule ID 1343 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1752:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1343, GIR_Done, // Label 1066: @49139 GIM_Try, /*On fail goto*//*Label 1067*/ 49198, // Rule ID 1344 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1752:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1344, GIR_Done, // Label 1067: @49198 GIM_Try, /*On fail goto*//*Label 1068*/ 49257, // Rule ID 1345 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1752:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1345, GIR_Done, // Label 1068: @49257 GIM_Try, /*On fail goto*//*Label 1069*/ 49316, // Rule ID 1346 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1752:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1346, GIR_Done, // Label 1069: @49316 GIM_Try, /*On fail goto*//*Label 1070*/ 49375, // Rule ID 1347 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1753:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1347, GIR_Done, // Label 1070: @49375 GIM_Try, /*On fail goto*//*Label 1071*/ 49434, // Rule ID 1348 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1753:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1348, GIR_Done, // Label 1071: @49434 GIM_Try, /*On fail goto*//*Label 1072*/ 49493, // Rule ID 1349 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1753:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1349, GIR_Done, // Label 1072: @49493 GIM_Try, /*On fail goto*//*Label 1073*/ 49552, // Rule ID 1350 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1753:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1350, GIR_Done, // Label 1073: @49552 GIM_Try, /*On fail goto*//*Label 1074*/ 49611, // Rule ID 1351 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1753:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1351, GIR_Done, // Label 1074: @49611 GIM_Try, /*On fail goto*//*Label 1075*/ 49670, // Rule ID 1352 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1753:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1352, GIR_Done, // Label 1075: @49670 GIM_Try, /*On fail goto*//*Label 1076*/ 49729, // Rule ID 1353 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1753:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1353, GIR_Done, // Label 1076: @49729 GIM_Try, /*On fail goto*//*Label 1077*/ 49788, // Rule ID 1354 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1753:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1354, GIR_Done, // Label 1077: @49788 GIM_Try, /*On fail goto*//*Label 1078*/ 49847, // Rule ID 1374 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1737:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1374, GIR_Done, // Label 1078: @49847 GIM_Try, /*On fail goto*//*Label 1079*/ 49906, // Rule ID 1375 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1737:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1375, GIR_Done, // Label 1079: @49906 GIM_Try, /*On fail goto*//*Label 1080*/ 49965, // Rule ID 1376 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1737:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1376, GIR_Done, // Label 1080: @49965 GIM_Try, /*On fail goto*//*Label 1081*/ 50024, // Rule ID 1377 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1737:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1377, GIR_Done, // Label 1081: @50024 GIM_Try, /*On fail goto*//*Label 1082*/ 50083, // Rule ID 1378 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1737:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1378, GIR_Done, // Label 1082: @50083 GIM_Try, /*On fail goto*//*Label 1083*/ 50142, // Rule ID 1379 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1737:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1379, GIR_Done, // Label 1083: @50142 GIM_Try, /*On fail goto*//*Label 1084*/ 50201, // Rule ID 1380 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1737:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1380, GIR_Done, // Label 1084: @50201 GIM_Try, /*On fail goto*//*Label 1085*/ 50260, // Rule ID 1381 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1737:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1381, GIR_Done, // Label 1085: @50260 GIM_Try, /*On fail goto*//*Label 1086*/ 50319, // Rule ID 1382 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1739:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1382, GIR_Done, // Label 1086: @50319 GIM_Try, /*On fail goto*//*Label 1087*/ 50378, // Rule ID 1383 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1739:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1383, GIR_Done, // Label 1087: @50378 GIM_Try, /*On fail goto*//*Label 1088*/ 50437, // Rule ID 1384 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1739:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1384, GIR_Done, // Label 1088: @50437 GIM_Try, /*On fail goto*//*Label 1089*/ 50496, // Rule ID 1385 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1739:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1385, GIR_Done, // Label 1089: @50496 GIM_Try, /*On fail goto*//*Label 1090*/ 50555, // Rule ID 1386 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1739:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1386, GIR_Done, // Label 1090: @50555 GIM_Try, /*On fail goto*//*Label 1091*/ 50614, // Rule ID 1387 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1739:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1387, GIR_Done, // Label 1091: @50614 GIM_Try, /*On fail goto*//*Label 1092*/ 50673, // Rule ID 1388 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1739:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1388, GIR_Done, // Label 1092: @50673 GIM_Try, /*On fail goto*//*Label 1093*/ 50732, // Rule ID 1389 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1739:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1389, GIR_Done, // Label 1093: @50732 GIM_Try, /*On fail goto*//*Label 1094*/ 50791, // Rule ID 1423 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1732:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1423, GIR_Done, // Label 1094: @50791 GIM_Try, /*On fail goto*//*Label 1095*/ 50850, // Rule ID 1424 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1732:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1424, GIR_Done, // Label 1095: @50850 GIM_Try, /*On fail goto*//*Label 1096*/ 50909, // Rule ID 1425 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1732:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1425, GIR_Done, // Label 1096: @50909 GIM_Try, /*On fail goto*//*Label 1097*/ 50968, // Rule ID 1426 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1732:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1426, GIR_Done, // Label 1097: @50968 GIM_Try, /*On fail goto*//*Label 1098*/ 51027, // Rule ID 1427 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1732:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1427, GIR_Done, // Label 1098: @51027 GIM_Try, /*On fail goto*//*Label 1099*/ 51086, // Rule ID 1428 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1732:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1428, GIR_Done, // Label 1099: @51086 GIM_Try, /*On fail goto*//*Label 1100*/ 51145, // Rule ID 1429 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1732:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1429, GIR_Done, // Label 1100: @51145 GIM_Try, /*On fail goto*//*Label 1101*/ 51204, // Rule ID 1430 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1732:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1430, GIR_Done, // Label 1101: @51204 GIM_Try, /*On fail goto*//*Label 1102*/ 51263, // Rule ID 1431 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1733:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1431, GIR_Done, // Label 1102: @51263 GIM_Try, /*On fail goto*//*Label 1103*/ 51322, // Rule ID 1432 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1733:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1432, GIR_Done, // Label 1103: @51322 GIM_Try, /*On fail goto*//*Label 1104*/ 51381, // Rule ID 1433 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1733:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1433, GIR_Done, // Label 1104: @51381 GIM_Try, /*On fail goto*//*Label 1105*/ 51440, // Rule ID 1434 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1733:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1434, GIR_Done, // Label 1105: @51440 GIM_Try, /*On fail goto*//*Label 1106*/ 51499, // Rule ID 1435 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1733:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1435, GIR_Done, // Label 1106: @51499 GIM_Try, /*On fail goto*//*Label 1107*/ 51558, // Rule ID 1436 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1733:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1436, GIR_Done, // Label 1107: @51558 GIM_Try, /*On fail goto*//*Label 1108*/ 51617, // Rule ID 1437 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1733:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1437, GIR_Done, // Label 1108: @51617 GIM_Try, /*On fail goto*//*Label 1109*/ 51676, // Rule ID 1438 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1733:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1438, GIR_Done, // Label 1109: @51676 GIM_Try, /*On fail goto*//*Label 1110*/ 51728, // Rule ID 1703 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1646:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1703, GIR_Done, // Label 1110: @51728 GIM_Try, /*On fail goto*//*Label 1111*/ 51780, // Rule ID 1704 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aese, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1647:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1704, GIR_Done, // Label 1111: @51780 GIM_Try, /*On fail goto*//*Label 1112*/ 51832, // Rule ID 1707 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1656:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1707, GIR_Done, // Label 1112: @51832 GIM_Try, /*On fail goto*//*Label 1113*/ 51884, // Rule ID 1708 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1659:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1708, GIR_Done, // Label 1113: @51884 GIM_Try, /*On fail goto*//*Label 1114*/ 51943, // Rule ID 1717 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqrshr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1567:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQRSHR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1717, GIR_Done, // Label 1114: @51943 GIM_Try, /*On fail goto*//*Label 1115*/ 52002, // Rule ID 1718 // GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqrshl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1574:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQRSHL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1718, GIR_Done, // Label 1115: @52002 GIM_Try, /*On fail goto*//*Label 1116*/ 52061, // Rule ID 1834 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1834, GIR_Done, // Label 1116: @52061 GIM_Try, /*On fail goto*//*Label 1117*/ 52120, // Rule ID 1835 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1835, GIR_Done, // Label 1117: @52120 GIM_Try, /*On fail goto*//*Label 1118*/ 52179, // Rule ID 1836 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1546:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1836, GIR_Done, // Label 1118: @52179 GIM_Try, /*On fail goto*//*Label 1119*/ 52238, // Rule ID 1837 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1837, GIR_Done, // Label 1119: @52238 GIM_Try, /*On fail goto*//*Label 1120*/ 52297, // Rule ID 1838 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1838, GIR_Done, // Label 1120: @52297 GIM_Try, /*On fail goto*//*Label 1121*/ 52356, // Rule ID 1839 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1547:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1839, GIR_Done, // Label 1121: @52356 GIM_Try, /*On fail goto*//*Label 1122*/ 52415, // Rule ID 1840 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1840, GIR_Done, // Label 1122: @52415 GIM_Try, /*On fail goto*//*Label 1123*/ 52474, // Rule ID 1841 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1841, GIR_Done, // Label 1123: @52474 GIM_Try, /*On fail goto*//*Label 1124*/ 52533, // Rule ID 1842 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_s, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1549:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1842, GIR_Done, // Label 1124: @52533 GIM_Try, /*On fail goto*//*Label 1125*/ 52592, // Rule ID 1843 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1843, GIR_Done, // Label 1125: @52592 GIM_Try, /*On fail goto*//*Label 1126*/ 52651, // Rule ID 1844 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1844, GIR_Done, // Label 1126: @52651 GIM_Try, /*On fail goto*//*Label 1127*/ 52710, // Rule ID 1845 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv_u, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1550:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1845, GIR_Done, // Label 1127: @52710 GIM_Try, /*On fail goto*//*Label 1128*/ 52772, // Rule ID 1866 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1835:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1866, GIR_Done, // Label 1128: @52772 GIM_Try, /*On fail goto*//*Label 1129*/ 52834, // Rule ID 1873 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1860:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1873, GIR_Done, // Label 1129: @52834 GIM_Try, /*On fail goto*//*Label 1130*/ 52893, // Rule ID 1912 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1811:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1912, GIR_Done, // Label 1130: @52893 GIM_Try, /*On fail goto*//*Label 1131*/ 52952, // Rule ID 1913 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1812:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1913, GIR_Done, // Label 1131: @52952 GIM_Try, /*On fail goto*//*Label 1132*/ 53011, // Rule ID 1914 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1819:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1914, GIR_Done, // Label 1132: @53011 GIM_Try, /*On fail goto*//*Label 1133*/ 53070, // Rule ID 1915 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1820:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1915, GIR_Done, // Label 1133: @53070 GIM_Try, /*On fail goto*//*Label 1134*/ 53129, // Rule ID 1974 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1813:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1974, GIR_Done, // Label 1134: @53129 GIM_Try, /*On fail goto*//*Label 1135*/ 53188, // Rule ID 1975 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1814:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1975, GIR_Done, // Label 1135: @53188 GIM_Try, /*On fail goto*//*Label 1136*/ 53247, // Rule ID 1976 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1815:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1976, GIR_Done, // Label 1136: @53247 GIM_Try, /*On fail goto*//*Label 1137*/ 53306, // Rule ID 1977 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1816:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1977, GIR_Done, // Label 1137: @53306 GIM_Try, /*On fail goto*//*Label 1138*/ 53365, // Rule ID 1978 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1817:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1978, GIR_Done, // Label 1138: @53365 GIM_Try, /*On fail goto*//*Label 1139*/ 53424, // Rule ID 1979 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1818:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1979, GIR_Done, // Label 1139: @53424 GIM_Try, /*On fail goto*//*Label 1140*/ 53486, // Rule ID 2082 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2082, GIR_Done, // Label 1140: @53486 GIM_Try, /*On fail goto*//*Label 1141*/ 53545, // Rule ID 2115 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2115, GIR_Done, // Label 1141: @53545 GIM_Try, /*On fail goto*//*Label 1142*/ 53604, // Rule ID 2116 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2116, GIR_Done, // Label 1142: @53604 GIM_Try, /*On fail goto*//*Label 1143*/ 53663, // Rule ID 2144 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1813:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2144, GIR_Done, // Label 1143: @53663 GIM_Try, /*On fail goto*//*Label 1144*/ 53722, // Rule ID 2145 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1814:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2145, GIR_Done, // Label 1144: @53722 GIM_Try, /*On fail goto*//*Label 1145*/ 53781, // Rule ID 2146 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1815:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2146, GIR_Done, // Label 1145: @53781 GIM_Try, /*On fail goto*//*Label 1146*/ 53840, // Rule ID 2147 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1816:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2147, GIR_Done, // Label 1146: @53840 GIM_Try, /*On fail goto*//*Label 1147*/ 53899, // Rule ID 2148 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1817:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2148, GIR_Done, // Label 1147: @53899 GIM_Try, /*On fail goto*//*Label 1148*/ 53958, // Rule ID 2149 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1818:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2149, GIR_Done, // Label 1148: @53958 GIM_Try, /*On fail goto*//*Label 1149*/ 54013, // Rule ID 2424 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1669:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2424, GIR_Done, // Label 1149: @54013 GIM_Try, /*On fail goto*//*Label 1150*/ 54068, // Rule ID 2425 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f16] } 1668:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2425, GIR_Done, // Label 1150: @54068 GIM_Try, /*On fail goto*//*Label 1151*/ 54123, // Rule ID 2426 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1669:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2426, GIR_Done, // Label 1151: @54123 GIM_Try, /*On fail goto*//*Label 1152*/ 54178, // Rule ID 2427 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8f16] } 1668:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2427, GIR_Done, // Label 1152: @54178 GIM_Try, /*On fail goto*//*Label 1153*/ 54233, // Rule ID 2428 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1669:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2428, GIR_Done, // Label 1153: @54233 GIM_Try, /*On fail goto*//*Label 1154*/ 54288, // Rule ID 2429 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1668:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2429, GIR_Done, // Label 1154: @54288 GIM_Try, /*On fail goto*//*Label 1155*/ 54343, // Rule ID 2430 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1669:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2430, GIR_Done, // Label 1155: @54343 GIM_Try, /*On fail goto*//*Label 1156*/ 54398, // Rule ID 2431 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1668:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2431, GIR_Done, // Label 1156: @54398 GIM_Try, /*On fail goto*//*Label 1157*/ 54471, // Rule ID 3004 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1614:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3004, GIR_Done, // Label 1157: @54471 GIM_Try, /*On fail goto*//*Label 1158*/ 54544, // Rule ID 3006 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1614:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3006, GIR_Done, // Label 1158: @54544 GIM_Try, /*On fail goto*//*Label 1159*/ 54617, // Rule ID 3008 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1614:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3008, GIR_Done, // Label 1159: @54617 GIM_Try, /*On fail goto*//*Label 1160*/ 54690, // Rule ID 3010 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1615:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3010, GIR_Done, // Label 1160: @54690 GIM_Try, /*On fail goto*//*Label 1161*/ 54763, // Rule ID 3012 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1615:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3012, GIR_Done, // Label 1161: @54763 GIM_Try, /*On fail goto*//*Label 1162*/ 54836, // Rule ID 3014 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1615:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3014, GIR_Done, // Label 1162: @54836 GIM_Reject, // Label 822: @54837 GIM_Try, /*On fail goto*//*Label 1163*/ 63188, GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_Try, /*On fail goto*//*Label 1164*/ 54928, // Rule ID 3314 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1616:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3314, GIR_Done, // Label 1164: @54928 GIM_Try, /*On fail goto*//*Label 1165*/ 55014, // Rule ID 3316 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1616:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3316, GIR_Done, // Label 1165: @55014 GIM_Try, /*On fail goto*//*Label 1166*/ 55100, // Rule ID 3318 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1616:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3318, GIR_Done, // Label 1166: @55100 GIM_Try, /*On fail goto*//*Label 1167*/ 55186, // Rule ID 3320 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1616:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3320, GIR_Done, // Label 1167: @55186 GIM_Try, /*On fail goto*//*Label 1168*/ 55272, // Rule ID 3322 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1616:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3322, GIR_Done, // Label 1168: @55272 GIM_Try, /*On fail goto*//*Label 1169*/ 55358, // Rule ID 3324 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1616:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3324, GIR_Done, // Label 1169: @55358 GIM_Try, /*On fail goto*//*Label 1170*/ 55444, // Rule ID 3332 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1624:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3332, GIR_Done, // Label 1170: @55444 GIM_Try, /*On fail goto*//*Label 1171*/ 55530, // Rule ID 3334 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1624:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3334, GIR_Done, // Label 1171: @55530 GIM_Try, /*On fail goto*//*Label 1172*/ 55616, // Rule ID 3336 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1624:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3336, GIR_Done, // Label 1172: @55616 GIM_Try, /*On fail goto*//*Label 1173*/ 55702, // Rule ID 3338 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1624:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3338, GIR_Done, // Label 1173: @55702 GIM_Try, /*On fail goto*//*Label 1174*/ 55788, // Rule ID 3340 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1624:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3340, GIR_Done, // Label 1174: @55788 GIM_Try, /*On fail goto*//*Label 1175*/ 55874, // Rule ID 3342 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1624:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<>:$imm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3342, GIR_Done, // Label 1175: @55874 GIM_Try, /*On fail goto*//*Label 1176*/ 55955, // Rule ID 3052 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1582:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3052, GIR_Done, // Label 1176: @55955 GIM_Try, /*On fail goto*//*Label 1177*/ 56036, // Rule ID 3054 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3054, GIR_Done, // Label 1177: @56036 GIM_Try, /*On fail goto*//*Label 1178*/ 56117, // Rule ID 3056 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3056, GIR_Done, // Label 1178: @56117 GIM_Try, /*On fail goto*//*Label 1179*/ 56198, // Rule ID 3058 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1582:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3058, GIR_Done, // Label 1179: @56198 GIM_Try, /*On fail goto*//*Label 1180*/ 56279, // Rule ID 3060 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3060, GIR_Done, // Label 1180: @56279 GIM_Try, /*On fail goto*//*Label 1181*/ 56360, // Rule ID 3062 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3062, GIR_Done, // Label 1181: @56360 GIM_Try, /*On fail goto*//*Label 1182*/ 56441, // Rule ID 3064 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1620:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3064, GIR_Done, // Label 1182: @56441 GIM_Try, /*On fail goto*//*Label 1183*/ 56522, // Rule ID 3066 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1620:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3066, GIR_Done, // Label 1183: @56522 GIM_Try, /*On fail goto*//*Label 1184*/ 56603, // Rule ID 3068 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1620:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3068, GIR_Done, // Label 1184: @56603 GIM_Try, /*On fail goto*//*Label 1185*/ 56684, // Rule ID 3070 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1620:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3070, GIR_Done, // Label 1185: @56684 GIM_Try, /*On fail goto*//*Label 1186*/ 56765, // Rule ID 3072 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1620:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3072, GIR_Done, // Label 1186: @56765 GIM_Try, /*On fail goto*//*Label 1187*/ 56846, // Rule ID 3074 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1620:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3074, GIR_Done, // Label 1187: @56846 GIM_Try, /*On fail goto*//*Label 1188*/ 56927, // Rule ID 3076 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1597:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3076, GIR_Done, // Label 1188: @56927 GIM_Try, /*On fail goto*//*Label 1189*/ 57008, // Rule ID 3078 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1597:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3078, GIR_Done, // Label 1189: @57008 GIM_Try, /*On fail goto*//*Label 1190*/ 57089, // Rule ID 3080 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1597:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3080, GIR_Done, // Label 1190: @57089 GIM_Try, /*On fail goto*//*Label 1191*/ 57170, // Rule ID 3082 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1597:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3082, GIR_Done, // Label 1191: @57170 GIM_Try, /*On fail goto*//*Label 1192*/ 57251, // Rule ID 3084 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1597:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3084, GIR_Done, // Label 1192: @57251 GIM_Try, /*On fail goto*//*Label 1193*/ 57332, // Rule ID 3086 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1597:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3086, GIR_Done, // Label 1193: @57332 GIM_Try, /*On fail goto*//*Label 1194*/ 57413, // Rule ID 3088 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1598:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3088, GIR_Done, // Label 1194: @57413 GIM_Try, /*On fail goto*//*Label 1195*/ 57494, // Rule ID 3090 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1598:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3090, GIR_Done, // Label 1195: @57494 GIM_Try, /*On fail goto*//*Label 1196*/ 57575, // Rule ID 3092 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1598:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3092, GIR_Done, // Label 1196: @57575 GIM_Try, /*On fail goto*//*Label 1197*/ 57656, // Rule ID 3094 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1598:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3094, GIR_Done, // Label 1197: @57656 GIM_Try, /*On fail goto*//*Label 1198*/ 57737, // Rule ID 3096 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1598:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3096, GIR_Done, // Label 1198: @57737 GIM_Try, /*On fail goto*//*Label 1199*/ 57818, // Rule ID 3098 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1598:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3098, GIR_Done, // Label 1199: @57818 GIM_Try, /*On fail goto*//*Label 1200*/ 57899, // Rule ID 3396 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4f32] } 1582:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3396, GIR_Done, // Label 1200: @57899 GIM_Try, /*On fail goto*//*Label 1201*/ 57980, // Rule ID 3398 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8f16] } 1582:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3398, GIR_Done, // Label 1201: @57980 GIM_Try, /*On fail goto*//*Label 1202*/ 58061, // Rule ID 3563 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1613:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3563, GIR_Done, // Label 1202: @58061 GIM_Try, /*On fail goto*//*Label 1203*/ 58142, // Rule ID 3565 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1613:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3565, GIR_Done, // Label 1203: @58142 GIM_Try, /*On fail goto*//*Label 1204*/ 58223, // Rule ID 3567 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1613:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3567, GIR_Done, // Label 1204: @58223 GIM_Try, /*On fail goto*//*Label 1205*/ 58304, // Rule ID 3569 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1613:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3569, GIR_Done, // Label 1205: @58304 GIM_Try, /*On fail goto*//*Label 1206*/ 58385, // Rule ID 3571 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1611:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3571, GIR_Done, // Label 1206: @58385 GIM_Try, /*On fail goto*//*Label 1207*/ 58466, // Rule ID 3573 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1611:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3573, GIR_Done, // Label 1207: @58466 GIM_Try, /*On fail goto*//*Label 1208*/ 58547, // Rule ID 3575 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1611:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3575, GIR_Done, // Label 1208: @58547 GIM_Try, /*On fail goto*//*Label 1209*/ 58628, // Rule ID 3577 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1611:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3577, GIR_Done, // Label 1209: @58628 GIM_Try, /*On fail goto*//*Label 1210*/ 58709, // Rule ID 3579 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1611:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3579, GIR_Done, // Label 1210: @58709 GIM_Try, /*On fail goto*//*Label 1211*/ 58790, // Rule ID 3581 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1611:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3581, GIR_Done, // Label 1211: @58790 GIM_Try, /*On fail goto*//*Label 1212*/ 58871, // Rule ID 3583 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1623:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3583, GIR_Done, // Label 1212: @58871 GIM_Try, /*On fail goto*//*Label 1213*/ 58952, // Rule ID 3585 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1623:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3585, GIR_Done, // Label 1213: @58952 GIM_Try, /*On fail goto*//*Label 1214*/ 59033, // Rule ID 3587 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1623:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3587, GIR_Done, // Label 1214: @59033 GIM_Try, /*On fail goto*//*Label 1215*/ 59114, // Rule ID 3589 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1623:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3589, GIR_Done, // Label 1215: @59114 GIM_Try, /*On fail goto*//*Label 1216*/ 59195, // Rule ID 3591 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1623:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3591, GIR_Done, // Label 1216: @59195 GIM_Try, /*On fail goto*//*Label 1217*/ 59276, // Rule ID 3593 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1623:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3593, GIR_Done, // Label 1217: @59276 GIM_Try, /*On fail goto*//*Label 1218*/ 59343, // Rule ID 3599 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, // (intrinsic_wo_chain:{ *:[v8f16] } 1595:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3599, GIR_Done, // Label 1218: @59343 GIM_Try, /*On fail goto*//*Label 1219*/ 59410, // Rule ID 3601 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, // (intrinsic_wo_chain:{ *:[v8f16] } 1595:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3601, GIR_Done, // Label 1219: @59410 GIM_Try, /*On fail goto*//*Label 1220*/ 59486, // Rule ID 3302 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1634:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3302, GIR_Done, // Label 1220: @59486 GIM_Try, /*On fail goto*//*Label 1221*/ 59562, // Rule ID 3304 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1634:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3304, GIR_Done, // Label 1221: @59562 GIM_Try, /*On fail goto*//*Label 1222*/ 59638, // Rule ID 3306 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1634:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3306, GIR_Done, // Label 1222: @59638 GIM_Try, /*On fail goto*//*Label 1223*/ 59714, // Rule ID 3308 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1636:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3308, GIR_Done, // Label 1223: @59714 GIM_Try, /*On fail goto*//*Label 1224*/ 59790, // Rule ID 3310 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1636:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3310, GIR_Done, // Label 1224: @59790 GIM_Try, /*On fail goto*//*Label 1225*/ 59866, // Rule ID 3312 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1636:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3312, GIR_Done, // Label 1225: @59866 GIM_Try, /*On fail goto*//*Label 1226*/ 59955, // Rule ID 3535 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 1589:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3535, GIR_Done, // Label 1226: @59955 GIM_Try, /*On fail goto*//*Label 1227*/ 60044, // Rule ID 3537 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 1589:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3537, GIR_Done, // Label 1227: @60044 GIM_Try, /*On fail goto*//*Label 1228*/ 60115, // Rule ID 148 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1854:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 148, GIR_Done, // Label 1228: @60115 GIM_Try, /*On fail goto*//*Label 1229*/ 60186, // Rule ID 475 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1854:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 475, GIR_Done, // Label 1229: @60186 GIM_Try, /*On fail goto*//*Label 1230*/ 60257, // Rule ID 534 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 534, GIR_Done, // Label 1230: @60257 GIM_Try, /*On fail goto*//*Label 1231*/ 60328, // Rule ID 535 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1800:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 535, GIR_Done, // Label 1231: @60328 GIM_Try, /*On fail goto*//*Label 1232*/ 60399, // Rule ID 536 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1807:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 536, GIR_Done, // Label 1232: @60399 GIM_Try, /*On fail goto*//*Label 1233*/ 60470, // Rule ID 537 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 537, GIR_Done, // Label 1233: @60470 GIM_Try, /*On fail goto*//*Label 1234*/ 60534, // Rule ID 954 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1661:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 954, GIR_Done, // Label 1234: @60534 GIM_Try, /*On fail goto*//*Label 1235*/ 60598, // Rule ID 955 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1650:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 955, GIR_Done, // Label 1235: @60598 GIM_Try, /*On fail goto*//*Label 1236*/ 60662, // Rule ID 956 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1661:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 956, GIR_Done, // Label 1236: @60662 GIM_Try, /*On fail goto*//*Label 1237*/ 60726, // Rule ID 957 // GIM_CheckFeatures, GIFBS_HasDotProd, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1650:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 957, GIR_Done, // Label 1237: @60726 GIM_Try, /*On fail goto*//*Label 1238*/ 60797, // Rule ID 1678 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1774:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1678, GIR_Done, // Label 1238: @60797 GIM_Try, /*On fail goto*//*Label 1239*/ 60861, // Rule ID 1709 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1655:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1709, GIR_Done, // Label 1239: @60861 GIM_Try, /*On fail goto*//*Label 1240*/ 60925, // Rule ID 1710 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1657:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1710, GIR_Done, // Label 1240: @60925 GIM_Try, /*On fail goto*//*Label 1241*/ 60989, // Rule ID 1711 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1658:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1711, GIR_Done, // Label 1241: @60989 GIM_Try, /*On fail goto*//*Label 1242*/ 61053, // Rule ID 1712 // GIM_CheckFeatures, GIFBS_HasCrypto_HasV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1660:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1712, GIR_Done, // Label 1242: @61053 GIM_Try, /*On fail goto*//*Label 1243*/ 61124, // Rule ID 1904 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1799:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1904, GIR_Done, // Label 1243: @61124 GIM_Try, /*On fail goto*//*Label 1244*/ 61195, // Rule ID 1905 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1800:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1905, GIR_Done, // Label 1244: @61195 GIM_Try, /*On fail goto*//*Label 1245*/ 61266, // Rule ID 1906 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1807:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1906, GIR_Done, // Label 1245: @61266 GIM_Try, /*On fail goto*//*Label 1246*/ 61337, // Rule ID 1907 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1808:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1907, GIR_Done, // Label 1246: @61337 GIM_Try, /*On fail goto*//*Label 1247*/ 61408, // Rule ID 1980 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1797:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1980, GIR_Done, // Label 1247: @61408 GIM_Try, /*On fail goto*//*Label 1248*/ 61479, // Rule ID 1981 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1798:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1981, GIR_Done, // Label 1248: @61479 GIM_Try, /*On fail goto*//*Label 1249*/ 61550, // Rule ID 1982 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1803:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1982, GIR_Done, // Label 1249: @61550 GIM_Try, /*On fail goto*//*Label 1250*/ 61621, // Rule ID 1983 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1804:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1983, GIR_Done, // Label 1250: @61621 GIM_Try, /*On fail goto*//*Label 1251*/ 61692, // Rule ID 1984 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1805:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1984, GIR_Done, // Label 1251: @61692 GIM_Try, /*On fail goto*//*Label 1252*/ 61763, // Rule ID 1985 // GIM_CheckFeatures, GIFBS_HasV5TE_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1985, GIR_Done, // Label 1252: @61763 GIM_Try, /*On fail goto*//*Label 1253*/ 61834, // Rule ID 2154 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1797:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2154, GIR_Done, // Label 1253: @61834 GIM_Try, /*On fail goto*//*Label 1254*/ 61905, // Rule ID 2155 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1798:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2155, GIR_Done, // Label 1254: @61905 GIM_Try, /*On fail goto*//*Label 1255*/ 61976, // Rule ID 2156 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1803:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2156, GIR_Done, // Label 1255: @61976 GIM_Try, /*On fail goto*//*Label 1256*/ 62047, // Rule ID 2157 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1804:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2157, GIR_Done, // Label 1256: @62047 GIM_Try, /*On fail goto*//*Label 1257*/ 62118, // Rule ID 2158 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1805:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2158, GIR_Done, // Label 1257: @62118 GIM_Try, /*On fail goto*//*Label 1258*/ 62189, // Rule ID 2159 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2159, GIR_Done, // Label 1258: @62189 GIM_Try, /*On fail goto*//*Label 1259*/ 62260, // Rule ID 2437 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1667:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VBSLd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2437, GIR_Done, // Label 1259: @62260 GIM_Try, /*On fail goto*//*Label 1260*/ 62331, // Rule ID 2438 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i16] } 1667:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VBSLd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2438, GIR_Done, // Label 1260: @62331 GIM_Try, /*On fail goto*//*Label 1261*/ 62402, // Rule ID 2439 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i32] } 1667:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2439, GIR_Done, // Label 1261: @62402 GIM_Try, /*On fail goto*//*Label 1262*/ 62473, // Rule ID 2440 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v2f32] } 1667:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VBSLd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2440, GIR_Done, // Label 1262: @62473 GIM_Try, /*On fail goto*//*Label 1263*/ 62544, // Rule ID 2441 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v1i64] } 1667:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2441, GIR_Done, // Label 1263: @62544 GIM_Try, /*On fail goto*//*Label 1264*/ 62615, // Rule ID 2444 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v16i8] } 1667:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VBSLq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2444, GIR_Done, // Label 1264: @62615 GIM_Try, /*On fail goto*//*Label 1265*/ 62686, // Rule ID 2445 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i16] } 1667:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VBSLq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2445, GIR_Done, // Label 1265: @62686 GIM_Try, /*On fail goto*//*Label 1266*/ 62757, // Rule ID 2446 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1667:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2446, GIR_Done, // Label 1266: @62757 GIM_Try, /*On fail goto*//*Label 1267*/ 62828, // Rule ID 2447 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4f32] } 1667:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VBSLq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2447, GIR_Done, // Label 1267: @62828 GIM_Try, /*On fail goto*//*Label 1268*/ 62899, // Rule ID 2448 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v2i64] } 1667:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2448, GIR_Done, // Label 1268: @62899 GIM_Try, /*On fail goto*//*Label 1269*/ 62995, // Rule ID 2561 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1c, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1651:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/17, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1C, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2561, GIR_Done, // Label 1269: @62995 GIM_Try, /*On fail goto*//*Label 1270*/ 63091, // Rule ID 2562 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1m, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1653:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/17, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1M, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2562, GIR_Done, // Label 1270: @63091 GIM_Try, /*On fail goto*//*Label 1271*/ 63187, // Rule ID 2563 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1p, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, // (intrinsic_wo_chain:{ *:[v4i32] } 1654:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/0, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*Imm*/17, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC DPair_with_ssub_0*/53, GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC SPR*/2, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1P, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2563, GIR_Done, // Label 1271: @63187 GIM_Reject, // Label 1163: @63188 GIM_Try, /*On fail goto*//*Label 1272*/ 66550, GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, GIM_Try, /*On fail goto*//*Label 1273*/ 63276, // Rule ID 3137 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3137, GIR_Done, // Label 1273: @63276 GIM_Try, /*On fail goto*//*Label 1274*/ 63359, // Rule ID 3141 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3141, GIR_Done, // Label 1274: @63359 GIM_Try, /*On fail goto*//*Label 1275*/ 63442, // Rule ID 3145 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3145, GIR_Done, // Label 1275: @63442 GIM_Try, /*On fail goto*//*Label 1276*/ 63525, // Rule ID 3149 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3149, GIR_Done, // Label 1276: @63525 GIM_Try, /*On fail goto*//*Label 1277*/ 63608, // Rule ID 3153 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3153, GIR_Done, // Label 1277: @63608 GIM_Try, /*On fail goto*//*Label 1278*/ 63691, // Rule ID 3157 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1630:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3157, GIR_Done, // Label 1278: @63691 GIM_Try, /*On fail goto*//*Label 1279*/ 63774, // Rule ID 3161 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3161, GIR_Done, // Label 1279: @63774 GIM_Try, /*On fail goto*//*Label 1280*/ 63857, // Rule ID 3165 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1630:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3165, GIR_Done, // Label 1280: @63857 GIM_Try, /*On fail goto*//*Label 1281*/ 63946, // Rule ID 3539 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3539, GIR_Done, // Label 1281: @63946 GIM_Try, /*On fail goto*//*Label 1282*/ 64035, // Rule ID 3541 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3541, GIR_Done, // Label 1282: @64035 GIM_Try, /*On fail goto*//*Label 1283*/ 64124, // Rule ID 3543 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3543, GIR_Done, // Label 1283: @64124 GIM_Try, /*On fail goto*//*Label 1284*/ 64213, // Rule ID 3545 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3545, GIR_Done, // Label 1284: @64213 GIM_Try, /*On fail goto*//*Label 1285*/ 64302, // Rule ID 3547 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3547, GIR_Done, // Label 1285: @64302 GIM_Try, /*On fail goto*//*Label 1286*/ 64391, // Rule ID 3549 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3549, GIR_Done, // Label 1286: @64391 GIM_Try, /*On fail goto*//*Label 1287*/ 64480, // Rule ID 3551 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3551, GIR_Done, // Label 1287: @64480 GIM_Try, /*On fail goto*//*Label 1288*/ 64569, // Rule ID 3553 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1612:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3553, GIR_Done, // Label 1288: @64569 GIM_Try, /*On fail goto*//*Label 1289*/ 64658, // Rule ID 3555 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3555, GIR_Done, // Label 1289: @64658 GIM_Try, /*On fail goto*//*Label 1290*/ 64747, // Rule ID 3557 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1612:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3557, GIR_Done, // Label 1290: @64747 GIM_Try, /*On fail goto*//*Label 1291*/ 64836, // Rule ID 3559 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3559, GIR_Done, // Label 1291: @64836 GIM_Try, /*On fail goto*//*Label 1292*/ 64925, // Rule ID 3561 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_wo_chain:{ *:[v2i64] } 1612:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3561, GIR_Done, // Label 1292: @64925 GIM_Try, /*On fail goto*//*Label 1293*/ 65022, // Rule ID 3392 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3392, GIR_Done, // Label 1293: @65022 GIM_Try, /*On fail goto*//*Label 1294*/ 65119, // Rule ID 3394 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3394, GIR_Done, // Label 1294: @65119 GIM_Try, /*On fail goto*//*Label 1295*/ 65216, // Rule ID 3603 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3603, GIR_Done, // Label 1295: @65216 GIM_Try, /*On fail goto*//*Label 1296*/ 65313, // Rule ID 3605 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3605, GIR_Done, // Label 1296: @65313 GIM_Try, /*On fail goto*//*Label 1297*/ 65410, // Rule ID 3607 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1585:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3607, GIR_Done, // Label 1297: @65410 GIM_Try, /*On fail goto*//*Label 1298*/ 65507, // Rule ID 3609 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3609, GIR_Done, // Label 1298: @65507 GIM_Try, /*On fail goto*//*Label 1299*/ 65604, // Rule ID 3611 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3611, GIR_Done, // Label 1299: @65604 GIM_Try, /*On fail goto*//*Label 1300*/ 65701, // Rule ID 3613 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4i32] } 1585:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3613, GIR_Done, // Label 1300: @65701 GIM_Try, /*On fail goto*//*Label 1301*/ 65780, // Rule ID 2799 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2799, GIR_Done, // Label 1301: @65780 GIM_Try, /*On fail goto*//*Label 1302*/ 65859, // Rule ID 2801 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2801, GIR_Done, // Label 1302: @65859 GIM_Try, /*On fail goto*//*Label 1303*/ 65938, // Rule ID 2803 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2803, GIR_Done, // Label 1303: @65938 GIM_Try, /*On fail goto*//*Label 1304*/ 66017, // Rule ID 2805 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2805, GIR_Done, // Label 1304: @66017 GIM_Try, /*On fail goto*//*Label 1305*/ 66096, // Rule ID 2807 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2807, GIR_Done, // Label 1305: @66096 GIM_Try, /*On fail goto*//*Label 1306*/ 66175, // Rule ID 2809 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1580:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2809, GIR_Done, // Label 1306: @66175 GIM_Try, /*On fail goto*//*Label 1307*/ 66262, // Rule ID 3376 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8f16] } 1587:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3376, GIR_Done, // Label 1307: @66262 GIM_Try, /*On fail goto*//*Label 1308*/ 66349, // Rule ID 3378 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v4f32] } 1587:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3378, GIR_Done, // Label 1308: @66349 GIM_Try, /*On fail goto*//*Label 1309*/ 66438, // Rule ID 2555 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1775:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2555, GIR_Done, // Label 1309: @66438 GIM_Try, /*On fail goto*//*Label 1310*/ 66549, // Rule ID 2556 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl3, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1772:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL3Pseudo, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2556, GIR_Done, // Label 1310: @66549 GIM_Reject, // Label 1272: @66550 GIM_Try, /*On fail goto*//*Label 1311*/ 71002, GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, GIM_Try, /*On fail goto*//*Label 1312*/ 66650, // Rule ID 3248 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3248, GIR_Done, // Label 1312: @66650 GIM_Try, /*On fail goto*//*Label 1313*/ 66745, // Rule ID 3250 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3250, GIR_Done, // Label 1313: @66745 GIM_Try, /*On fail goto*//*Label 1314*/ 66840, // Rule ID 3252 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3252, GIR_Done, // Label 1314: @66840 GIM_Try, /*On fail goto*//*Label 1315*/ 66935, // Rule ID 3254 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3254, GIR_Done, // Label 1315: @66935 GIM_Try, /*On fail goto*//*Label 1316*/ 67030, // Rule ID 3256 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3256, GIR_Done, // Label 1316: @67030 GIM_Try, /*On fail goto*//*Label 1317*/ 67125, // Rule ID 3258 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3258, GIR_Done, // Label 1317: @67125 GIM_Try, /*On fail goto*//*Label 1318*/ 67220, // Rule ID 3260 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3260, GIR_Done, // Label 1318: @67220 GIM_Try, /*On fail goto*//*Label 1319*/ 67315, // Rule ID 3262 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3262, GIR_Done, // Label 1319: @67315 GIM_Try, /*On fail goto*//*Label 1320*/ 67410, // Rule ID 3264 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3264, GIR_Done, // Label 1320: @67410 GIM_Try, /*On fail goto*//*Label 1321*/ 67505, // Rule ID 3266 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3266, GIR_Done, // Label 1321: @67505 GIM_Try, /*On fail goto*//*Label 1322*/ 67600, // Rule ID 3268 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3268, GIR_Done, // Label 1322: @67600 GIM_Try, /*On fail goto*//*Label 1323*/ 67695, // Rule ID 3270 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3270, GIR_Done, // Label 1323: @67695 GIM_Try, /*On fail goto*//*Label 1324*/ 67790, // Rule ID 3272 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3272, GIR_Done, // Label 1324: @67790 GIM_Try, /*On fail goto*//*Label 1325*/ 67885, // Rule ID 3274 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3274, GIR_Done, // Label 1325: @67885 GIM_Try, /*On fail goto*//*Label 1326*/ 67980, // Rule ID 3276 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3276, GIR_Done, // Label 1326: @67980 GIM_Try, /*On fail goto*//*Label 1327*/ 68075, // Rule ID 3278 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3278, GIR_Done, // Label 1327: @68075 GIM_Try, /*On fail goto*//*Label 1328*/ 68170, // Rule ID 3280 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3280, GIR_Done, // Label 1328: @68170 GIM_Try, /*On fail goto*//*Label 1329*/ 68265, // Rule ID 3282 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3282, GIR_Done, // Label 1329: @68265 GIM_Try, /*On fail goto*//*Label 1330*/ 68360, // Rule ID 3284 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3284, GIR_Done, // Label 1330: @68360 GIM_Try, /*On fail goto*//*Label 1331*/ 68455, // Rule ID 3286 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3286, GIR_Done, // Label 1331: @68455 GIM_Try, /*On fail goto*//*Label 1332*/ 68550, // Rule ID 3288 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3288, GIR_Done, // Label 1332: @68550 GIM_Try, /*On fail goto*//*Label 1333*/ 68645, // Rule ID 3290 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1628:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3290, GIR_Done, // Label 1333: @68645 GIM_Try, /*On fail goto*//*Label 1334*/ 68740, // Rule ID 3292 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1628:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3292, GIR_Done, // Label 1334: @68740 GIM_Try, /*On fail goto*//*Label 1335*/ 68835, // Rule ID 3294 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1628:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3294, GIR_Done, // Label 1335: @68835 GIM_Try, /*On fail goto*//*Label 1336*/ 68916, // Rule ID 3621 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3621, GIR_Done, // Label 1336: @68916 GIM_Try, /*On fail goto*//*Label 1337*/ 68997, // Rule ID 3623 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3623, GIR_Done, // Label 1337: @68997 GIM_Try, /*On fail goto*//*Label 1338*/ 69078, // Rule ID 3625 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3625, GIR_Done, // Label 1338: @69078 GIM_Try, /*On fail goto*//*Label 1339*/ 69159, // Rule ID 3627 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3627, GIR_Done, // Label 1339: @69159 GIM_Try, /*On fail goto*//*Label 1340*/ 69240, // Rule ID 3629 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3629, GIR_Done, // Label 1340: @69240 GIM_Try, /*On fail goto*//*Label 1341*/ 69321, // Rule ID 3631 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3631, GIR_Done, // Label 1341: @69321 GIM_Try, /*On fail goto*//*Label 1342*/ 69402, // Rule ID 3633 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3633, GIR_Done, // Label 1342: @69402 GIM_Try, /*On fail goto*//*Label 1343*/ 69483, // Rule ID 3635 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3635, GIR_Done, // Label 1343: @69483 GIM_Try, /*On fail goto*//*Label 1344*/ 69564, // Rule ID 3637 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3637, GIR_Done, // Label 1344: @69564 GIM_Try, /*On fail goto*//*Label 1345*/ 69645, // Rule ID 3639 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3639, GIR_Done, // Label 1345: @69645 GIM_Try, /*On fail goto*//*Label 1346*/ 69726, // Rule ID 3641 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3641, GIR_Done, // Label 1346: @69726 GIM_Try, /*On fail goto*//*Label 1347*/ 69807, // Rule ID 3643 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3643, GIR_Done, // Label 1347: @69807 GIM_Try, /*On fail goto*//*Label 1348*/ 69888, // Rule ID 3645 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3645, GIR_Done, // Label 1348: @69888 GIM_Try, /*On fail goto*//*Label 1349*/ 69969, // Rule ID 3647 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3647, GIR_Done, // Label 1349: @69969 GIM_Try, /*On fail goto*//*Label 1350*/ 70050, // Rule ID 3649 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3649, GIR_Done, // Label 1350: @70050 GIM_Try, /*On fail goto*//*Label 1351*/ 70131, // Rule ID 3651 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3651, GIR_Done, // Label 1351: @70131 GIM_Try, /*On fail goto*//*Label 1352*/ 70212, // Rule ID 3653 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3653, GIR_Done, // Label 1352: @70212 GIM_Try, /*On fail goto*//*Label 1353*/ 70293, // Rule ID 3655 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3655, GIR_Done, // Label 1353: @70293 GIM_Try, /*On fail goto*//*Label 1354*/ 70374, // Rule ID 3657 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3657, GIR_Done, // Label 1354: @70374 GIM_Try, /*On fail goto*//*Label 1355*/ 70455, // Rule ID 3659 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3659, GIR_Done, // Label 1355: @70455 GIM_Try, /*On fail goto*//*Label 1356*/ 70536, // Rule ID 3661 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3661, GIR_Done, // Label 1356: @70536 GIM_Try, /*On fail goto*//*Label 1357*/ 70617, // Rule ID 3663 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v16i8] } 1626:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3663, GIR_Done, // Label 1357: @70617 GIM_Try, /*On fail goto*//*Label 1358*/ 70698, // Rule ID 3665 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v8i16] } 1626:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3665, GIR_Done, // Label 1358: @70698 GIM_Try, /*On fail goto*//*Label 1359*/ 70779, // Rule ID 3667 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_wo_chain:{ *:[v4i32] } 1626:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3667, GIR_Done, // Label 1359: @70779 GIM_Try, /*On fail goto*//*Label 1360*/ 70898, // Rule ID 2557 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx3, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1776:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, GIR_ConstrainSelectedInstOperands, /*InsnID*/2, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX3Pseudo, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2557, GIR_Done, // Label 1360: @70898 GIM_Try, /*On fail goto*//*Label 1361*/ 71001, // Rule ID 2558 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl4, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1773:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL4Pseudo, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2558, GIR_Done, // Label 1361: @71001 GIM_Reject, // Label 1311: @71002 GIM_Try, /*On fail goto*//*Label 1362*/ 73909, GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, GIM_Try, /*On fail goto*//*Label 1363*/ 71098, // Rule ID 2829 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2829, GIR_Done, // Label 1363: @71098 GIM_Try, /*On fail goto*//*Label 1364*/ 71189, // Rule ID 2833 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2833, GIR_Done, // Label 1364: @71189 GIM_Try, /*On fail goto*//*Label 1365*/ 71280, // Rule ID 2837 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2837, GIR_Done, // Label 1365: @71280 GIM_Try, /*On fail goto*//*Label 1366*/ 71371, // Rule ID 2841 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2841, GIR_Done, // Label 1366: @71371 GIM_Try, /*On fail goto*//*Label 1367*/ 71462, // Rule ID 2845 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2845, GIR_Done, // Label 1367: @71462 GIM_Try, /*On fail goto*//*Label 1368*/ 71553, // Rule ID 2849 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2849, GIR_Done, // Label 1368: @71553 GIM_Try, /*On fail goto*//*Label 1369*/ 71644, // Rule ID 2853 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2853, GIR_Done, // Label 1369: @71644 GIM_Try, /*On fail goto*//*Label 1370*/ 71735, // Rule ID 2857 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2857, GIR_Done, // Label 1370: @71735 GIM_Try, /*On fail goto*//*Label 1371*/ 71826, // Rule ID 2861 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2861, GIR_Done, // Label 1371: @71826 GIM_Try, /*On fail goto*//*Label 1372*/ 71917, // Rule ID 2865 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2865, GIR_Done, // Label 1372: @71917 GIM_Try, /*On fail goto*//*Label 1373*/ 72008, // Rule ID 2869 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2869, GIR_Done, // Label 1373: @72008 GIM_Try, /*On fail goto*//*Label 1374*/ 72099, // Rule ID 2873 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2873, GIR_Done, // Label 1374: @72099 GIM_Try, /*On fail goto*//*Label 1375*/ 72190, // Rule ID 2877 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2877, GIR_Done, // Label 1375: @72190 GIM_Try, /*On fail goto*//*Label 1376*/ 72281, // Rule ID 2881 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2881, GIR_Done, // Label 1376: @72281 GIM_Try, /*On fail goto*//*Label 1377*/ 72372, // Rule ID 2885 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2885, GIR_Done, // Label 1377: @72372 GIM_Try, /*On fail goto*//*Label 1378*/ 72467, // Rule ID 2831 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2831, GIR_Done, // Label 1378: @72467 GIM_Try, /*On fail goto*//*Label 1379*/ 72562, // Rule ID 2835 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2835, GIR_Done, // Label 1379: @72562 GIM_Try, /*On fail goto*//*Label 1380*/ 72657, // Rule ID 2839 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2839, GIR_Done, // Label 1380: @72657 GIM_Try, /*On fail goto*//*Label 1381*/ 72752, // Rule ID 2843 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2843, GIR_Done, // Label 1381: @72752 GIM_Try, /*On fail goto*//*Label 1382*/ 72847, // Rule ID 2847 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2847, GIR_Done, // Label 1382: @72847 GIM_Try, /*On fail goto*//*Label 1383*/ 72942, // Rule ID 2851 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2851, GIR_Done, // Label 1383: @72942 GIM_Try, /*On fail goto*//*Label 1384*/ 73037, // Rule ID 2855 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2855, GIR_Done, // Label 1384: @73037 GIM_Try, /*On fail goto*//*Label 1385*/ 73132, // Rule ID 2859 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2859, GIR_Done, // Label 1385: @73132 GIM_Try, /*On fail goto*//*Label 1386*/ 73227, // Rule ID 2863 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2863, GIR_Done, // Label 1386: @73227 GIM_Try, /*On fail goto*//*Label 1387*/ 73322, // Rule ID 2867 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2867, GIR_Done, // Label 1387: @73322 GIM_Try, /*On fail goto*//*Label 1388*/ 73417, // Rule ID 2871 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2871, GIR_Done, // Label 1388: @73417 GIM_Try, /*On fail goto*//*Label 1389*/ 73512, // Rule ID 2875 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2875, GIR_Done, // Label 1389: @73512 GIM_Try, /*On fail goto*//*Label 1390*/ 73607, // Rule ID 2879 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2879, GIR_Done, // Label 1390: @73607 GIM_Try, /*On fail goto*//*Label 1391*/ 73702, // Rule ID 2883 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2883, GIR_Done, // Label 1391: @73702 GIM_Try, /*On fail goto*//*Label 1392*/ 73797, // Rule ID 2887 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID, // (intrinsic_wo_chain:{ *:[i32] } 1607:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2887, GIR_Done, // Label 1392: @73797 GIM_Try, /*On fail goto*//*Label 1393*/ 73908, // Rule ID 2559 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx4, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // (intrinsic_wo_chain:{ *:[v8i8] } 1777:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX4Pseudo, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2559, GIR_Done, // Label 1393: @73908 GIM_Reject, // Label 1362: @73909 GIM_Try, /*On fail goto*//*Label 1394*/ 78399, GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshrn, GIM_Try, /*On fail goto*//*Label 1395*/ 74030, // Rule ID 3168 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3168, GIR_Done, // Label 1395: @74030 GIM_Try, /*On fail goto*//*Label 1396*/ 74142, // Rule ID 3170 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3170, GIR_Done, // Label 1396: @74142 GIM_Try, /*On fail goto*//*Label 1397*/ 74254, // Rule ID 3172 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3172, GIR_Done, // Label 1397: @74254 GIM_Try, /*On fail goto*//*Label 1398*/ 74366, // Rule ID 3174 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3174, GIR_Done, // Label 1398: @74366 GIM_Try, /*On fail goto*//*Label 1399*/ 74478, // Rule ID 3176 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3176, GIR_Done, // Label 1399: @74478 GIM_Try, /*On fail goto*//*Label 1400*/ 74590, // Rule ID 3178 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3178, GIR_Done, // Label 1400: @74590 GIM_Try, /*On fail goto*//*Label 1401*/ 74702, // Rule ID 3180 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3180, GIR_Done, // Label 1401: @74702 GIM_Try, /*On fail goto*//*Label 1402*/ 74814, // Rule ID 3182 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3182, GIR_Done, // Label 1402: @74814 GIM_Try, /*On fail goto*//*Label 1403*/ 74926, // Rule ID 3184 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3184, GIR_Done, // Label 1403: @74926 GIM_Try, /*On fail goto*//*Label 1404*/ 75038, // Rule ID 3186 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3186, GIR_Done, // Label 1404: @75038 GIM_Try, /*On fail goto*//*Label 1405*/ 75150, // Rule ID 3188 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3188, GIR_Done, // Label 1405: @75150 GIM_Try, /*On fail goto*//*Label 1406*/ 75262, // Rule ID 3190 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3190, GIR_Done, // Label 1406: @75262 GIM_Try, /*On fail goto*//*Label 1407*/ 75374, // Rule ID 3192 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3192, GIR_Done, // Label 1407: @75374 GIM_Try, /*On fail goto*//*Label 1408*/ 75486, // Rule ID 3194 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3194, GIR_Done, // Label 1408: @75486 GIM_Try, /*On fail goto*//*Label 1409*/ 75598, // Rule ID 3196 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3196, GIR_Done, // Label 1409: @75598 GIM_Try, /*On fail goto*//*Label 1410*/ 75710, // Rule ID 3198 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3198, GIR_Done, // Label 1410: @75710 GIM_Try, /*On fail goto*//*Label 1411*/ 75822, // Rule ID 3200 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3200, GIR_Done, // Label 1411: @75822 GIM_Try, /*On fail goto*//*Label 1412*/ 75934, // Rule ID 3202 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3202, GIR_Done, // Label 1412: @75934 GIM_Try, /*On fail goto*//*Label 1413*/ 76046, // Rule ID 3204 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3204, GIR_Done, // Label 1413: @76046 GIM_Try, /*On fail goto*//*Label 1414*/ 76158, // Rule ID 3206 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3206, GIR_Done, // Label 1414: @76158 GIM_Try, /*On fail goto*//*Label 1415*/ 76270, // Rule ID 3208 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3208, GIR_Done, // Label 1415: @76270 GIM_Try, /*On fail goto*//*Label 1416*/ 76382, // Rule ID 3210 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3210, GIR_Done, // Label 1416: @76382 GIM_Try, /*On fail goto*//*Label 1417*/ 76494, // Rule ID 3212 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3212, GIR_Done, // Label 1417: @76494 GIM_Try, /*On fail goto*//*Label 1418*/ 76606, // Rule ID 3214 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3214, GIR_Done, // Label 1418: @76606 GIM_Try, /*On fail goto*//*Label 1419*/ 76718, // Rule ID 3216 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3216, GIR_Done, // Label 1419: @76718 GIM_Try, /*On fail goto*//*Label 1420*/ 76830, // Rule ID 3218 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3218, GIR_Done, // Label 1420: @76830 GIM_Try, /*On fail goto*//*Label 1421*/ 76942, // Rule ID 3220 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3220, GIR_Done, // Label 1421: @76942 GIM_Try, /*On fail goto*//*Label 1422*/ 77054, // Rule ID 3222 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3222, GIR_Done, // Label 1422: @77054 GIM_Try, /*On fail goto*//*Label 1423*/ 77166, // Rule ID 3224 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3224, GIR_Done, // Label 1423: @77166 GIM_Try, /*On fail goto*//*Label 1424*/ 77278, // Rule ID 3226 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3226, GIR_Done, // Label 1424: @77278 GIM_Try, /*On fail goto*//*Label 1425*/ 77390, // Rule ID 3228 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3228, GIR_Done, // Label 1425: @77390 GIM_Try, /*On fail goto*//*Label 1426*/ 77502, // Rule ID 3230 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3230, GIR_Done, // Label 1426: @77502 GIM_Try, /*On fail goto*//*Label 1427*/ 77614, // Rule ID 3232 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3232, GIR_Done, // Label 1427: @77614 GIM_Try, /*On fail goto*//*Label 1428*/ 77726, // Rule ID 3234 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3234, GIR_Done, // Label 1428: @77726 GIM_Try, /*On fail goto*//*Label 1429*/ 77838, // Rule ID 3236 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3236, GIR_Done, // Label 1429: @77838 GIM_Try, /*On fail goto*//*Label 1430*/ 77950, // Rule ID 3238 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3238, GIR_Done, // Label 1430: @77950 GIM_Try, /*On fail goto*//*Label 1431*/ 78062, // Rule ID 3240 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3240, GIR_Done, // Label 1431: @78062 GIM_Try, /*On fail goto*//*Label 1432*/ 78174, // Rule ID 3242 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v16i8] } 1632:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3242, GIR_Done, // Label 1432: @78174 GIM_Try, /*On fail goto*//*Label 1433*/ 78286, // Rule ID 3244 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32bh, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3244, GIR_Done, // Label 1433: @78286 GIM_Try, /*On fail goto*//*Label 1434*/ 78398, // Rule ID 3246 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16, // MIs[1] Operand 1 // No operand predicates GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_wo_chain:{ *:[v8i16] } 1632:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32th, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3246, GIR_Done, // Label 1434: @78398 GIM_Reject, // Label 1394: @78399 GIM_Reject, // Label 13: @78400 GIM_Try, /*On fail goto*//*Label 1435*/ 78449, GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_clrex, GIM_Try, /*On fail goto*//*Label 1436*/ 78425, // Rule ID 254 // GIM_CheckFeatures, GIFBS_HasV6K_IsARM, // (intrinsic_void 1500:{ *:[iPTR] }) => (CLREX) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 254, GIR_Done, // Label 1436: @78425 GIM_Try, /*On fail goto*//*Label 1437*/ 78448, // Rule ID 589 // GIM_CheckFeatures, GIFBS_HasV7Clrex_IsThumb, // (intrinsic_void 1500:{ *:[iPTR] }) => (t2CLREX) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 589, GIR_Done, // Label 1437: @78448 GIM_Reject, // Label 1435: @78449 GIM_Try, /*On fail goto*//*Label 1438*/ 79209, GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, GIM_Try, /*On fail goto*//*Label 1439*/ 78482, // Rule ID 352 // GIM_CheckFeatures, GIFBS_IsThumb_IsWindows, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 249, // (intrinsic_void 1846:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 352, GIR_Done, // Label 1439: @78482 GIM_Try, /*On fail goto*//*Label 1440*/ 78529, // Rule ID 2 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (HINT (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2, GIR_Done, // Label 1440: @78529 GIM_Try, /*On fail goto*//*Label 1441*/ 78576, // Rule ID 10 // GIM_CheckFeatures, GIFBS_HasV7_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1513:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (DBG (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 10, GIR_Done, // Label 1441: @78576 GIM_Try, /*On fail goto*//*Label 1442*/ 78616, // Rule ID 11 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 11, GIR_Done, // Label 1442: @78616 GIM_Try, /*On fail goto*//*Label 1443*/ 78656, // Rule ID 237 // GIM_CheckFeatures, GIFBS_HasDB_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1514:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (DMB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 237, GIR_Done, // Label 1443: @78656 GIM_Try, /*On fail goto*//*Label 1444*/ 78696, // Rule ID 238 // GIM_CheckFeatures, GIFBS_HasDB_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1515:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (DSB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 238, GIR_Done, // Label 1444: @78696 GIM_Try, /*On fail goto*//*Label 1445*/ 78736, // Rule ID 239 // GIM_CheckFeatures, GIFBS_HasDB_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1519:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (ISB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 239, GIR_Done, // Label 1445: @78736 GIM_Try, /*On fail goto*//*Label 1446*/ 78783, // Rule ID 285 // GIM_CheckFeatures, GIFBS_HasV6M_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 285, GIR_Done, // Label 1446: @78783 GIM_Try, /*On fail goto*//*Label 1447*/ 78823, // Rule ID 351 // GIM_CheckFeatures, GIFBS_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_255, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 351, GIR_Done, // Label 1447: @78823 GIM_Try, /*On fail goto*//*Label 1448*/ 78863, // Rule ID 500 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1846:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 500, GIR_Done, // Label 1448: @78863 GIM_Try, /*On fail goto*//*Label 1449*/ 78910, // Rule ID 574 // GIM_CheckFeatures, GIFBS_HasDB_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1514:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 574, GIR_Done, // Label 1449: @78910 GIM_Try, /*On fail goto*//*Label 1450*/ 78957, // Rule ID 575 // GIM_CheckFeatures, GIFBS_HasDB_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1515:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 575, GIR_Done, // Label 1450: @78957 GIM_Try, /*On fail goto*//*Label 1451*/ 79004, // Rule ID 576 // GIM_CheckFeatures, GIFBS_HasDB_IsThumb, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1519:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 576, GIR_Done, // Label 1451: @79004 GIM_Try, /*On fail goto*//*Label 1452*/ 79051, // Rule ID 594 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1518:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 594, GIR_Done, // Label 1452: @79051 GIM_Try, /*On fail goto*//*Label 1453*/ 79098, // Rule ID 595 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1513:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG, GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 595, GIR_Done, // Label 1453: @79098 GIM_Try, /*On fail goto*//*Label 1454*/ 79137, // Rule ID 740 // GIM_CheckFeatures, GIFBS_HasFPRegs, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_get_fpscr, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1516:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 740, GIR_Done, // Label 1454: @79137 GIM_Try, /*On fail goto*//*Label 1455*/ 79169, // Rule ID 618 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::set_loop_iterations, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, // (intrinsic_void 231:{ *:[iPTR] }, rGPR:{ *:[i32] }:$elts) => (t2DoLoopStart rGPR:{ *:[i32] }:$elts) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DoLoopStart, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elts GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 618, GIR_Done, // Label 1455: @79169 GIM_Try, /*On fail goto*//*Label 1456*/ 79208, // Rule ID 741 // GIM_CheckFeatures, GIFBS_HasFPRegs, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_set_fpscr, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_void 1790:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR GPRnopc:{ *:[i32] }:$Rt) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 741, GIR_Done, // Label 1456: @79208 GIM_Reject, // Label 1438: @79209 GIM_Try, /*On fail goto*//*Label 1457*/ 81374, GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, GIM_Try, /*On fail goto*//*Label 1458*/ 79273, // Rule ID 3836 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v4i32] } 1601:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3836, GIR_Done, // Label 1458: @79273 GIM_Try, /*On fail goto*//*Label 1459*/ 79332, // Rule ID 3842 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v4f32] } 1601:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3842, GIR_Done, // Label 1459: @79332 GIM_Try, /*On fail goto*//*Label 1460*/ 79391, // Rule ID 3844 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v2i64] } 1601:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3844, GIR_Done, // Label 1460: @79391 GIM_Try, /*On fail goto*//*Label 1461*/ 79450, // Rule ID 3846 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v2f64] } 1601:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3846, GIR_Done, // Label 1461: @79450 GIM_Try, /*On fail goto*//*Label 1462*/ 79499, // Rule ID 1724 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_space, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, // MIs[0] size GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1821:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1724, GIR_Done, // Label 1462: @79499 GIM_Try, /*On fail goto*//*Label 1463*/ 79558, // Rule ID 3838 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3838, GIR_Done, // Label 1463: @79558 GIM_Try, /*On fail goto*//*Label 1464*/ 79617, // Rule ID 3848 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3848, GIR_Done, // Label 1464: @79617 GIM_Try, /*On fail goto*//*Label 1465*/ 79676, // Rule ID 3852 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3852, GIR_Done, // Label 1465: @79676 GIM_Try, /*On fail goto*//*Label 1466*/ 79735, // Rule ID 3856 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_void 1640:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3856, GIR_Done, // Label 1466: @79735 GIM_Try, /*On fail goto*//*Label 1467*/ 79798, // Rule ID 3 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1789:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3, GIR_Done, // Label 1467: @79798 GIM_Try, /*On fail goto*//*Label 1468*/ 79861, // Rule ID 123 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1788:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 123, GIR_Done, // Label 1468: @79861 GIM_Try, /*On fail goto*//*Label 1469*/ 79924, // Rule ID 124 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1786:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 124, GIR_Done, // Label 1469: @79924 GIM_Try, /*On fail goto*//*Label 1470*/ 79987, // Rule ID 125 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1787:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 125, GIR_Done, // Label 1470: @79987 GIM_Try, /*On fail goto*//*Label 1471*/ 80050, // Rule ID 126 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1824:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 126, GIR_Done, // Label 1471: @80050 GIM_Try, /*On fail goto*//*Label 1472*/ 80113, // Rule ID 127 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1825:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 127, GIR_Done, // Label 1472: @80113 GIM_Try, /*On fail goto*//*Label 1473*/ 80176, // Rule ID 128 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1826:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 128, GIR_Done, // Label 1473: @80176 GIM_Try, /*On fail goto*//*Label 1474*/ 80239, // Rule ID 129 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1839:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 129, GIR_Done, // Label 1474: @80239 GIM_Try, /*On fail goto*//*Label 1475*/ 80302, // Rule ID 130 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1837:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 130, GIR_Done, // Label 1475: @80302 GIM_Try, /*On fail goto*//*Label 1476*/ 80365, // Rule ID 131 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1838:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 131, GIR_Done, // Label 1476: @80365 GIM_Try, /*On fail goto*//*Label 1477*/ 80428, // Rule ID 132 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1857:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 132, GIR_Done, // Label 1477: @80428 GIM_Try, /*On fail goto*//*Label 1478*/ 80491, // Rule ID 133 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1858:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 133, GIR_Done, // Label 1478: @80491 GIM_Try, /*On fail goto*//*Label 1479*/ 80554, // Rule ID 134 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1859:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 134, GIR_Done, // Label 1479: @80554 GIM_Try, /*On fail goto*//*Label 1480*/ 80617, // Rule ID 437 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1789:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 437, GIR_Done, // Label 1480: @80617 GIM_Try, /*On fail goto*//*Label 1481*/ 80680, // Rule ID 450 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1788:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 450, GIR_Done, // Label 1481: @80680 GIM_Try, /*On fail goto*//*Label 1482*/ 80743, // Rule ID 451 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1786:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 451, GIR_Done, // Label 1482: @80743 GIM_Try, /*On fail goto*//*Label 1483*/ 80806, // Rule ID 452 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 452, GIR_Done, // Label 1483: @80806 GIM_Try, /*On fail goto*//*Label 1484*/ 80869, // Rule ID 453 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1824:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 453, GIR_Done, // Label 1484: @80869 GIM_Try, /*On fail goto*//*Label 1485*/ 80932, // Rule ID 454 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1825:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 454, GIR_Done, // Label 1485: @80932 GIM_Try, /*On fail goto*//*Label 1486*/ 80995, // Rule ID 455 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1826:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 455, GIR_Done, // Label 1486: @80995 GIM_Try, /*On fail goto*//*Label 1487*/ 81058, // Rule ID 456 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1839:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 456, GIR_Done, // Label 1487: @81058 GIM_Try, /*On fail goto*//*Label 1488*/ 81121, // Rule ID 457 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1837:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 457, GIR_Done, // Label 1488: @81121 GIM_Try, /*On fail goto*//*Label 1489*/ 81184, // Rule ID 458 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 458, GIR_Done, // Label 1489: @81184 GIM_Try, /*On fail goto*//*Label 1490*/ 81247, // Rule ID 459 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1857:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 459, GIR_Done, // Label 1490: @81247 GIM_Try, /*On fail goto*//*Label 1491*/ 81310, // Rule ID 460 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1858:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 460, GIR_Done, // Label 1491: @81310 GIM_Try, /*On fail goto*//*Label 1492*/ 81373, // Rule ID 461 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID, // (intrinsic_w_chain:{ *:[i32] } 1859:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 461, GIR_Done, // Label 1492: @81373 GIM_Reject, // Label 1457: @81374 GIM_Try, /*On fail goto*//*Label 1493*/ 81652, GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vstr_scatter_base_wb, GIM_Try, /*On fail goto*//*Label 1494*/ 81450, // Rule ID 3840 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v4i32] } 1642:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3840, GIR_Done, // Label 1494: @81450 GIM_Try, /*On fail goto*//*Label 1495*/ 81517, // Rule ID 3850 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v4i32] } 1642:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3850, GIR_Done, // Label 1495: @81517 GIM_Try, /*On fail goto*//*Label 1496*/ 81584, // Rule ID 3854 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v2i64] } 1642:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3854, GIR_Done, // Label 1496: @81584 GIM_Try, /*On fail goto*//*Label 1497*/ 81651, // Rule ID 3858 // GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, // MIs[1] Operand 1 // No operand predicates GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (intrinsic_w_chain:{ *:[v2i64] } 1642:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3858, GIR_Done, // Label 1497: @81651 GIM_Reject, // Label 1493: @81652 GIM_Try, /*On fail goto*//*Label 1498*/ 82989, GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, GIM_Try, /*On fail goto*//*Label 1499*/ 81727, // Rule ID 3728 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3728, GIR_Done, // Label 1499: @81727 GIM_Try, /*On fail goto*//*Label 1500*/ 81797, // Rule ID 3729 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3729, GIR_Done, // Label 1500: @81797 GIM_Try, /*On fail goto*//*Label 1501*/ 81867, // Rule ID 3732 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB8_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3732, GIR_Done, // Label 1501: @81867 GIM_Try, /*On fail goto*//*Label 1502*/ 81937, // Rule ID 3812 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3812, GIR_Done, // Label 1502: @81937 GIM_Try, /*On fail goto*//*Label 1503*/ 82007, // Rule ID 3814 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3814, GIR_Done, // Label 1503: @82007 GIM_Try, /*On fail goto*//*Label 1504*/ 82077, // Rule ID 3816 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3816, GIR_Done, // Label 1504: @82077 GIM_Try, /*On fail goto*//*Label 1505*/ 82147, // Rule ID 3817 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3817, GIR_Done, // Label 1505: @82147 GIM_Try, /*On fail goto*//*Label 1506*/ 82217, // Rule ID 3820 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3820, GIR_Done, // Label 1506: @82217 GIM_Try, /*On fail goto*//*Label 1507*/ 82287, // Rule ID 3821 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3821, GIR_Done, // Label 1507: @82287 GIM_Try, /*On fail goto*//*Label 1508*/ 82357, // Rule ID 3824 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3824, GIR_Done, // Label 1508: @82357 GIM_Try, /*On fail goto*//*Label 1509*/ 82427, // Rule ID 3825 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3825, GIR_Done, // Label 1509: @82427 GIM_Try, /*On fail goto*//*Label 1510*/ 82497, // Rule ID 3828 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3828, GIR_Done, // Label 1510: @82497 GIM_Try, /*On fail goto*//*Label 1511*/ 82567, // Rule ID 3829 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3829, GIR_Done, // Label 1511: @82567 GIM_Try, /*On fail goto*//*Label 1512*/ 82637, // Rule ID 3832 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3832, GIR_Done, // Label 1512: @82637 GIM_Try, /*On fail goto*//*Label 1513*/ 82707, // Rule ID 3833 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3, // (intrinsic_void 1644:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3833, GIR_Done, // Label 1513: @82707 GIM_Try, /*On fail goto*//*Label 1514*/ 82779, // Rule ID 267 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_void 1530:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 267, GIR_Done, // Label 1514: @82779 GIM_Try, /*On fail goto*//*Label 1515*/ 82844, // Rule ID 268 // GIM_CheckFeatures, GIFBS_IsARM_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_void 1531:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 268, GIR_Done, // Label 1515: @82844 GIM_Try, /*On fail goto*//*Label 1516*/ 82916, // Rule ID 610 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_void 1530:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 610, GIR_Done, // Label 1516: @82916 GIM_Try, /*On fail goto*//*Label 1517*/ 82988, // Rule ID 611 // GIM_CheckFeatures, GIFBS_IsThumb2_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // (intrinsic_void 1531:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 611, GIR_Done, // Label 1517: @82988 GIM_Reject, // Label 1498: @82989 GIM_Try, /*On fail goto*//*Label 1518*/ 86829, GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, GIM_Try, /*On fail goto*//*Label 1519*/ 83063, // Rule ID 255 // GIM_CheckFeatures, GIFBS_IsARM_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, // MIs[0] CRd GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1498:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 255, GIR_Done, // Label 1519: @83063 GIM_Try, /*On fail goto*//*Label 1520*/ 83125, // Rule ID 256 // GIM_CheckFeatures, GIFBS_IsARM_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, // MIs[0] CRd GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1499:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 256, GIR_Done, // Label 1520: @83125 GIM_Try, /*On fail goto*//*Label 1521*/ 83194, // Rule ID 612 // GIM_CheckFeatures, GIFBS_IsThumb2_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, // MIs[0] CRd GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1498:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 612, GIR_Done, // Label 1521: @83194 GIM_Try, /*On fail goto*//*Label 1522*/ 83263, // Rule ID 613 // GIM_CheckFeatures, GIFBS_IsThumb2_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, // MIs[0] CRd GIM_CheckIsImm, /*MI*/0, /*Op*/3, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1499:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 613, GIR_Done, // Label 1522: @83263 GIM_Try, /*On fail goto*//*Label 1523*/ 83341, // Rule ID 3722 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3722, GIR_Done, // Label 1523: @83341 GIM_Try, /*On fail goto*//*Label 1524*/ 83419, // Rule ID 3723 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3723, GIR_Done, // Label 1524: @83419 GIM_Try, /*On fail goto*//*Label 1525*/ 83497, // Rule ID 3726 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v16i8] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3726, GIR_Done, // Label 1525: @83497 GIM_Try, /*On fail goto*//*Label 1526*/ 83575, // Rule ID 3734 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v16i8] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3734, GIR_Done, // Label 1526: @83575 GIM_Try, /*On fail goto*//*Label 1527*/ 83653, // Rule ID 3736 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3736, GIR_Done, // Label 1527: @83653 GIM_Try, /*On fail goto*//*Label 1528*/ 83731, // Rule ID 3738 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3738, GIR_Done, // Label 1528: @83731 GIM_Try, /*On fail goto*//*Label 1529*/ 83809, // Rule ID 3740 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3740, GIR_Done, // Label 1529: @83809 GIM_Try, /*On fail goto*//*Label 1530*/ 83887, // Rule ID 3742 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3742, GIR_Done, // Label 1530: @83887 GIM_Try, /*On fail goto*//*Label 1531*/ 83965, // Rule ID 3744 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3744, GIR_Done, // Label 1531: @83965 GIM_Try, /*On fail goto*//*Label 1532*/ 84043, // Rule ID 3745 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3745, GIR_Done, // Label 1532: @84043 GIM_Try, /*On fail goto*//*Label 1533*/ 84121, // Rule ID 3748 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3748, GIR_Done, // Label 1533: @84121 GIM_Try, /*On fail goto*//*Label 1534*/ 84199, // Rule ID 3749 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3749, GIR_Done, // Label 1534: @84199 GIM_Try, /*On fail goto*//*Label 1535*/ 84277, // Rule ID 3752 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3752, GIR_Done, // Label 1535: @84277 GIM_Try, /*On fail goto*//*Label 1536*/ 84355, // Rule ID 3753 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8i16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3753, GIR_Done, // Label 1536: @84355 GIM_Try, /*On fail goto*//*Label 1537*/ 84433, // Rule ID 3756 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3756, GIR_Done, // Label 1537: @84433 GIM_Try, /*On fail goto*//*Label 1538*/ 84511, // Rule ID 3757 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3757, GIR_Done, // Label 1538: @84511 GIM_Try, /*On fail goto*//*Label 1539*/ 84589, // Rule ID 3760 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3760, GIR_Done, // Label 1539: @84589 GIM_Try, /*On fail goto*//*Label 1540*/ 84667, // Rule ID 3761 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v8f16] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3761, GIR_Done, // Label 1540: @84667 GIM_Try, /*On fail goto*//*Label 1541*/ 84745, // Rule ID 3764 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3764, GIR_Done, // Label 1541: @84745 GIM_Try, /*On fail goto*//*Label 1542*/ 84823, // Rule ID 3765 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3765, GIR_Done, // Label 1542: @84823 GIM_Try, /*On fail goto*//*Label 1543*/ 84901, // Rule ID 3768 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3768, GIR_Done, // Label 1543: @84901 GIM_Try, /*On fail goto*//*Label 1544*/ 84979, // Rule ID 3769 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3769, GIR_Done, // Label 1544: @84979 GIM_Try, /*On fail goto*//*Label 1545*/ 85057, // Rule ID 3772 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3772, GIR_Done, // Label 1545: @85057 GIM_Try, /*On fail goto*//*Label 1546*/ 85135, // Rule ID 3773 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3773, GIR_Done, // Label 1546: @85135 GIM_Try, /*On fail goto*//*Label 1547*/ 85213, // Rule ID 3776 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3776, GIR_Done, // Label 1547: @85213 GIM_Try, /*On fail goto*//*Label 1548*/ 85291, // Rule ID 3777 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3777, GIR_Done, // Label 1548: @85291 GIM_Try, /*On fail goto*//*Label 1549*/ 85369, // Rule ID 3780 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3780, GIR_Done, // Label 1549: @85369 GIM_Try, /*On fail goto*//*Label 1550*/ 85447, // Rule ID 3781 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3781, GIR_Done, // Label 1550: @85447 GIM_Try, /*On fail goto*//*Label 1551*/ 85525, // Rule ID 3784 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3784, GIR_Done, // Label 1551: @85525 GIM_Try, /*On fail goto*//*Label 1552*/ 85603, // Rule ID 3785 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4i32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3785, GIR_Done, // Label 1552: @85603 GIM_Try, /*On fail goto*//*Label 1553*/ 85681, // Rule ID 3788 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3788, GIR_Done, // Label 1553: @85681 GIM_Try, /*On fail goto*//*Label 1554*/ 85759, // Rule ID 3789 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3789, GIR_Done, // Label 1554: @85759 GIM_Try, /*On fail goto*//*Label 1555*/ 85837, // Rule ID 3792 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3792, GIR_Done, // Label 1555: @85837 GIM_Try, /*On fail goto*//*Label 1556*/ 85915, // Rule ID 3793 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v4f32] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3793, GIR_Done, // Label 1556: @85915 GIM_Try, /*On fail goto*//*Label 1557*/ 85993, // Rule ID 3796 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3796, GIR_Done, // Label 1557: @85993 GIM_Try, /*On fail goto*//*Label 1558*/ 86071, // Rule ID 3797 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3797, GIR_Done, // Label 1558: @86071 GIM_Try, /*On fail goto*//*Label 1559*/ 86149, // Rule ID 3800 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3800, GIR_Done, // Label 1559: @86149 GIM_Try, /*On fail goto*//*Label 1560*/ 86227, // Rule ID 3801 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3801, GIR_Done, // Label 1560: @86227 GIM_Try, /*On fail goto*//*Label 1561*/ 86305, // Rule ID 3804 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3804, GIR_Done, // Label 1561: @86305 GIM_Try, /*On fail goto*//*Label 1562*/ 86383, // Rule ID 3805 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3805, GIR_Done, // Label 1562: @86383 GIM_Try, /*On fail goto*//*Label 1563*/ 86461, // Rule ID 3808 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3808, GIR_Done, // Label 1563: @86461 GIM_Try, /*On fail goto*//*Label 1564*/ 86539, // Rule ID 3809 // GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, // MIs[0] base GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64, GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3, GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1, // (intrinsic_w_chain:{ *:[v2i64] } 1605:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3809, GIR_Done, // Label 1564: @86539 GIM_Try, /*On fail goto*//*Label 1565*/ 86613, // Rule ID 265 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 265, GIR_Done, // Label 1565: @86613 GIM_Try, /*On fail goto*//*Label 1566*/ 86680, // Rule ID 266 // GIM_CheckFeatures, GIFBS_IsARM_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 266, GIR_Done, // Label 1566: @86680 GIM_Try, /*On fail goto*//*Label 1567*/ 86754, // Rule ID 608 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1528:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 608, GIR_Done, // Label 1567: @86754 GIM_Try, /*On fail goto*//*Label 1568*/ 86828, // Rule ID 609 // GIM_CheckFeatures, GIFBS_IsThumb2_PreV8, GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // MIs[0] cop GIM_CheckIsImm, /*MI*/0, /*Op*/1, // MIs[0] opc1 GIM_CheckIsImm, /*MI*/0, /*Op*/2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID, // MIs[0] CRn GIM_CheckIsImm, /*MI*/0, /*Op*/4, // MIs[0] CRm GIM_CheckIsImm, /*MI*/0, /*Op*/5, // MIs[0] opc2 GIM_CheckIsImm, /*MI*/0, /*Op*/6, // (intrinsic_void 1529:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2 GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 609, GIR_Done, // Label 1568: @86828 GIM_Reject, // Label 1518: @86829 GIM_Reject, // Label 14: @86830 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1572*/ 86964, /*GILLT_v2s64*//*Label 1569*/ 86844, 0, 0, /*GILLT_v4s32*//*Label 1570*/ 86884, 0, 0, 0, /*GILLT_v8s16*//*Label 1571*/ 86924, // Label 1569: @86844 GIM_Try, /*On fail goto*//*Label 1573*/ 86883, // Rule ID 2537 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2537, GIR_Done, // Label 1573: @86883 GIM_Reject, // Label 1570: @86884 GIM_Try, /*On fail goto*//*Label 1574*/ 86923, // Rule ID 2536 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2536, GIR_Done, // Label 1574: @86923 GIM_Reject, // Label 1571: @86924 GIM_Try, /*On fail goto*//*Label 1575*/ 86963, // Rule ID 2535 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2535, GIR_Done, // Label 1575: @86963 GIM_Reject, // Label 1572: @86964 GIM_Reject, // Label 15: @86965 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 14, /*)*//*default:*//*Label 1582*/ 87243, /*GILLT_v2s32*//*Label 1576*/ 86982, 0, /*GILLT_v4s1*//*Label 1577*/ 87022, /*GILLT_v4s16*//*Label 1578*/ 87069, 0, 0, /*GILLT_v8s1*//*Label 1579*/ 87109, /*GILLT_v8s8*//*Label 1580*/ 87156, 0, 0, /*GILLT_v16s1*//*Label 1581*/ 87196, // Label 1576: @86982 GIM_Try, /*On fail goto*//*Label 1583*/ 87021, // Rule ID 1576 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1576, GIR_Done, // Label 1583: @87021 GIM_Reject, // Label 1577: @87022 GIM_Try, /*On fail goto*//*Label 1584*/ 87068, // Rule ID 3881 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (trunc:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1) => (MVE_VCMPi32r:{ *:[v4i1] } MQPR:{ *:[v4i32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3881, GIR_Done, // Label 1584: @87068 GIM_Reject, // Label 1578: @87069 GIM_Try, /*On fail goto*//*Label 1585*/ 87108, // Rule ID 1575 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1575, GIR_Done, // Label 1585: @87108 GIM_Reject, // Label 1579: @87109 GIM_Try, /*On fail goto*//*Label 1586*/ 87155, // Rule ID 3880 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (trunc:{ *:[v8i1] } MQPR:{ *:[v8i16] }:$v1) => (MVE_VCMPi32r:{ *:[v8i1] } MQPR:{ *:[v8i16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3880, GIR_Done, // Label 1586: @87155 GIM_Reject, // Label 1580: @87156 GIM_Try, /*On fail goto*//*Label 1587*/ 87195, // Rule ID 1574 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1574, GIR_Done, // Label 1587: @87195 GIM_Reject, // Label 1581: @87196 GIM_Try, /*On fail goto*//*Label 1588*/ 87242, // Rule ID 3879 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (trunc:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1) => (MVE_VCMPi32r:{ *:[v16i1] } MQPR:{ *:[v16i8] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPi32r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3879, GIR_Done, // Label 1588: @87242 GIM_Reject, // Label 1582: @87243 GIM_Reject, // Label 16: @87244 GIM_Try, /*On fail goto*//*Label 1589*/ 87440, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1590*/ 87287, // Rule ID 410 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] })<>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 410, GIR_Done, // Label 1590: @87287 GIM_Try, /*On fail goto*//*Label 1591*/ 87324, // Rule ID 59 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_mod_imm, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] })<>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 59, GIR_Done, // Label 1591: @87324 GIM_Try, /*On fail goto*//*Label 1592*/ 87357, // Rule ID 60 // GIM_CheckFeatures, GIFBS_HasV6T2_IsARM, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] })<>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 60, GIR_Done, // Label 1592: @87357 GIM_Try, /*On fail goto*//*Label 1593*/ 87383, // Rule ID 277 // GIM_CheckFeatures, GIFBS_IsARM, GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_arm_i32imm, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] })<>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi32imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 277, GIR_Done, // Label 1593: @87383 GIM_Try, /*On fail goto*//*Label 1594*/ 87416, // Rule ID 411 // GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb, GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] })<>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 411, GIR_Done, // Label 1594: @87416 GIM_Try, /*On fail goto*//*Label 1595*/ 87439, // Rule ID 597 // GIM_CheckFeatures, GIFBS_IsThumb_UseMovt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 597, GIR_Done, // Label 1595: @87439 GIM_Reject, // Label 1589: @87440 GIM_Reject, // Label 17: @87441 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1598*/ 87519, /*GILLT_s32*//*Label 1596*/ 87449, /*GILLT_s64*//*Label 1597*/ 87484, // Label 1596: @87449 GIM_Try, /*On fail goto*//*Label 1599*/ 87483, // Rule ID 743 // GIM_CheckFeatures, GIFBS_HasVFP3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f32imm, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f32] })<><>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF32Imm, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 743, GIR_Done, // Label 1599: @87483 GIM_Reject, // Label 1597: @87484 GIM_Try, /*On fail goto*//*Label 1600*/ 87518, // Rule ID 742 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP3, GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f64imm, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, // MIs[0] Operand 1 // No operand predicates // (fpimm:{ *:[f64] })<><>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF64Imm, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 742, GIR_Done, // Label 1600: @87518 GIM_Reject, // Label 1598: @87519 GIM_Reject, // Label 18: @87520 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1604*/ 87654, /*GILLT_v2s64*//*Label 1601*/ 87534, 0, 0, /*GILLT_v4s32*//*Label 1602*/ 87574, 0, 0, 0, /*GILLT_v8s16*//*Label 1603*/ 87614, // Label 1601: @87534 GIM_Try, /*On fail goto*//*Label 1605*/ 87573, // Rule ID 1588 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1588, GIR_Done, // Label 1605: @87573 GIM_Reject, // Label 1602: @87574 GIM_Try, /*On fail goto*//*Label 1606*/ 87613, // Rule ID 1587 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1587, GIR_Done, // Label 1606: @87613 GIM_Reject, // Label 1603: @87614 GIM_Try, /*On fail goto*//*Label 1607*/ 87653, // Rule ID 1586 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1586, GIR_Done, // Label 1607: @87653 GIM_Reject, // Label 1604: @87654 GIM_Reject, // Label 19: @87655 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1611*/ 88176, /*GILLT_v2s64*//*Label 1608*/ 87669, 0, 0, /*GILLT_v4s32*//*Label 1609*/ 87838, 0, 0, 0, /*GILLT_v8s16*//*Label 1610*/ 88007, // Label 1608: @87669 GIM_Try, /*On fail goto*//*Label 1612*/ 87837, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 1613*/ 87742, // Rule ID 1163 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1163, GIR_Done, // Label 1613: @87742 GIM_Try, /*On fail goto*//*Label 1614*/ 87805, // Rule ID 1166 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1166, GIR_Done, // Label 1614: @87805 GIM_Try, /*On fail goto*//*Label 1615*/ 87836, // Rule ID 1591 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1591, GIR_Done, // Label 1615: @87836 GIM_Reject, // Label 1612: @87837 GIM_Reject, // Label 1609: @87838 GIM_Try, /*On fail goto*//*Label 1616*/ 88006, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 1617*/ 87911, // Rule ID 1162 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1662:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1162, GIR_Done, // Label 1617: @87911 GIM_Try, /*On fail goto*//*Label 1618*/ 87974, // Rule ID 1165 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1663:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1165, GIR_Done, // Label 1618: @87974 GIM_Try, /*On fail goto*//*Label 1619*/ 88005, // Rule ID 1590 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1590, GIR_Done, // Label 1619: @88005 GIM_Reject, // Label 1616: @88006 GIM_Reject, // Label 1610: @88007 GIM_Try, /*On fail goto*//*Label 1620*/ 88175, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 1621*/ 88080, // Rule ID 1161 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1662:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1161, GIR_Done, // Label 1621: @88080 GIM_Try, /*On fail goto*//*Label 1622*/ 88143, // Rule ID 1164 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC, GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1663:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1164, GIR_Done, // Label 1622: @88143 GIM_Try, /*On fail goto*//*Label 1623*/ 88174, // Rule ID 1589 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1589, GIR_Done, // Label 1623: @88174 GIM_Reject, // Label 1620: @88175 GIM_Reject, // Label 1611: @88176 GIM_Reject, // Label 20: @88177 GIM_Try, /*On fail goto*//*Label 1624*/ 88285, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_Try, /*On fail goto*//*Label 1625*/ 88245, // Rule ID 476 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31, // MIs[1] Operand 1 // No operand predicates GIM_CheckIsSafeToFold, /*InsnID*/1, // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 476, GIR_Done, // Label 1625: @88245 GIM_Try, /*On fail goto*//*Label 1626*/ 88284, // Rule ID 477 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 477, GIR_Done, // Label 1626: @88284 GIM_Reject, // Label 1624: @88285 GIM_Reject, // Label 21: @88286 GIM_Try, /*On fail goto*//*Label 1627*/ 88345, // Rule ID 479 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 479, GIR_Done, // Label 1627: @88345 GIM_Reject, // Label 22: @88346 GIM_Try, /*On fail goto*//*Label 1628*/ 88563, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1629*/ 88412, // Rule ID 203 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 203, GIR_Done, // Label 1629: @88412 GIM_Try, /*On fail goto*//*Label 1630*/ 88464, // Rule ID 336 // GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 336, GIR_Done, // Label 1630: @88464 GIM_Try, /*On fail goto*//*Label 1631*/ 88562, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_Try, /*On fail goto*//*Label 1632*/ 88518, // Rule ID 544 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16, GIM_CheckIsSafeToFold, /*InsnID*/1, // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 544, GIR_Done, // Label 1632: @88518 GIM_Try, /*On fail goto*//*Label 1633*/ 88561, // Rule ID 481 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 481, GIR_Done, // Label 1633: @88561 GIM_Reject, // Label 1631: @88562 GIM_Reject, // Label 1628: @88563 GIM_Reject, // Label 23: @88564 GIM_Try, /*On fail goto*//*Label 1634*/ 88665, GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 1635*/ 88621, // Rule ID 180 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID, // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMUL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 180, GIR_Done, // Label 1635: @88621 GIM_Try, /*On fail goto*//*Label 1636*/ 88664, // Rule ID 513 // GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID, // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMUL, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 513, GIR_Done, // Label 1636: @88664 GIM_Reject, // Label 1634: @88665 GIM_Reject, // Label 24: @88666 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1644*/ 89435, /*GILLT_s16*//*Label 1637*/ 88684, /*GILLT_s32*//*Label 1638*/ 88736, /*GILLT_s64*//*Label 1639*/ 88788, /*GILLT_v2s32*//*Label 1640*/ 88840, 0, 0, /*GILLT_v4s16*//*Label 1641*/ 88892, /*GILLT_v4s32*//*Label 1642*/ 89075, 0, 0, 0, /*GILLT_v8s16*//*Label 1643*/ 89187, // Label 1637: @88684 GIM_Try, /*On fail goto*//*Label 1645*/ 88735, // Rule ID 627 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 627, GIR_Done, // Label 1645: @88735 GIM_Reject, // Label 1638: @88736 GIM_Try, /*On fail goto*//*Label 1646*/ 88787, // Rule ID 626 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 626, GIR_Done, // Label 1646: @88787 GIM_Reject, // Label 1639: @88788 GIM_Try, /*On fail goto*//*Label 1647*/ 88839, // Rule ID 625 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 625, GIR_Done, // Label 1647: @88839 GIM_Reject, // Label 1640: @88840 GIM_Try, /*On fail goto*//*Label 1648*/ 88891, // Rule ID 779 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 779, GIR_Done, // Label 1648: @88891 GIM_Reject, // Label 1641: @88892 GIM_Try, /*On fail goto*//*Label 1649*/ 89074, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1650*/ 88970, // Rule ID 4302 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4302, GIR_Done, // Label 1650: @88970 GIM_Try, /*On fail goto*//*Label 1651*/ 89034, // Rule ID 948 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 948, GIR_Done, // Label 1651: @89034 GIM_Try, /*On fail goto*//*Label 1652*/ 89073, // Rule ID 781 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 781, GIR_Done, // Label 1652: @89073 GIM_Reject, // Label 1649: @89074 GIM_Reject, // Label 1642: @89075 GIM_Try, /*On fail goto*//*Label 1653*/ 89186, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1654*/ 89128, // Rule ID 780 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 780, GIR_Done, // Label 1654: @89128 GIM_Try, /*On fail goto*//*Label 1655*/ 89185, // Rule ID 3384 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3384, GIR_Done, // Label 1655: @89185 GIM_Reject, // Label 1653: @89186 GIM_Reject, // Label 1643: @89187 GIM_Try, /*On fail goto*//*Label 1656*/ 89434, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1657*/ 89265, // Rule ID 4303 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4303, GIR_Done, // Label 1657: @89265 GIM_Try, /*On fail goto*//*Label 1658*/ 89333, // Rule ID 949 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 949, GIR_Done, // Label 1658: @89333 GIM_Try, /*On fail goto*//*Label 1659*/ 89376, // Rule ID 782 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 782, GIR_Done, // Label 1659: @89376 GIM_Try, /*On fail goto*//*Label 1660*/ 89433, // Rule ID 3386 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3386, GIR_Done, // Label 1660: @89433 GIM_Reject, // Label 1656: @89434 GIM_Reject, // Label 1644: @89435 GIM_Reject, // Label 25: @89436 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1668*/ 90197, /*GILLT_s16*//*Label 1661*/ 89454, /*GILLT_s32*//*Label 1662*/ 89506, /*GILLT_s64*//*Label 1663*/ 89558, /*GILLT_v2s32*//*Label 1664*/ 89610, 0, 0, /*GILLT_v4s16*//*Label 1665*/ 89662, /*GILLT_v4s32*//*Label 1666*/ 89837, 0, 0, 0, /*GILLT_v8s16*//*Label 1667*/ 89949, // Label 1661: @89454 GIM_Try, /*On fail goto*//*Label 1669*/ 89505, // Rule ID 630 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 630, GIR_Done, // Label 1669: @89505 GIM_Reject, // Label 1662: @89506 GIM_Try, /*On fail goto*//*Label 1670*/ 89557, // Rule ID 629 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 629, GIR_Done, // Label 1670: @89557 GIM_Reject, // Label 1663: @89558 GIM_Try, /*On fail goto*//*Label 1671*/ 89609, // Rule ID 628 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 628, GIR_Done, // Label 1671: @89609 GIM_Reject, // Label 1664: @89610 GIM_Try, /*On fail goto*//*Label 1672*/ 89661, // Rule ID 966 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 966, GIR_Done, // Label 1672: @89661 GIM_Reject, // Label 1665: @89662 GIM_Try, /*On fail goto*//*Label 1673*/ 89836, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1674*/ 89740, // Rule ID 926 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 926, GIR_Done, // Label 1674: @89740 GIM_Try, /*On fail goto*//*Label 1675*/ 89800, // Rule ID 952 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 952, GIR_Done, // Label 1675: @89800 GIM_Try, /*On fail goto*//*Label 1676*/ 89835, // Rule ID 968 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 968, GIR_Done, // Label 1676: @89835 GIM_Reject, // Label 1673: @89836 GIM_Reject, // Label 1666: @89837 GIM_Try, /*On fail goto*//*Label 1677*/ 89948, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1678*/ 89890, // Rule ID 967 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 967, GIR_Done, // Label 1678: @89890 GIM_Try, /*On fail goto*//*Label 1679*/ 89947, // Rule ID 3388 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3388, GIR_Done, // Label 1679: @89947 GIM_Reject, // Label 1677: @89948 GIM_Reject, // Label 1667: @89949 GIM_Try, /*On fail goto*//*Label 1680*/ 90196, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1681*/ 90027, // Rule ID 927 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 927, GIR_Done, // Label 1681: @90027 GIM_Try, /*On fail goto*//*Label 1682*/ 90095, // Rule ID 953 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 953, GIR_Done, // Label 1682: @90095 GIM_Try, /*On fail goto*//*Label 1683*/ 90138, // Rule ID 969 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 969, GIR_Done, // Label 1683: @90138 GIM_Try, /*On fail goto*//*Label 1684*/ 90195, // Rule ID 3390 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3390, GIR_Done, // Label 1684: @90195 GIM_Reject, // Label 1680: @90196 GIM_Reject, // Label 1668: @90197 GIM_Reject, // Label 26: @90198 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1692*/ 90914, /*GILLT_s16*//*Label 1685*/ 90216, /*GILLT_s32*//*Label 1686*/ 90268, /*GILLT_s64*//*Label 1687*/ 90427, /*GILLT_v2s32*//*Label 1688*/ 90586, 0, 0, /*GILLT_v4s16*//*Label 1689*/ 90638, /*GILLT_v4s32*//*Label 1690*/ 90690, 0, 0, 0, /*GILLT_v8s16*//*Label 1691*/ 90802, // Label 1685: @90216 GIM_Try, /*On fail goto*//*Label 1693*/ 90267, // Rule ID 636 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 636, GIR_Done, // Label 1693: @90267 GIM_Reject, // Label 1686: @90268 GIM_Try, /*On fail goto*//*Label 1694*/ 90426, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_Try, /*On fail goto*//*Label 1695*/ 90334, // Rule ID 2238 // GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2238, GIR_Done, // Label 1695: @90334 GIM_Try, /*On fail goto*//*Label 1696*/ 90386, // Rule ID 4428 // GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4428, GIR_Done, // Label 1696: @90386 GIM_Try, /*On fail goto*//*Label 1697*/ 90425, // Rule ID 635 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 635, GIR_Done, // Label 1697: @90425 GIM_Reject, // Label 1694: @90426 GIM_Reject, // Label 1687: @90427 GIM_Try, /*On fail goto*//*Label 1698*/ 90585, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1699*/ 90493, // Rule ID 2237 // GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2237, GIR_Done, // Label 1699: @90493 GIM_Try, /*On fail goto*//*Label 1700*/ 90545, // Rule ID 4427 // GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 4427, GIR_Done, // Label 1700: @90545 GIM_Try, /*On fail goto*//*Label 1701*/ 90584, // Rule ID 634 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 634, GIR_Done, // Label 1701: @90584 GIM_Reject, // Label 1698: @90585 GIM_Reject, // Label 1688: @90586 GIM_Try, /*On fail goto*//*Label 1702*/ 90637, // Rule ID 846 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 846, GIR_Done, // Label 1702: @90637 GIM_Reject, // Label 1689: @90638 GIM_Try, /*On fail goto*//*Label 1703*/ 90689, // Rule ID 848 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 848, GIR_Done, // Label 1703: @90689 GIM_Reject, // Label 1690: @90690 GIM_Try, /*On fail goto*//*Label 1704*/ 90801, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1705*/ 90743, // Rule ID 847 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 847, GIR_Done, // Label 1705: @90743 GIM_Try, /*On fail goto*//*Label 1706*/ 90800, // Rule ID 3372 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3372, GIR_Done, // Label 1706: @90800 GIM_Reject, // Label 1704: @90801 GIM_Reject, // Label 1691: @90802 GIM_Try, /*On fail goto*//*Label 1707*/ 90913, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1708*/ 90855, // Rule ID 849 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 849, GIR_Done, // Label 1708: @90855 GIM_Try, /*On fail goto*//*Label 1709*/ 90912, // Rule ID 3374 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3374, GIR_Done, // Label 1709: @90912 GIM_Reject, // Label 1707: @90913 GIM_Reject, // Label 1692: @90914 GIM_Reject, // Label 27: @90915 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1717*/ 92275, /*GILLT_s16*//*Label 1710*/ 90933, /*GILLT_s32*//*Label 1711*/ 91253, /*GILLT_s64*//*Label 1712*/ 91573, /*GILLT_v2s32*//*Label 1713*/ 91893, 0, 0, /*GILLT_v4s16*//*Label 1714*/ 92020, /*GILLT_v4s32*//*Label 1715*/ 92084, 0, 0, 0, /*GILLT_v8s16*//*Label 1716*/ 92211, // Label 1710: @90933 GIM_Try, /*On fail goto*//*Label 1718*/ 91252, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_Try, /*On fail goto*//*Label 1719*/ 91024, // Rule ID 2327 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2327, GIR_Done, // Label 1719: @91024 GIM_Try, /*On fail goto*//*Label 1720*/ 91084, // Rule ID 2316 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2316, GIR_Done, // Label 1720: @91084 GIM_Try, /*On fail goto*//*Label 1721*/ 91144, // Rule ID 2319 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2319, GIR_Done, // Label 1721: @91144 GIM_Try, /*On fail goto*//*Label 1722*/ 91204, // Rule ID 2332 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2332, GIR_Done, // Label 1722: @91204 GIM_Try, /*On fail goto*//*Label 1723*/ 91251, // Rule ID 2310 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID, // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2310, GIR_Done, // Label 1723: @91251 GIM_Reject, // Label 1718: @91252 GIM_Reject, // Label 1711: @91253 GIM_Try, /*On fail goto*//*Label 1724*/ 91572, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_Try, /*On fail goto*//*Label 1725*/ 91344, // Rule ID 2326 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2326, GIR_Done, // Label 1725: @91344 GIM_Try, /*On fail goto*//*Label 1726*/ 91404, // Rule ID 2315 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2315, GIR_Done, // Label 1726: @91404 GIM_Try, /*On fail goto*//*Label 1727*/ 91464, // Rule ID 2318 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2318, GIR_Done, // Label 1727: @91464 GIM_Try, /*On fail goto*//*Label 1728*/ 91524, // Rule ID 2331 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2331, GIR_Done, // Label 1728: @91524 GIM_Try, /*On fail goto*//*Label 1729*/ 91571, // Rule ID 2309 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID, // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2309, GIR_Done, // Label 1729: @91571 GIM_Reject, // Label 1724: @91572 GIM_Reject, // Label 1712: @91573 GIM_Try, /*On fail goto*//*Label 1730*/ 91892, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1731*/ 91664, // Rule ID 2325 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2325, GIR_Done, // Label 1731: @91664 GIM_Try, /*On fail goto*//*Label 1732*/ 91724, // Rule ID 2314 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2314, GIR_Done, // Label 1732: @91724 GIM_Try, /*On fail goto*//*Label 1733*/ 91784, // Rule ID 2317 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2317, GIR_Done, // Label 1733: @91784 GIM_Try, /*On fail goto*//*Label 1734*/ 91844, // Rule ID 2330 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2330, GIR_Done, // Label 1734: @91844 GIM_Try, /*On fail goto*//*Label 1735*/ 91891, // Rule ID 2308 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2308, GIR_Done, // Label 1735: @91891 GIM_Reject, // Label 1730: @91892 GIM_Reject, // Label 1713: @91893 GIM_Try, /*On fail goto*//*Label 1736*/ 92019, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1737*/ 91971, // Rule ID 2418 // GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2418, GIR_Done, // Label 1737: @91971 GIM_Try, /*On fail goto*//*Label 1738*/ 92018, // Rule ID 2416 // GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2416, GIR_Done, // Label 1738: @92018 GIM_Reject, // Label 1736: @92019 GIM_Reject, // Label 1714: @92020 GIM_Try, /*On fail goto*//*Label 1739*/ 92083, // Rule ID 2414 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID, // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2414, GIR_Done, // Label 1739: @92083 GIM_Reject, // Label 1715: @92084 GIM_Try, /*On fail goto*//*Label 1740*/ 92210, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_Try, /*On fail goto*//*Label 1741*/ 92162, // Rule ID 2419 // GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2419, GIR_Done, // Label 1741: @92162 GIM_Try, /*On fail goto*//*Label 1742*/ 92209, // Rule ID 2417 // GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2417, GIR_Done, // Label 1742: @92209 GIM_Reject, // Label 1740: @92210 GIM_Reject, // Label 1716: @92211 GIM_Try, /*On fail goto*//*Label 1743*/ 92274, // Rule ID 2415 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID, // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2415, GIR_Done, // Label 1743: @92274 GIM_Reject, // Label 1717: @92275 GIM_Reject, // Label 28: @92276 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 1747*/ 92441, /*GILLT_s16*//*Label 1744*/ 92285, /*GILLT_s32*//*Label 1745*/ 92337, /*GILLT_s64*//*Label 1746*/ 92389, // Label 1744: @92285 GIM_Try, /*On fail goto*//*Label 1748*/ 92336, // Rule ID 633 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 633, GIR_Done, // Label 1748: @92336 GIM_Reject, // Label 1745: @92337 GIM_Try, /*On fail goto*//*Label 1749*/ 92388, // Rule ID 632 // GIM_CheckFeatures, GIFBS_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 632, GIR_Done, // Label 1749: @92388 GIM_Reject, // Label 1746: @92389 GIM_Try, /*On fail goto*//*Label 1750*/ 92440, // Rule ID 631 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 631, GIR_Done, // Label 1750: @92440 GIM_Reject, // Label 1747: @92441 GIM_Reject, // Label 29: @92442 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1758*/ 93711, /*GILLT_s16*//*Label 1751*/ 92460, /*GILLT_s32*//*Label 1752*/ 92789, /*GILLT_s64*//*Label 1753*/ 93118, /*GILLT_v2s32*//*Label 1754*/ 93447, 0, 0, /*GILLT_v4s16*//*Label 1755*/ 93487, /*GILLT_v4s32*//*Label 1756*/ 93527, 0, 0, 0, /*GILLT_v8s16*//*Label 1757*/ 93619, // Label 1751: @92460 GIM_Try, /*On fail goto*//*Label 1759*/ 92788, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_Try, /*On fail goto*//*Label 1760*/ 92551, // Rule ID 2335 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2335, GIR_Done, // Label 1760: @92551 GIM_Try, /*On fail goto*//*Label 1761*/ 92632, // Rule ID 2338 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2338, GIR_Done, // Label 1761: @92632 GIM_Try, /*On fail goto*//*Label 1762*/ 92700, // Rule ID 2324 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2324, GIR_Done, // Label 1762: @92700 GIM_Try, /*On fail goto*//*Label 1763*/ 92756, // Rule ID 639 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 639, GIR_Done, // Label 1763: @92756 GIM_Try, /*On fail goto*//*Label 1764*/ 92787, // Rule ID 677 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 677, GIR_Done, // Label 1764: @92787 GIM_Reject, // Label 1759: @92788 GIM_Reject, // Label 1752: @92789 GIM_Try, /*On fail goto*//*Label 1765*/ 93117, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_Try, /*On fail goto*//*Label 1766*/ 92880, // Rule ID 2334 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2334, GIR_Done, // Label 1766: @92880 GIM_Try, /*On fail goto*//*Label 1767*/ 92961, // Rule ID 2337 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2337, GIR_Done, // Label 1767: @92961 GIM_Try, /*On fail goto*//*Label 1768*/ 93029, // Rule ID 2323 // GIM_CheckFeatures, GIFBS_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2323, GIR_Done, // Label 1768: @93029 GIM_Try, /*On fail goto*//*Label 1769*/ 93085, // Rule ID 638 // GIM_CheckFeatures, GIFBS_HasVFP2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 638, GIR_Done, // Label 1769: @93085 GIM_Try, /*On fail goto*//*Label 1770*/ 93116, // Rule ID 676 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 676, GIR_Done, // Label 1770: @93116 GIM_Reject, // Label 1765: @93117 GIM_Reject, // Label 1753: @93118 GIM_Try, /*On fail goto*//*Label 1771*/ 93446, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_Try, /*On fail goto*//*Label 1772*/ 93209, // Rule ID 2333 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2333, GIR_Done, // Label 1772: @93209 GIM_Try, /*On fail goto*//*Label 1773*/ 93290, // Rule ID 2336 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, GIM_CheckIsSafeToFold, /*InsnID*/2, // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2336, GIR_Done, // Label 1773: @93290 GIM_Try, /*On fail goto*//*Label 1774*/ 93358, // Rule ID 2322 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2322, GIR_Done, // Label 1774: @93358 GIM_Try, /*On fail goto*//*Label 1775*/ 93414, // Rule ID 637 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 637, GIR_Done, // Label 1775: @93414 GIM_Try, /*On fail goto*//*Label 1776*/ 93445, // Rule ID 675 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 675, GIR_Done, // Label 1776: @93445 GIM_Reject, // Label 1771: @93446 GIM_Reject, // Label 1754: @93447 GIM_Try, /*On fail goto*//*Label 1777*/ 93486, // Rule ID 1518 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1518, GIR_Done, // Label 1777: @93486 GIM_Reject, // Label 1755: @93487 GIM_Try, /*On fail goto*//*Label 1778*/ 93526, // Rule ID 1520 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1520, GIR_Done, // Label 1778: @93526 GIM_Reject, // Label 1756: @93527 GIM_Try, /*On fail goto*//*Label 1779*/ 93618, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1780*/ 93568, // Rule ID 1519 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1519, GIR_Done, // Label 1780: @93568 GIM_Try, /*On fail goto*//*Label 1781*/ 93617, // Rule ID 3411 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VNEGf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3411, GIR_Done, // Label 1781: @93617 GIM_Reject, // Label 1779: @93618 GIM_Reject, // Label 1757: @93619 GIM_Try, /*On fail goto*//*Label 1782*/ 93710, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1783*/ 93660, // Rule ID 1521 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1521, GIR_Done, // Label 1783: @93660 GIM_Try, /*On fail goto*//*Label 1784*/ 93709, // Rule ID 3410 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VNEGf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VNEGf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3410, GIR_Done, // Label 1784: @93709 GIM_Reject, // Label 1782: @93710 GIM_Reject, // Label 1758: @93711 GIM_Reject, // Label 30: @93712 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1787*/ 93871, /*GILLT_s32*//*Label 1785*/ 93720, /*GILLT_s64*//*Label 1786*/ 93776, // Label 1785: @93720 GIM_Try, /*On fail goto*//*Label 1788*/ 93775, // Rule ID 2239 // GIM_CheckFeatures, GIFBS_HasFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2239, GIR_Done, // Label 1788: @93775 GIM_Reject, // Label 1786: @93776 GIM_Try, /*On fail goto*//*Label 1789*/ 93815, // Rule ID 673 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 673, GIR_Done, // Label 1789: @93815 GIM_Try, /*On fail goto*//*Label 1790*/ 93870, // Rule ID 2243 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2243, GIR_Done, // Label 1790: @93870 GIM_Reject, // Label 1787: @93871 GIM_Reject, // Label 31: @93872 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1793*/ 94035, /*GILLT_s16*//*Label 1791*/ 93880, /*GILLT_s32*//*Label 1792*/ 93995, // Label 1791: @93880 GIM_Try, /*On fail goto*//*Label 1794*/ 93937, // Rule ID 2241 // GIM_CheckFeatures, GIFBS_HasFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0, // GIR_Coverage, 2241, GIR_Done, // Label 1794: @93937 GIM_Try, /*On fail goto*//*Label 1795*/ 93994, // Rule ID 2245 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0, // GIR_Coverage, 2245, GIR_Done, // Label 1795: @93994 GIM_Reject, // Label 1792: @93995 GIM_Try, /*On fail goto*//*Label 1796*/ 94034, // Rule ID 674 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 674, GIR_Done, // Label 1796: @94034 GIM_Reject, // Label 1793: @94035 GIM_Reject, // Label 32: @94036 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 1804*/ 95150, /*GILLT_s32*//*Label 1797*/ 94053, 0, /*GILLT_v2s32*//*Label 1798*/ 94792, 0, /*GILLT_v4s1*//*Label 1799*/ 94832, /*GILLT_v4s16*//*Label 1800*/ 94879, /*GILLT_v4s32*//*Label 1801*/ 94919, 0, /*GILLT_v8s1*//*Label 1802*/ 95011, 0, /*GILLT_v8s16*//*Label 1803*/ 95058, // Label 1797: @94053 GIM_Try, /*On fail goto*//*Label 1805*/ 94116, // Rule ID 2253 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2253, GIR_Done, // Label 1805: @94116 GIM_Try, /*On fail goto*//*Label 1806*/ 94179, // Rule ID 2255 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2255, GIR_Done, // Label 1806: @94179 GIM_Try, /*On fail goto*//*Label 1807*/ 94242, // Rule ID 2257 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2257, GIR_Done, // Label 1807: @94242 GIM_Try, /*On fail goto*//*Label 1808*/ 94305, // Rule ID 2259 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2259, GIR_Done, // Label 1808: @94305 GIM_Try, /*On fail goto*//*Label 1809*/ 94368, // Rule ID 2261 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2261, GIR_Done, // Label 1809: @94368 GIM_Try, /*On fail goto*//*Label 1810*/ 94431, // Rule ID 2263 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2263, GIR_Done, // Label 1810: @94431 GIM_Try, /*On fail goto*//*Label 1811*/ 94494, // Rule ID 2247 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2247, GIR_Done, // Label 1811: @94494 GIM_Try, /*On fail goto*//*Label 1812*/ 94557, // Rule ID 2249 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2249, GIR_Done, // Label 1812: @94557 GIM_Try, /*On fail goto*//*Label 1813*/ 94620, // Rule ID 2251 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2251, GIR_Done, // Label 1813: @94620 GIM_Try, /*On fail goto*//*Label 1814*/ 94677, // Rule ID 2280 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2280, GIR_Done, // Label 1814: @94677 GIM_Try, /*On fail goto*//*Label 1815*/ 94734, // Rule ID 2282 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2282, GIR_Done, // Label 1815: @94734 GIM_Try, /*On fail goto*//*Label 1816*/ 94791, // Rule ID 2284 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2284, GIR_Done, // Label 1816: @94791 GIM_Reject, // Label 1798: @94792 GIM_Try, /*On fail goto*//*Label 1817*/ 94831, // Rule ID 1592 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1592, GIR_Done, // Label 1817: @94831 GIM_Reject, // Label 1799: @94832 GIM_Try, /*On fail goto*//*Label 1818*/ 94878, // Rule ID 3888 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3888, GIR_Done, // Label 1818: @94878 GIM_Reject, // Label 1800: @94879 GIM_Try, /*On fail goto*//*Label 1819*/ 94918, // Rule ID 1600 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1600, GIR_Done, // Label 1819: @94918 GIM_Reject, // Label 1801: @94919 GIM_Try, /*On fail goto*//*Label 1820*/ 95010, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1821*/ 94960, // Rule ID 1596 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1596, GIR_Done, // Label 1821: @94960 GIM_Try, /*On fail goto*//*Label 1822*/ 95009, // Rule ID 3400 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3400, GIR_Done, // Label 1822: @95009 GIM_Reject, // Label 1820: @95010 GIM_Reject, // Label 1802: @95011 GIM_Try, /*On fail goto*//*Label 1823*/ 95057, // Rule ID 3889 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3889, GIR_Done, // Label 1823: @95057 GIM_Reject, // Label 1803: @95058 GIM_Try, /*On fail goto*//*Label 1824*/ 95149, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1825*/ 95099, // Rule ID 1604 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1604, GIR_Done, // Label 1825: @95099 GIM_Try, /*On fail goto*//*Label 1826*/ 95148, // Rule ID 3402 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3402, GIR_Done, // Label 1826: @95148 GIM_Reject, // Label 1824: @95149 GIM_Reject, // Label 1804: @95150 GIM_Reject, // Label 33: @95151 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 1834*/ 96265, /*GILLT_s32*//*Label 1827*/ 95168, 0, /*GILLT_v2s32*//*Label 1828*/ 95907, 0, /*GILLT_v4s1*//*Label 1829*/ 95947, /*GILLT_v4s16*//*Label 1830*/ 95994, /*GILLT_v4s32*//*Label 1831*/ 96034, 0, /*GILLT_v8s1*//*Label 1832*/ 96126, 0, /*GILLT_v8s16*//*Label 1833*/ 96173, // Label 1827: @95168 GIM_Try, /*On fail goto*//*Label 1835*/ 95231, // Rule ID 2254 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2254, GIR_Done, // Label 1835: @95231 GIM_Try, /*On fail goto*//*Label 1836*/ 95294, // Rule ID 2256 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2256, GIR_Done, // Label 1836: @95294 GIM_Try, /*On fail goto*//*Label 1837*/ 95357, // Rule ID 2258 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2258, GIR_Done, // Label 1837: @95357 GIM_Try, /*On fail goto*//*Label 1838*/ 95420, // Rule ID 2260 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2260, GIR_Done, // Label 1838: @95420 GIM_Try, /*On fail goto*//*Label 1839*/ 95483, // Rule ID 2262 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2262, GIR_Done, // Label 1839: @95483 GIM_Try, /*On fail goto*//*Label 1840*/ 95546, // Rule ID 2264 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2264, GIR_Done, // Label 1840: @95546 GIM_Try, /*On fail goto*//*Label 1841*/ 95609, // Rule ID 2248 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2248, GIR_Done, // Label 1841: @95609 GIM_Try, /*On fail goto*//*Label 1842*/ 95672, // Rule ID 2250 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2250, GIR_Done, // Label 1842: @95672 GIM_Try, /*On fail goto*//*Label 1843*/ 95735, // Rule ID 2252 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND, GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckIsSafeToFold, /*InsnID*/1, // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2252, GIR_Done, // Label 1843: @95735 GIM_Try, /*On fail goto*//*Label 1844*/ 95792, // Rule ID 2285 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2285, GIR_Done, // Label 1844: @95792 GIM_Try, /*On fail goto*//*Label 1845*/ 95849, // Rule ID 2287 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2287, GIR_Done, // Label 1845: @95849 GIM_Try, /*On fail goto*//*Label 1846*/ 95906, // Rule ID 2289 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/4, // GIR_Coverage, 2289, GIR_Done, // Label 1846: @95906 GIM_Reject, // Label 1828: @95907 GIM_Try, /*On fail goto*//*Label 1847*/ 95946, // Rule ID 1593 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1593, GIR_Done, // Label 1847: @95946 GIM_Reject, // Label 1829: @95947 GIM_Try, /*On fail goto*//*Label 1848*/ 95993, // Rule ID 3886 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3886, GIR_Done, // Label 1848: @95993 GIM_Reject, // Label 1830: @95994 GIM_Try, /*On fail goto*//*Label 1849*/ 96033, // Rule ID 1601 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1601, GIR_Done, // Label 1849: @96033 GIM_Reject, // Label 1831: @96034 GIM_Try, /*On fail goto*//*Label 1850*/ 96125, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1851*/ 96075, // Rule ID 1597 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1597, GIR_Done, // Label 1851: @96075 GIM_Try, /*On fail goto*//*Label 1852*/ 96124, // Rule ID 3401 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3401, GIR_Done, // Label 1852: @96124 GIM_Reject, // Label 1850: @96125 GIM_Reject, // Label 1832: @96126 GIM_Try, /*On fail goto*//*Label 1853*/ 96172, // Rule ID 3887 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/1, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3887, GIR_Done, // Label 1853: @96172 GIM_Reject, // Label 1833: @96173 GIM_Try, /*On fail goto*//*Label 1854*/ 96264, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1855*/ 96214, // Rule ID 1605 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1605, GIR_Done, // Label 1855: @96214 GIM_Try, /*On fail goto*//*Label 1856*/ 96263, // Rule ID 3403 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16z, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3403, GIR_Done, // Label 1856: @96263 GIM_Reject, // Label 1854: @96264 GIM_Reject, // Label 1834: @96265 GIM_Reject, // Label 34: @96266 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1864*/ 96716, /*GILLT_s16*//*Label 1857*/ 96284, /*GILLT_s32*//*Label 1858*/ 96340, /*GILLT_s64*//*Label 1859*/ 96396, /*GILLT_v2s32*//*Label 1860*/ 96452, 0, 0, /*GILLT_v4s16*//*Label 1861*/ 96492, /*GILLT_v4s32*//*Label 1862*/ 96532, 0, 0, 0, /*GILLT_v8s16*//*Label 1863*/ 96624, // Label 1857: @96284 GIM_Try, /*On fail goto*//*Label 1865*/ 96339, // Rule ID 2274 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2274, GIR_Done, // Label 1865: @96339 GIM_Reject, // Label 1858: @96340 GIM_Try, /*On fail goto*//*Label 1866*/ 96395, // Rule ID 2272 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2272, GIR_Done, // Label 1866: @96395 GIM_Reject, // Label 1859: @96396 GIM_Try, /*On fail goto*//*Label 1867*/ 96451, // Rule ID 2270 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2270, GIR_Done, // Label 1867: @96451 GIM_Reject, // Label 1860: @96452 GIM_Try, /*On fail goto*//*Label 1868*/ 96491, // Rule ID 1594 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1594, GIR_Done, // Label 1868: @96491 GIM_Reject, // Label 1861: @96492 GIM_Try, /*On fail goto*//*Label 1869*/ 96531, // Rule ID 1602 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1602, GIR_Done, // Label 1869: @96531 GIM_Reject, // Label 1862: @96532 GIM_Try, /*On fail goto*//*Label 1870*/ 96623, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1871*/ 96573, // Rule ID 1598 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1598, GIR_Done, // Label 1871: @96573 GIM_Try, /*On fail goto*//*Label 1872*/ 96622, // Rule ID 3404 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32n, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3404, GIR_Done, // Label 1872: @96622 GIM_Reject, // Label 1870: @96623 GIM_Reject, // Label 1863: @96624 GIM_Try, /*On fail goto*//*Label 1873*/ 96715, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1874*/ 96665, // Rule ID 1606 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1606, GIR_Done, // Label 1874: @96665 GIM_Try, /*On fail goto*//*Label 1875*/ 96714, // Rule ID 3406 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16n, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3406, GIR_Done, // Label 1875: @96714 GIM_Reject, // Label 1873: @96715 GIM_Reject, // Label 1864: @96716 GIM_Reject, // Label 35: @96717 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1883*/ 97167, /*GILLT_s16*//*Label 1876*/ 96735, /*GILLT_s32*//*Label 1877*/ 96791, /*GILLT_s64*//*Label 1878*/ 96847, /*GILLT_v2s32*//*Label 1879*/ 96903, 0, 0, /*GILLT_v4s16*//*Label 1880*/ 96943, /*GILLT_v4s32*//*Label 1881*/ 96983, 0, 0, 0, /*GILLT_v8s16*//*Label 1882*/ 97075, // Label 1876: @96735 GIM_Try, /*On fail goto*//*Label 1884*/ 96790, // Rule ID 2279 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2279, GIR_Done, // Label 1884: @96790 GIM_Reject, // Label 1877: @96791 GIM_Try, /*On fail goto*//*Label 1885*/ 96846, // Rule ID 2277 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2277, GIR_Done, // Label 1885: @96846 GIM_Reject, // Label 1878: @96847 GIM_Try, /*On fail goto*//*Label 1886*/ 96902, // Rule ID 2275 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2275, GIR_Done, // Label 1886: @96902 GIM_Reject, // Label 1879: @96903 GIM_Try, /*On fail goto*//*Label 1887*/ 96942, // Rule ID 1595 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1595, GIR_Done, // Label 1887: @96942 GIM_Reject, // Label 1880: @96943 GIM_Try, /*On fail goto*//*Label 1888*/ 96982, // Rule ID 1603 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1603, GIR_Done, // Label 1888: @96982 GIM_Reject, // Label 1881: @96983 GIM_Try, /*On fail goto*//*Label 1889*/ 97074, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1890*/ 97024, // Rule ID 1599 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1599, GIR_Done, // Label 1890: @97024 GIM_Try, /*On fail goto*//*Label 1891*/ 97073, // Rule ID 3405 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32n, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3405, GIR_Done, // Label 1891: @97073 GIM_Reject, // Label 1889: @97074 GIM_Reject, // Label 1882: @97075 GIM_Try, /*On fail goto*//*Label 1892*/ 97166, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1893*/ 97116, // Rule ID 1607 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1607, GIR_Done, // Label 1893: @97116 GIM_Try, /*On fail goto*//*Label 1894*/ 97165, // Rule ID 3407 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16n, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3407, GIR_Done, // Label 1894: @97165 GIM_Reject, // Label 1892: @97166 GIM_Reject, // Label 1883: @97167 GIM_Reject, // Label 36: @97168 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1902*/ 97570, /*GILLT_s16*//*Label 1895*/ 97186, /*GILLT_s32*//*Label 1896*/ 97226, /*GILLT_s64*//*Label 1897*/ 97266, /*GILLT_v2s32*//*Label 1898*/ 97306, 0, 0, /*GILLT_v4s16*//*Label 1899*/ 97346, /*GILLT_v4s32*//*Label 1900*/ 97386, 0, 0, 0, /*GILLT_v8s16*//*Label 1901*/ 97478, // Label 1895: @97186 GIM_Try, /*On fail goto*//*Label 1903*/ 97225, // Rule ID 666 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 666, GIR_Done, // Label 1903: @97225 GIM_Reject, // Label 1896: @97226 GIM_Try, /*On fail goto*//*Label 1904*/ 97265, // Rule ID 665 // GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 665, GIR_Done, // Label 1904: @97265 GIM_Reject, // Label 1897: @97266 GIM_Try, /*On fail goto*//*Label 1905*/ 97305, // Rule ID 664 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 664, GIR_Done, // Label 1905: @97305 GIM_Reject, // Label 1898: @97306 GIM_Try, /*On fail goto*//*Label 1906*/ 97345, // Rule ID 1502 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1502, GIR_Done, // Label 1906: @97345 GIM_Reject, // Label 1899: @97346 GIM_Try, /*On fail goto*//*Label 1907*/ 97385, // Rule ID 1504 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1504, GIR_Done, // Label 1907: @97385 GIM_Reject, // Label 1900: @97386 GIM_Try, /*On fail goto*//*Label 1908*/ 97477, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1909*/ 97427, // Rule ID 1503 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1503, GIR_Done, // Label 1909: @97427 GIM_Try, /*On fail goto*//*Label 1910*/ 97476, // Rule ID 3409 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VABSf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3409, GIR_Done, // Label 1910: @97476 GIM_Reject, // Label 1908: @97477 GIM_Reject, // Label 1901: @97478 GIM_Try, /*On fail goto*//*Label 1911*/ 97569, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1912*/ 97519, // Rule ID 1505 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1505, GIR_Done, // Label 1912: @97519 GIM_Try, /*On fail goto*//*Label 1913*/ 97568, // Rule ID 3408 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VABSf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABSf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3408, GIR_Done, // Label 1913: @97568 GIM_Reject, // Label 1911: @97569 GIM_Reject, // Label 1902: @97570 GIM_Reject, // Label 37: @97571 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1921*/ 97933, /*GILLT_s16*//*Label 1914*/ 97589, /*GILLT_s32*//*Label 1915*/ 97621, /*GILLT_s64*//*Label 1916*/ 97653, /*GILLT_v2s32*//*Label 1917*/ 97685, 0, 0, /*GILLT_v4s16*//*Label 1918*/ 97717, /*GILLT_v4s32*//*Label 1919*/ 97749, 0, 0, 0, /*GILLT_v8s16*//*Label 1920*/ 97841, // Label 1914: @97589 GIM_Try, /*On fail goto*//*Label 1922*/ 97620, // Rule ID 655 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 655, GIR_Done, // Label 1922: @97620 GIM_Reject, // Label 1915: @97621 GIM_Try, /*On fail goto*//*Label 1923*/ 97652, // Rule ID 656 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMS, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 656, GIR_Done, // Label 1923: @97652 GIM_Reject, // Label 1916: @97653 GIM_Try, /*On fail goto*//*Label 1924*/ 97684, // Rule ID 657 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMD, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 657, GIR_Done, // Label 1924: @97684 GIM_Reject, // Label 1917: @97685 GIM_Try, /*On fail goto*//*Label 1925*/ 97716, // Rule ID 1221 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDf, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1221, GIR_Done, // Label 1925: @97716 GIM_Reject, // Label 1918: @97717 GIM_Try, /*On fail goto*//*Label 1926*/ 97748, // Rule ID 1223 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDh, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1223, GIR_Done, // Label 1926: @97748 GIM_Reject, // Label 1919: @97749 GIM_Try, /*On fail goto*//*Label 1927*/ 97840, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1928*/ 97782, // Rule ID 1222 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQf, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1222, GIR_Done, // Label 1928: @97782 GIM_Try, /*On fail goto*//*Label 1929*/ 97839, // Rule ID 2893 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2893, GIR_Done, // Label 1929: @97839 GIM_Reject, // Label 1927: @97840 GIM_Reject, // Label 1920: @97841 GIM_Try, /*On fail goto*//*Label 1930*/ 97932, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1931*/ 97874, // Rule ID 1224 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQh, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1224, GIR_Done, // Label 1931: @97874 GIM_Try, /*On fail goto*//*Label 1932*/ 97931, // Rule ID 2894 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2894, GIR_Done, // Label 1932: @97931 GIM_Reject, // Label 1930: @97932 GIM_Reject, // Label 1921: @97933 GIM_Reject, // Label 38: @97934 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1940*/ 98296, /*GILLT_s16*//*Label 1933*/ 97952, /*GILLT_s32*//*Label 1934*/ 97984, /*GILLT_s64*//*Label 1935*/ 98016, /*GILLT_v2s32*//*Label 1936*/ 98048, 0, 0, /*GILLT_v4s16*//*Label 1937*/ 98080, /*GILLT_v4s32*//*Label 1938*/ 98112, 0, 0, 0, /*GILLT_v8s16*//*Label 1939*/ 98204, // Label 1933: @97952 GIM_Try, /*On fail goto*//*Label 1941*/ 97983, // Rule ID 652 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID, // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 652, GIR_Done, // Label 1941: @97983 GIM_Reject, // Label 1934: @97984 GIM_Try, /*On fail goto*//*Label 1942*/ 98015, // Rule ID 653 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID, // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMS, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 653, GIR_Done, // Label 1942: @98015 GIM_Reject, // Label 1935: @98016 GIM_Try, /*On fail goto*//*Label 1943*/ 98047, // Rule ID 654 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMD, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 654, GIR_Done, // Label 1943: @98047 GIM_Reject, // Label 1936: @98048 GIM_Try, /*On fail goto*//*Label 1944*/ 98079, // Rule ID 1201 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDf, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1201, GIR_Done, // Label 1944: @98079 GIM_Reject, // Label 1937: @98080 GIM_Try, /*On fail goto*//*Label 1945*/ 98111, // Rule ID 1203 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDh, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1203, GIR_Done, // Label 1945: @98111 GIM_Reject, // Label 1938: @98112 GIM_Try, /*On fail goto*//*Label 1946*/ 98203, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1947*/ 98145, // Rule ID 1202 // GIM_CheckFeatures, GIFBS_HasNEON_HasV8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQf, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1202, GIR_Done, // Label 1947: @98145 GIM_Try, /*On fail goto*//*Label 1948*/ 98202, // Rule ID 2889 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1, MQPR:{ *:[v4f32] }:$val2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2889, GIR_Done, // Label 1948: @98202 GIM_Reject, // Label 1946: @98203 GIM_Reject, // Label 1939: @98204 GIM_Try, /*On fail goto*//*Label 1949*/ 98295, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1950*/ 98237, // Rule ID 1204 // GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQh, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1204, GIR_Done, // Label 1950: @98237 GIM_Try, /*On fail goto*//*Label 1951*/ 98294, // Rule ID 2890 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1, MQPR:{ *:[v8f16] }:$val2) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val2 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2890, GIR_Done, // Label 1951: @98294 GIM_Reject, // Label 1949: @98295 GIM_Reject, // Label 1940: @98296 GIM_Reject, // Label 39: @98297 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1958*/ 98807, /*GILLT_v2s32*//*Label 1952*/ 98315, 0, 0, /*GILLT_v4s16*//*Label 1953*/ 98367, /*GILLT_v4s32*//*Label 1954*/ 98419, 0, 0, /*GILLT_v8s8*//*Label 1955*/ 98531, /*GILLT_v8s16*//*Label 1956*/ 98583, 0, 0, /*GILLT_v16s8*//*Label 1957*/ 98695, // Label 1952: @98315 GIM_Try, /*On fail goto*//*Label 1959*/ 98366, // Rule ID 1206 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1206, GIR_Done, // Label 1959: @98366 GIM_Reject, // Label 1953: @98367 GIM_Try, /*On fail goto*//*Label 1960*/ 98418, // Rule ID 1205 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1205, GIR_Done, // Label 1960: @98418 GIM_Reject, // Label 1954: @98419 GIM_Try, /*On fail goto*//*Label 1961*/ 98530, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1962*/ 98472, // Rule ID 1208 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1208, GIR_Done, // Label 1962: @98472 GIM_Try, /*On fail goto*//*Label 1963*/ 98529, // Rule ID 2901 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2901, GIR_Done, // Label 1963: @98529 GIM_Reject, // Label 1961: @98530 GIM_Reject, // Label 1955: @98531 GIM_Try, /*On fail goto*//*Label 1964*/ 98582, // Rule ID 1209 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1209, GIR_Done, // Label 1964: @98582 GIM_Reject, // Label 1956: @98583 GIM_Try, /*On fail goto*//*Label 1965*/ 98694, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1966*/ 98636, // Rule ID 1207 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1207, GIR_Done, // Label 1966: @98636 GIM_Try, /*On fail goto*//*Label 1967*/ 98693, // Rule ID 2899 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2899, GIR_Done, // Label 1967: @98693 GIM_Reject, // Label 1965: @98694 GIM_Reject, // Label 1957: @98695 GIM_Try, /*On fail goto*//*Label 1968*/ 98806, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 1969*/ 98748, // Rule ID 1210 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1210, GIR_Done, // Label 1969: @98748 GIM_Try, /*On fail goto*//*Label 1970*/ 98805, // Rule ID 2897 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2897, GIR_Done, // Label 1970: @98805 GIM_Reject, // Label 1968: @98806 GIM_Reject, // Label 1958: @98807 GIM_Reject, // Label 40: @98808 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1977*/ 99318, /*GILLT_v2s32*//*Label 1971*/ 98826, 0, 0, /*GILLT_v4s16*//*Label 1972*/ 98878, /*GILLT_v4s32*//*Label 1973*/ 98930, 0, 0, /*GILLT_v8s8*//*Label 1974*/ 99042, /*GILLT_v8s16*//*Label 1975*/ 99094, 0, 0, /*GILLT_v16s8*//*Label 1976*/ 99206, // Label 1971: @98826 GIM_Try, /*On fail goto*//*Label 1978*/ 98877, // Rule ID 1186 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1186, GIR_Done, // Label 1978: @98877 GIM_Reject, // Label 1972: @98878 GIM_Try, /*On fail goto*//*Label 1979*/ 98929, // Rule ID 1185 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1185, GIR_Done, // Label 1979: @98929 GIM_Reject, // Label 1973: @98930 GIM_Try, /*On fail goto*//*Label 1980*/ 99041, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 1981*/ 98983, // Rule ID 1188 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1188, GIR_Done, // Label 1981: @98983 GIM_Try, /*On fail goto*//*Label 1982*/ 99040, // Rule ID 2913 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2913, GIR_Done, // Label 1982: @99040 GIM_Reject, // Label 1980: @99041 GIM_Reject, // Label 1974: @99042 GIM_Try, /*On fail goto*//*Label 1983*/ 99093, // Rule ID 1189 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1189, GIR_Done, // Label 1983: @99093 GIM_Reject, // Label 1975: @99094 GIM_Try, /*On fail goto*//*Label 1984*/ 99205, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 1985*/ 99147, // Rule ID 1187 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1187, GIR_Done, // Label 1985: @99147 GIM_Try, /*On fail goto*//*Label 1986*/ 99204, // Rule ID 2911 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2911, GIR_Done, // Label 1986: @99204 GIM_Reject, // Label 1984: @99205 GIM_Reject, // Label 1976: @99206 GIM_Try, /*On fail goto*//*Label 1987*/ 99317, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 1988*/ 99259, // Rule ID 1190 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1190, GIR_Done, // Label 1988: @99259 GIM_Try, /*On fail goto*//*Label 1989*/ 99316, // Rule ID 2909 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2909, GIR_Done, // Label 1989: @99316 GIM_Reject, // Label 1987: @99317 GIM_Reject, // Label 1977: @99318 GIM_Reject, // Label 41: @99319 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 1996*/ 99829, /*GILLT_v2s32*//*Label 1990*/ 99337, 0, 0, /*GILLT_v4s16*//*Label 1991*/ 99389, /*GILLT_v4s32*//*Label 1992*/ 99441, 0, 0, /*GILLT_v8s8*//*Label 1993*/ 99553, /*GILLT_v8s16*//*Label 1994*/ 99605, 0, 0, /*GILLT_v16s8*//*Label 1995*/ 99717, // Label 1990: @99337 GIM_Try, /*On fail goto*//*Label 1997*/ 99388, // Rule ID 1212 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1212, GIR_Done, // Label 1997: @99388 GIM_Reject, // Label 1991: @99389 GIM_Try, /*On fail goto*//*Label 1998*/ 99440, // Rule ID 1211 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1211, GIR_Done, // Label 1998: @99440 GIM_Reject, // Label 1992: @99441 GIM_Try, /*On fail goto*//*Label 1999*/ 99552, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 2000*/ 99494, // Rule ID 1214 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1214, GIR_Done, // Label 2000: @99494 GIM_Try, /*On fail goto*//*Label 2001*/ 99551, // Rule ID 2907 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2907, GIR_Done, // Label 2001: @99551 GIM_Reject, // Label 1999: @99552 GIM_Reject, // Label 1993: @99553 GIM_Try, /*On fail goto*//*Label 2002*/ 99604, // Rule ID 1215 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1215, GIR_Done, // Label 2002: @99604 GIM_Reject, // Label 1994: @99605 GIM_Try, /*On fail goto*//*Label 2003*/ 99716, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 2004*/ 99658, // Rule ID 1213 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1213, GIR_Done, // Label 2004: @99658 GIM_Try, /*On fail goto*//*Label 2005*/ 99715, // Rule ID 2905 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2905, GIR_Done, // Label 2005: @99715 GIM_Reject, // Label 2003: @99716 GIM_Reject, // Label 1995: @99717 GIM_Try, /*On fail goto*//*Label 2006*/ 99828, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 2007*/ 99770, // Rule ID 1216 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1216, GIR_Done, // Label 2007: @99770 GIM_Try, /*On fail goto*//*Label 2008*/ 99827, // Rule ID 2903 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2903, GIR_Done, // Label 2008: @99827 GIM_Reject, // Label 2006: @99828 GIM_Reject, // Label 1996: @99829 GIM_Reject, // Label 42: @99830 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2015*/ 100340, /*GILLT_v2s32*//*Label 2009*/ 99848, 0, 0, /*GILLT_v4s16*//*Label 2010*/ 99900, /*GILLT_v4s32*//*Label 2011*/ 99952, 0, 0, /*GILLT_v8s8*//*Label 2012*/ 100064, /*GILLT_v8s16*//*Label 2013*/ 100116, 0, 0, /*GILLT_v16s8*//*Label 2014*/ 100228, // Label 2009: @99848 GIM_Try, /*On fail goto*//*Label 2016*/ 99899, // Rule ID 1192 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1192, GIR_Done, // Label 2016: @99899 GIM_Reject, // Label 2010: @99900 GIM_Try, /*On fail goto*//*Label 2017*/ 99951, // Rule ID 1191 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1191, GIR_Done, // Label 2017: @99951 GIM_Reject, // Label 2011: @99952 GIM_Try, /*On fail goto*//*Label 2018*/ 100063, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 2019*/ 100005, // Rule ID 1194 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1194, GIR_Done, // Label 2019: @100005 GIM_Try, /*On fail goto*//*Label 2020*/ 100062, // Rule ID 2919 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2919, GIR_Done, // Label 2020: @100062 GIM_Reject, // Label 2018: @100063 GIM_Reject, // Label 2012: @100064 GIM_Try, /*On fail goto*//*Label 2021*/ 100115, // Rule ID 1195 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID, // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1195, GIR_Done, // Label 2021: @100115 GIM_Reject, // Label 2013: @100116 GIM_Try, /*On fail goto*//*Label 2022*/ 100227, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 2023*/ 100169, // Rule ID 1193 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1193, GIR_Done, // Label 2023: @100169 GIM_Try, /*On fail goto*//*Label 2024*/ 100226, // Rule ID 2917 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2917, GIR_Done, // Label 2024: @100226 GIM_Reject, // Label 2022: @100227 GIM_Reject, // Label 2014: @100228 GIM_Try, /*On fail goto*//*Label 2025*/ 100339, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 2026*/ 100281, // Rule ID 1196 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID, // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1196, GIR_Done, // Label 2026: @100281 GIM_Try, /*On fail goto*//*Label 2027*/ 100338, // Rule ID 2915 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID, // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2915, GIR_Done, // Label 2027: @100338 GIM_Reject, // Label 2025: @100339 GIM_Reject, // Label 2015: @100340 GIM_Reject, // Label 43: @100341 GIM_Try, /*On fail goto*//*Label 2028*/ 100404, GIM_CheckIsMBB, /*MI*/0, /*Op*/0, GIM_Try, /*On fail goto*//*Label 2029*/ 100357, // Rule ID 34 // GIM_CheckFeatures, GIFBS_IsARM, // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::B, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 34, GIR_Done, // Label 2029: @100357 GIM_Try, /*On fail goto*//*Label 2030*/ 100380, // Rule ID 291 // GIM_CheckFeatures, GIFBS_IsThumb_IsThumb1Only, // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 291, GIR_Done, // Label 2030: @100380 GIM_Try, /*On fail goto*//*Label 2031*/ 100403, // Rule ID 592 // GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb, // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 592, GIR_Done, // Label 2031: @100403 GIM_Reject, // Label 2028: @100404 GIM_Reject, // Label 44: @100405 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2039*/ 100899, /*GILLT_s32*//*Label 2032*/ 100425, 0, /*GILLT_v2s32*//*Label 2033*/ 100503, 0, 0, /*GILLT_v4s16*//*Label 2034*/ 100543, /*GILLT_v4s32*//*Label 2035*/ 100583, 0, 0, /*GILLT_v8s8*//*Label 2036*/ 100675, /*GILLT_v8s16*//*Label 2037*/ 100715, 0, 0, /*GILLT_v16s8*//*Label 2038*/ 100807, // Label 2032: @100425 GIM_Try, /*On fail goto*//*Label 2040*/ 100502, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 2041*/ 100466, // Rule ID 199 // GIM_CheckFeatures, GIFBS_HasV5T_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLZ, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 199, GIR_Done, // Label 2041: @100466 GIM_Try, /*On fail goto*//*Label 2042*/ 100501, // Rule ID 540 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLZ, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 540, GIR_Done, // Label 2042: @100501 GIM_Reject, // Label 2040: @100502 GIM_Reject, // Label 2033: @100503 GIM_Try, /*On fail goto*//*Label 2043*/ 100542, // Rule ID 1536 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv2i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1536, GIR_Done, // Label 2043: @100542 GIM_Reject, // Label 2034: @100543 GIM_Try, /*On fail goto*//*Label 2044*/ 100582, // Rule ID 1535 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1535, GIR_Done, // Label 2044: @100582 GIM_Reject, // Label 2035: @100583 GIM_Try, /*On fail goto*//*Label 2045*/ 100674, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_Try, /*On fail goto*//*Label 2046*/ 100624, // Rule ID 1539 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1539, GIR_Done, // Label 2046: @100624 GIM_Try, /*On fail goto*//*Label 2047*/ 100673, // Rule ID 3111 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3111, GIR_Done, // Label 2047: @100673 GIM_Reject, // Label 2045: @100674 GIM_Reject, // Label 2036: @100675 GIM_Try, /*On fail goto*//*Label 2048*/ 100714, // Rule ID 1534 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1534, GIR_Done, // Label 2048: @100714 GIM_Reject, // Label 2037: @100715 GIM_Try, /*On fail goto*//*Label 2049*/ 100806, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_Try, /*On fail goto*//*Label 2050*/ 100756, // Rule ID 1538 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1538, GIR_Done, // Label 2050: @100756 GIM_Try, /*On fail goto*//*Label 2051*/ 100805, // Rule ID 3112 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3112, GIR_Done, // Label 2051: @100805 GIM_Reject, // Label 2049: @100806 GIM_Reject, // Label 2038: @100807 GIM_Try, /*On fail goto*//*Label 2052*/ 100898, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_Try, /*On fail goto*//*Label 2053*/ 100848, // Rule ID 1537 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv16i8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1537, GIR_Done, // Label 2053: @100848 GIM_Try, /*On fail goto*//*Label 2054*/ 100897, // Rule ID 3110 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3110, GIR_Done, // Label 2054: @100897 GIM_Reject, // Label 2052: @100898 GIM_Reject, // Label 2039: @100899 GIM_Reject, // Label 45: @100900 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/10, 15, /*)*//*default:*//*Label 2057*/ 100991, /*GILLT_v8s8*//*Label 2055*/ 100911, 0, 0, 0, /*GILLT_v16s8*//*Label 2056*/ 100951, // Label 2055: @100911 GIM_Try, /*On fail goto*//*Label 2058*/ 100950, // Rule ID 1540 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTd, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1540, GIR_Done, // Label 2058: @100950 GIM_Reject, // Label 2056: @100951 GIM_Try, /*On fail goto*//*Label 2059*/ 100990, // Rule ID 1541 // GIM_CheckFeatures, GIFBS_HasNEON, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID, // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTq, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 1541, GIR_Done, // Label 2059: @100990 GIM_Reject, // Label 2057: @100991 GIM_Reject, // Label 46: @100992 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2063*/ 101230, /*GILLT_s32*//*Label 2060*/ 101009, 0, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2061*/ 101122, 0, 0, 0, /*GILLT_v8s16*//*Label 2062*/ 101176, // Label 2060: @101009 GIM_Try, /*On fail goto*//*Label 2064*/ 101121, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 2065*/ 101050, // Rule ID 201 // GIM_CheckFeatures, GIFBS_HasV6_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 201, GIR_Done, // Label 2065: @101050 GIM_Try, /*On fail goto*//*Label 2066*/ 101085, // Rule ID 334 // GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID, // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 334, GIR_Done, // Label 2066: @101085 GIM_Try, /*On fail goto*//*Label 2067*/ 101120, // Rule ID 542 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 542, GIR_Done, // Label 2067: @101120 GIM_Reject, // Label 2064: @101121 GIM_Reject, // Label 2061: @101122 GIM_Try, /*On fail goto*//*Label 2068*/ 101175, // Rule ID 2922 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2922, GIR_Done, // Label 2068: @101175 GIM_Reject, // Label 2062: @101176 GIM_Try, /*On fail goto*//*Label 2069*/ 101229, // Rule ID 2921 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 2921, GIR_Done, // Label 2069: @101229 GIM_Reject, // Label 2063: @101230 GIM_Reject, // Label 47: @101231 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2074*/ 101581, /*GILLT_s32*//*Label 2070*/ 101251, 0, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2071*/ 101329, 0, 0, 0, /*GILLT_v8s16*//*Label 2072*/ 101413, 0, 0, /*GILLT_v16s8*//*Label 2073*/ 101497, // Label 2070: @101251 GIM_Try, /*On fail goto*//*Label 2075*/ 101328, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_Try, /*On fail goto*//*Label 2076*/ 101292, // Rule ID 200 // GIM_CheckFeatures, GIFBS_HasV6T2_IsARM, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID, // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RBIT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 200, GIR_Done, // Label 2076: @101292 GIM_Try, /*On fail goto*//*Label 2077*/ 101327, // Rule ID 541 // GIM_CheckFeatures, GIFBS_IsThumb2, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID, // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RBIT, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 541, GIR_Done, // Label 2077: @101327 GIM_Reject, // Label 2075: @101328 GIM_Reject, // Label 2071: @101329 GIM_Try, /*On fail goto*//*Label 2078*/ 101412, // Rule ID 3676 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/32, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3676, GIR_Done, // Label 2078: @101412 GIM_Reject, // Label 2072: @101413 GIM_Try, /*On fail goto*//*Label 2079*/ 101496, // Rule ID 3677 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/16, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3677, GIR_Done, // Label 2079: @101496 GIM_Reject, // Label 2073: @101497 GIM_Try, /*On fail goto*//*Label 2080*/ 101580, // Rule ID 3675 // GIM_CheckFeatures, GIFBS_HasMVEInt, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, GIR_AddImm, /*InsnID*/1, /*Imm*/8, GIR_AddImm, /*InsnID*/1, /*Imm*/14, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddRegister, /*InsnID*/1, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/1, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3675, GIR_Done, // Label 2080: @101580 GIM_Reject, // Label 2074: @101581 GIM_Reject, // Label 48: @101582 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2086*/ 101780, /*GILLT_s16*//*Label 2081*/ 101600, /*GILLT_s32*//*Label 2082*/ 101624, /*GILLT_s64*//*Label 2083*/ 101648, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2084*/ 101672, 0, 0, 0, /*GILLT_v8s16*//*Label 2085*/ 101726, // Label 2081: @101600 GIM_Try, /*On fail goto*//*Label 2087*/ 101623, // Rule ID 693 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 693, GIR_Done, // Label 2087: @101623 GIM_Reject, // Label 2082: @101624 GIM_Try, /*On fail goto*//*Label 2088*/ 101647, // Rule ID 694 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPS, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 694, GIR_Done, // Label 2088: @101647 GIM_Reject, // Label 2083: @101648 GIM_Try, /*On fail goto*//*Label 2089*/ 101671, // Rule ID 695 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPD, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 695, GIR_Done, // Label 2089: @101671 GIM_Reject, // Label 2084: @101672 GIM_Try, /*On fail goto*//*Label 2090*/ 101725, // Rule ID 3370 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32P, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3370, GIR_Done, // Label 2090: @101725 GIM_Reject, // Label 2085: @101726 GIM_Try, /*On fail goto*//*Label 2091*/ 101779, // Rule ID 3371 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16P, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3371, GIR_Done, // Label 2091: @101779 GIM_Reject, // Label 2086: @101780 GIM_Reject, // Label 49: @101781 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2095*/ 101910, /*GILLT_s16*//*Label 2092*/ 101790, /*GILLT_s32*//*Label 2093*/ 101830, /*GILLT_s64*//*Label 2094*/ 101870, // Label 2092: @101790 GIM_Try, /*On fail goto*//*Label 2096*/ 101829, // Rule ID 701 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 701, GIR_Done, // Label 2096: @101829 GIM_Reject, // Label 2093: @101830 GIM_Try, /*On fail goto*//*Label 2097*/ 101869, // Rule ID 700 // GIM_CheckFeatures, GIFBS_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 700, GIR_Done, // Label 2097: @101869 GIM_Reject, // Label 2094: @101870 GIM_Try, /*On fail goto*//*Label 2098*/ 101909, // Rule ID 699 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 699, GIR_Done, // Label 2098: @101909 GIM_Reject, // Label 2095: @101910 GIM_Reject, // Label 50: @101911 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2104*/ 102109, /*GILLT_s16*//*Label 2099*/ 101929, /*GILLT_s32*//*Label 2100*/ 101953, /*GILLT_s64*//*Label 2101*/ 101977, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2102*/ 102001, 0, 0, 0, /*GILLT_v8s16*//*Label 2103*/ 102055, // Label 2099: @101929 GIM_Try, /*On fail goto*//*Label 2105*/ 101952, // Rule ID 696 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMH, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 696, GIR_Done, // Label 2105: @101952 GIM_Reject, // Label 2100: @101953 GIM_Try, /*On fail goto*//*Label 2106*/ 101976, // Rule ID 697 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMS, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 697, GIR_Done, // Label 2106: @101976 GIM_Reject, // Label 2101: @101977 GIM_Try, /*On fail goto*//*Label 2107*/ 102000, // Rule ID 698 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMD, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 698, GIR_Done, // Label 2107: @102000 GIM_Reject, // Label 2102: @102001 GIM_Try, /*On fail goto*//*Label 2108*/ 102054, // Rule ID 3368 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32M, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3368, GIR_Done, // Label 2108: @102054 GIM_Reject, // Label 2103: @102055 GIM_Try, /*On fail goto*//*Label 2109*/ 102108, // Rule ID 3369 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16M, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3369, GIR_Done, // Label 2109: @102108 GIM_Reject, // Label 2104: @102109 GIM_Reject, // Label 51: @102110 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2115*/ 102356, /*GILLT_s16*//*Label 2110*/ 102128, /*GILLT_s32*//*Label 2111*/ 102168, /*GILLT_s64*//*Label 2112*/ 102208, 0, 0, 0, 0, /*GILLT_v4s32*//*Label 2113*/ 102248, 0, 0, 0, /*GILLT_v8s16*//*Label 2114*/ 102302, // Label 2110: @102128 GIM_Try, /*On fail goto*//*Label 2116*/ 102167, // Rule ID 684 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 684, GIR_Done, // Label 2116: @102167 GIM_Reject, // Label 2111: @102168 GIM_Try, /*On fail goto*//*Label 2117*/ 102207, // Rule ID 685 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 685, GIR_Done, // Label 2117: @102207 GIM_Reject, // Label 2112: @102208 GIM_Try, /*On fail goto*//*Label 2118*/ 102247, // Rule ID 686 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 686, GIR_Done, // Label 2118: @102247 GIM_Reject, // Label 2113: @102248 GIM_Try, /*On fail goto*//*Label 2119*/ 102301, // Rule ID 3362 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32X, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3362, GIR_Done, // Label 2119: @102301 GIM_Reject, // Label 2114: @102302 GIM_Try, /*On fail goto*//*Label 2120*/ 102355, // Rule ID 3363 // GIM_CheckFeatures, GIFBS_HasMVEFloat, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID, // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val1) GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16X, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1 GIR_AddImm, /*InsnID*/0, /*Imm*/0, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 3363, GIR_Done, // Label 2120: @102355 GIM_Reject, // Label 2115: @102356 GIM_Reject, // Label 52: @102357 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2124*/ 102486, /*GILLT_s16*//*Label 2121*/ 102366, /*GILLT_s32*//*Label 2122*/ 102406, /*GILLT_s64*//*Label 2123*/ 102446, // Label 2121: @102366 GIM_Try, /*On fail goto*//*Label 2125*/ 102405, // Rule ID 681 // GIM_CheckFeatures, GIFBS_HasFullFP16, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID, // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRH, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 681, GIR_Done, // Label 2125: @102405 GIM_Reject, // Label 2122: @102406 GIM_Try, /*On fail goto*//*Label 2126*/ 102445, // Rule ID 682 // GIM_CheckFeatures, GIFBS_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID, // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRS, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 682, GIR_Done, // Label 2126: @102445 GIM_Reject, // Label 2123: @102446 GIM_Try, /*On fail goto*//*Label 2127*/ 102485, // Rule ID 683 // GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8, GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID, GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID, // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRD, GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm GIR_AddImm, /*InsnID*/0, /*Imm*/14, GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0, GIR_EraseFromParent, /*InsnID*/0, GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // GIR_Coverage, 683, GIR_Done, // Label 2127: @102485 GIM_Reject, // Label 2124: @102486 GIM_Reject, // Label 53: @102487 GIM_Reject, }; return MatchTable0; } #endif // ifdef GET_GLOBALISEL_IMPL #ifdef GET_GLOBALISEL_PREDICATES_DECL PredicateBitset AvailableModuleFeatures; mutable PredicateBitset AvailableFunctionFeatures; PredicateBitset getAvailableFeatures() const { return AvailableModuleFeatures | AvailableFunctionFeatures; } PredicateBitset computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; PredicateBitset computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const; void setupGeneratedPerFunctionState(MachineFunction &MF) override; #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL #ifdef GET_GLOBALISEL_PREDICATES_INIT AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), AvailableFunctionFeatures() #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT