//===-- SPIRVAsmBackend.cpp - SPIR-V Assembler Backend ---------*- C++ -*--===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "MCTargetDesc/SPIRVMCTargetDesc.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/EndianStream.h" using namespace llvm; namespace { class SPIRVAsmBackend : public MCAsmBackend { public: SPIRVAsmBackend(support::endianness Endian) : MCAsmBackend(Endian) {} void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override {} std::unique_ptr createObjectTargetWriter() const override { return createSPIRVObjectTargetWriter(); } // No instruction requires relaxation. bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override { return false; } unsigned getNumFixupKinds() const override { return 1; } bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override { return false; } void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override {} bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override { return false; } }; } // end anonymous namespace MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &) { return new SPIRVAsmBackend(support::little); }