/*
 * Copyright (c) 1992, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
 *
 * %sccs.include.redist.c%
 *
 * from: $Hdr: scc.conf,v 4.300 91/06/09 06:44:55 root Rel41 $ SONY
 *
 *	@(#)scc.conf	8.1 (Berkeley) 06/11/93
 */

/*
 *	SCC initialize data
 */

#define	N_INITDATA	sizeof (sccinit_a)
#define	N_SCC		10

char sccinit_a[] = {
	0x09, 0x80,	/* Channel A Reset			*/
	0x04, 0x44,	/* *16 CLK, 1 Stop Bit, No Parity	*/
	0x02, SCCVEC0,	/* Interrupt Vector			*/
	0x03, 0xc0,	/* Rx 8bit, Rx Disable			*/
	0x05, 0xe2,	/* Tx 8bit, Tx Disable			*/
	0x06, 0x00,	/* Null(No Sync Char)			*/
	0x07, 0x00,	/* Null(No Sync Char)			*/
	0x09, 0x01,	/* MIE Disable				*/
	0x0a, 0x00,	/* NRZ					*/
	0x0b, 0x50,	/* Tx & Rx CLK=BPG, TRXC=IN		*/
	0x0c, 0x0e,	/* Time Const(L) = 14 (9600)		*/
	0x0d, 0x00,	/* Time Const(H) = 0			*/
	0x0e, 0x02,	/* BRG Spc=PCLK, BRG OFF		*/
	0x0e, 0x03,	/* BRG ON				*/
	0x03, 0xc1,	/* Rx Enable				*/
	0x05, 0xea,	/* Tx Enable				*/
	0x0f, 0xa8,	/* Break, CTS, DCD, Interrupt Enable	*/
	0x10, 0x10,	/* Reset Ext/Status Interrupt(Twice)	*/
	0x09, 0x09,	/* MIE					*/
	0x01, 0x17	/* Rx Interrupt and Tx Interrupt Enable	*/
};

char sccinit_b[] = {
	0x09, 0x40,	/* Channel B Reset			*/
	0x04, 0x44,	/* *16 CLK, 1 Stop Bit, No Parity	*/
	0x02, SCCVEC0,	/* Interrupt Vector			*/
	0x03, 0xc0,	/* Rx 8bit, Rx Disable			*/
	0x05, 0xe2,	/* Tx 8bit, Tx Disable			*/
	0x06, 0x00,	/* Null(No Sync Char)			*/
	0x07, 0x00,	/* Null(No Sync Char)			*/
	0x09, 0x01,	/* MIE Disable				*/
	0x0a, 0x00,	/* NRZ					*/
	0x0b, 0x52,	/* Tx & Rx, CLK=BRG, TRXC=INP		*/
	0x0c, 0x0e,	/* Time Const(L) = 14 (9600)		*/
	0x0d, 0x00,	/* Time Const(H)			*/
	0x0e, 0x02,	/* BRG, SRC=PCLK, BRG OFF		*/
	0x0e, 0x03,	/* BRG ON				*/
	0x03, 0xc1,	/* Rx Enable				*/
	0x05, 0xea,	/* Tx Enable				*/
	0x0f, 0xa8,	/* Break, CTS, DCD, Interrupt Enable	*/
	0x10, 0x10,	/* Reset Ext/Status Interrpt(Twice)	*/
	0x09, 0x09,	/* MIE					*/
	0x01, 0x17	/* Rx Interrupt and Tx Interrupt Enable	*/
};

#if defined(news3400)
char sccinitxa[] = {
	0x09, 0x80,	/* Channel A Reset			*/
	0x04, 0x44,	/* *16 CLK, 1 Stop Bit, No Parity	*/
	0x02, SCCVEC0,	/* Interrupt Vector			*/
	0x03, 0xc0,	/* Rx 8bit, Rx Disable			*/
	0x05, 0xe2,	/* Tx 8bit, Tx Disable			*/
	0x06, 0x00,	/* Null(No Sync Char)			*/
	0x07, 0x00,	/* Null(No Sync Char)			*/
	0x09, 0x01,	/* MIE Disable				*/
	0x0a, 0x00,	/* NRZ					*/
	0x0b, 0x50,	/* Tx & Rx CLK=BPG, TRXC=IN		*/
	0x0c, 0x0a,	/* Time Const(L) = 11 (9600)		*/
	0x0d, 0x00,	/* Time Const(H) = 0			*/
	0x0e, 0x02,	/* BRG Spc=PCLK, BRG OFF		*/
	0x0e, 0x03,	/* BRG ON				*/
	0x03, 0xc1,	/* Rx Enable				*/
	0x05, 0xea,	/* Tx Enable				*/
	0x0f, 0xa8,	/* Break, CTS, DCD, Interrupt Enable	*/
	0x10, 0x10,	/* Reset Ext/Status Interrupt(Twice)	*/
	0x09, 0x09,	/* MIE					*/
	0x01, 0x17	/* Rx Interrupt and Tx Interrupt Enable	*/
}, sccinitxb[] = {
	0x09, 0x40,	/* Channel B Reset			*/
	0x04, 0x44,	/* *16 CLK, 1 Stop Bit, No Parity	*/
	0x02, SCCVEC0,	/* Interrupt Vector			*/
	0x03, 0xc0,	/* Rx 8bit, Rx Disable			*/
	0x05, 0xe2,	/* Tx 8bit, Tx Disable			*/
	0x06, 0x00,	/* Null(No Sync Char)			*/
	0x07, 0x00,	/* Null(No Sync Char)			*/
	0x09, 0x01,	/* MIE Disable				*/
	0x0a, 0x00,	/* NRZ					*/
	0x0b, 0x52,	/* Tx & Rx, CLK=BRG, TRXC=INP		*/
	0x0c, 0x0a,	/* Time Const(L)=11 (9600)		*/
	0x0d, 0x00,	/* Time Const(H)			*/
	0x0e, 0x02,	/* BRG, SRC=PCLK, BRG OFF		*/
	0x0e, 0x03,	/* BRG ON				*/
	0x03, 0xc1,	/* Rx Enable				*/
	0x05, 0xea,	/* Tx Enable				*/
	0x0f, 0xa8,	/* Break, CTS, DCD, Interrupt Enable	*/
	0x10, 0x10,	/* Reset Ext/Status Interrpt(Twice)	*/
	0x09, 0x09,	/* MIE					*/
	0x01, 0x17	/* Rx Interrupt and Tx Interrupt Enable	*/
};
#endif /* news3400 */

#if defined(news3400)
Scc_channel sccsw[] = {
	{	/* Remote0 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT0A,
		sccinit_a,
		SCCVEC0,
	},
	{	/* Remote1 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT0B,
		sccinit_b,
		SCCVEC0,
	},
	{	/* Remote2 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT1A,
		sccinitxa,
		SCCVEC1,
	},
	{	/* Remote3 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT1B,
		sccinitxb,
		SCCVEC1,
	},
	{	/* Remote4 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT2A,
		sccinitxa,
		SCCVEC2,
	},
	{	/* Remote5 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT2B,
		sccinitxb,
		SCCVEC2,
	},
	{	/* Remote6 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT3A,
		sccinitxa,
		SCCVEC3,
	},
	{	/* Remote7 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT3B,
		sccinitxb,
		SCCVEC3,
	},
	{	/* Remote8 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT4A,
		sccinitxa,
		SCCVEC4,
	},
	{	/* Remote9 */
		0,
		RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600,
		(struct scc_reg *)SCCPORT4B,
		sccinitxb,
		SCCVEC4,
	},
};
#endif /* news3400 */