1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_accreg.h 7.3 (Berkeley) 06/28/90 8 */ 9 10 /* 11 * ACC LH/DH-11 interface 12 */ 13 14 struct accdma { 15 short csr; /* control and status */ 16 short db; /* data buffer */ 17 u_short ba; /* buss address */ 18 short wc; /* word count */ 19 }; 20 21 struct accdevice { 22 struct accdma input; 23 struct accdma output; 24 }; 25 26 #define icsr input.csr 27 #define iba input.ba 28 #define iwc input.wc 29 #define ocsr output.csr 30 #define oba output.ba 31 #define owc output.wc 32 33 /* 34 * Bits Common to both input and out CSR's 35 */ 36 #define ACC_ERR 0x8000 /* error present */ 37 #define ACC_NXM 0x4000 /* non-existant memory */ 38 #define ACC_RDY 0x0080 /* ready */ 39 #define ACC_IE 0x0040 /* interrupt enable */ 40 #define ACC_RESET 0x0002 /* reset interface */ 41 #define ACC_GO 0x0001 /* start operation */ 42 43 /* 44 * Input Control Status Register 45 */ 46 #define IN_EOM 0x2000 /* end-of-message recieved */ 47 #define IN_HRDY 0x0800 /* host ready */ 48 #define IN_IMPBSY 0x0400 /* IMP not ready */ 49 #define IN_RMR 0x0200 /* receive master ready error */ 50 #define IN_IBF 0x0100 /* input data buffer full */ 51 #define IN_WEN 0x0008 /* write enable */ 52 #define IN_MRDY 0x0004 /* master ready */ 53 54 #define ACC_INBITS \ 55 "\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\ 56 \4WEN\3MRDY\2RESET\1GO" 57 58 /* 59 * Output Control Status Register 60 */ 61 #define OUT_TMR 0x0200 /* transmit master ready error */ 62 #define OUT_BBACK 0x0008 /* bus back */ 63 #define OUT_ENLB 0x0004 /* enable last bit */ 64 65 #define ACC_OUTBITS \ 66 "\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO" 67