1 /* $OpenBSD: pciide_acer_reg.h,v 1.8 2010/07/23 07:47:13 jsg Exp $ */ 2 /* $NetBSD: pciide_acer_reg.h,v 1.4 2001/07/26 20:02:22 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_PCI_PCIIDE_ACER_REG_H_ 30 #define _DEV_PCI_PCIIDE_ACER_REG_H_ 31 32 /* class code attribute register 1 (1 byte) */ 33 #define ACER_CCAR1 0x43 34 #define ACER_CHANSTATUS_RO 0x40 35 #define PCIIDE_CHAN_RO(chan) (0x20 >> (chan)) 36 37 /* from Linux, 80 pins cable detect */ 38 #define ACER_0x4A 0x4a 39 /* 40 * bit 0 is 0 -> primary has 80 pin cable 41 * bit 1 is 0 -> secondary has 80 pin cable 42 */ 43 #define ACER_0x4A_80PIN(chan) (0x1 << (chan)) 44 45 /* From FreeBSD, for UDMA mode > 2 */ 46 #define ACER_0x4B 0x4b 47 #define ACER_0x4B_UDMA66 0x01 48 /* From Linux */ 49 #define ACER_0x4B_CDETECT 0x08 50 51 /* class code attribute register 2 (1 byte) */ 52 #define ACER_CCAR2 0x4d 53 #define ACER_CHANSTATUSREGS_RO 0x80 54 55 /* class code attribute register 3 (1 byte) */ 56 #define ACER_CCAR3 0x50 57 #define ACER_CCAR3_PI 0x02 58 59 /* flexible channel setting register */ 60 #define ACER_FCS 0x52 61 #define ACER_FCS_TIMREG(chan,drv) ((0x8) >> ((drv) + (chan) * 2)) 62 63 /* CD-ROM control register */ 64 #define ACER_CDRC 0x53 65 #define ACER_CDRC_FIFO_DISABLE 0x02 66 #define ACER_CDRC_DMA_EN 0x01 67 68 /* Fifo threshold and Ultra-DMA settings (4 bytes). */ 69 #define ACER_FTH_UDMA 0x54 70 #define ACER_FTH_VAL(chan, drv, val) \ 71 (((val) & 0x3) << ((drv) * 4 + (chan) * 8)) 72 #define ACER_FTH_OPL(chan, drv, val) \ 73 (((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8)) 74 #define ACER_UDMA_EN(chan, drv) \ 75 (0x8 << (16 + (drv) * 4 + (chan) * 8)) 76 #define ACER_UDMA_TIM(chan, drv, val) \ 77 (((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8)) 78 79 /* drives timings setup (1 byte) */ 80 #define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4) 81 82 /* IRQ and drive select status */ 83 #define ACER_CHIDS 0x75 84 #define ACER_CHIDS_DRV(channel) ((0x4) << (channel)) 85 #define ACER_CHIDS_INT(channel) ((0x1) << (channel)) 86 87 /* Linux: south-bridge's enable bit (m1533) */ 88 #define ACER_0x79 0x79 89 #define ACER_0x79_REVC2_EN 0x4 90 #define ACER_0x79_EN 0x2 91 92 /* 93 * IDE bus frequency (1 byte) 94 * This should be setup by the BIOS - can we rely on this ? 95 */ 96 #define ACER_IDE_CLK 0x78 97 98 /* acer UDMA3/4/5 from FreeBSD */ 99 static int8_t acer_udma[] = {0x4, 0x3, 0x2, 0x1, 0x0, 0x7}; 100 static int8_t acer_pio[] = {0x0c, 0x58, 0x44, 0x33, 0x31}; 101 #ifdef unused 102 static int8_t acer_dma[] = {0x08, 0x33, 0x31}; 103 #endif 104 105 #endif /* !_DEV_PCI_PCIIDE_ACER_REG_H_ */ 106