1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2022 Intel Corporation */ 3 #ifndef ADF_4XXX_HW_DATA_H_ 4 #define ADF_4XXX_HW_DATA_H_ 5 6 #include <adf_accel_devices.h> 7 8 #define DEFAULT_4XXX_ASYM_AE_MASK 0x03 9 #define DEFAULT_401XX_ASYM_AE_MASK 0x3F 10 11 /* PCIe configuration space */ 12 #define ADF_4XXX_SRAM_BAR 0 13 #define ADF_4XXX_PMISC_BAR 1 14 #define ADF_4XXX_ETR_BAR 2 15 #define ADF_4XXX_RX_RINGS_OFFSET 1 16 #define ADF_4XXX_TX_RINGS_MASK 0x1 17 #define ADF_4XXX_MAX_ACCELERATORS 1 18 #define ADF_4XXX_MAX_ACCELENGINES 9 19 #define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4)) 20 21 /* 2 Accel units dedicated to services and */ 22 /* 1 Accel unit dedicated to Admin AE */ 23 #define ADF_4XXX_MAX_ACCELUNITS 3 24 25 /* Physical function fuses */ 26 #define ADF_4XXX_FUSECTL0_OFFSET (0x2C8) 27 #define ADF_4XXX_FUSECTL1_OFFSET (0x2CC) 28 #define ADF_4XXX_FUSECTL2_OFFSET (0x2D0) 29 #define ADF_4XXX_FUSECTL3_OFFSET (0x2D4) 30 #define ADF_4XXX_FUSECTL4_OFFSET (0x2D8) 31 #define ADF_4XXX_FUSECTL5_OFFSET (0x2DC) 32 33 #define ADF_4XXX_ACCELERATORS_MASK (0x1) 34 #define ADF_4XXX_ACCELENGINES_MASK (0x1FF) 35 #define ADF_4XXX_ADMIN_AE_MASK (0x100) 36 37 #define ADF_4XXX_ETR_MAX_BANKS 64 38 39 /* MSIX interrupt */ 40 #define ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET (0x41A040) 41 #define ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET (0x41A044) 42 #define ADF_4XXX_SMIAPF_MASK_OFFSET (0x41A084) 43 #define ADF_4XXX_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i)*0x04)) 44 45 /* Bank and ring configuration */ 46 #define ADF_4XXX_NUM_RINGS_PER_BANK 2 47 48 /* Error source registers */ 49 #define ADF_4XXX_ERRSOU0 (0x41A200) 50 #define ADF_4XXX_ERRSOU1 (0x41A204) 51 #define ADF_4XXX_ERRSOU2 (0x41A208) 52 #define ADF_4XXX_ERRSOU3 (0x41A20C) 53 54 /* Error source mask registers */ 55 #define ADF_4XXX_ERRMSK0 (0x41A210) 56 #define ADF_4XXX_ERRMSK1 (0x41A214) 57 #define ADF_4XXX_ERRMSK2 (0x41A218) 58 #define ADF_4XXX_ERRMSK3 (0x41A21C) 59 60 #define ADF_4XXX_VFLNOTIFY BIT(7) 61 #define ADF_4XXX_DEF_ASYM_MASK 0x1 62 63 /* Arbiter configuration */ 64 #define ADF_4XXX_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 65 #define ADF_4XXX_ARB_OFFSET (0x0) 66 #define ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET (0x400) 67 68 /* Admin Interface Reg Offset */ 69 #define ADF_4XXX_ADMINMSGUR_OFFSET (0x500574) 70 #define ADF_4XXX_ADMINMSGLR_OFFSET (0x500578) 71 #define ADF_4XXX_MAILBOX_BASE_OFFSET (0x600970) 72 73 /* Power management */ 74 #define ADF_4XXX_PM_POLL_DELAY_US 20 75 #define ADF_4XXX_PM_POLL_TIMEOUT_US USEC_PER_SEC 76 #define ADF_4XXX_PM_STATUS (0x50A00C) 77 #define ADF_4XXX_PM_INTERRUPT (0x50A028) 78 #define ADF_4XXX_PM_DRV_ACTIVE BIT(20) 79 #define ADF_4XXX_PM_INIT_STATE BIT(21) 80 /* Power management source in ERRSOU2 and ERRMSK2 */ 81 #define ADF_4XXX_PM_SOU BIT(18) 82 83 /* Firmware Binaries */ 84 #define ADF_4XXX_FW "qat_4xxx_fw" 85 #define ADF_4XXX_MMP "qat_4xxx_mmp_fw" 86 #define ADF_4XXX_DC_OBJ "qat_4xxx_dc.bin" 87 #define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin" 88 #define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin" 89 #define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin" 90 91 /* Only 3 types of images can be loaded including the admin image */ 92 #define ADF_4XXX_MAX_OBJ 3 93 94 #define ADF_4XXX_AE_FREQ (1000 * 1000000) 95 #define ADF_4XXX_KPT_COUNTER_FREQ (100 * 1000000) 96 97 #define ADF_4XXX_MIN_AE_FREQ (9 * 1000000) 98 #define ADF_4XXX_MAX_AE_FREQ (1100 * 1000000) 99 100 /* qat_4xxx fuse bits are different from old GENs, redefine them */ 101 enum icp_qat_4xxx_slice_mask { 102 ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0), 103 ICP_ACCEL_4XXX_MASK_AUTH_SLICE = BIT(1), 104 ICP_ACCEL_4XXX_MASK_PKE_SLICE = BIT(2), 105 ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3), 106 ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4), 107 ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5), 108 ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6), 109 }; 110 111 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id); 112 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data); 113 114 #endif 115