1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_C3XXX_HW_DATA_H_ 4 #define ADF_C3XXX_HW_DATA_H_ 5 6 /* PCIe configuration space */ 7 #define ADF_C3XXX_PMISC_BAR 0 8 #define ADF_C3XXX_ETR_BAR 1 9 #define ADF_C3XXX_RX_RINGS_OFFSET 8 10 #define ADF_C3XXX_TX_RINGS_MASK 0xFF 11 #define ADF_C3XXX_MAX_ACCELERATORS 3 12 #define ADF_C3XXX_MAX_ACCELENGINES 6 13 #define ADF_C3XXX_ACCELERATORS_REG_OFFSET 16 14 #define ADF_C3XXX_ACCELERATORS_MASK 0x7 15 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F 16 #define ADF_C3XXX_ETR_MAX_BANKS 16 17 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 18 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 19 #define ADF_C3XXX_SMIA0_MASK 0xFFFF 20 #define ADF_C3XXX_SMIA1_MASK 0x1 21 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC 22 #define ADF_C3XXX_POWERGATE_PKE BIT(24) 23 #define ADF_C3XXX_POWERGATE_CY BIT(23) 24 25 /* Error detection and correction */ 26 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 27 #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 28 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28) 29 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 30 #define ADF_C3XXX_UERRSSMSH(i) (i * 0x4000 + 0x18) 31 #define ADF_C3XXX_CERRSSMSH(i) (i * 0x4000 + 0x10) 32 #define ADF_C3XXX_ERRSSMSH_EN BIT(3) 33 #define ADF_C3XXX_ERRSOU3 (0x3A000 + 0x0C) 34 #define ADF_C3XXX_ERRSOU5 (0x3A000 + 0xD8) 35 36 /* BIT(2) enables the logging of push/pull data errors. */ 37 #define ADF_C3XXX_PPERR_EN (BIT(2)) 38 39 /* Mask for VF2PF interrupts */ 40 #define ADF_C3XXX_VF2PF1_16 (0xFFFF << 9) 41 #define ADF_C3XXX_ERRSOU3_VF2PF(errsou3) (((errsou3)&0x01FFFE00) >> 9) 42 #define ADF_C3XXX_ERRMSK3_VF2PF(vf_mask) (((vf_mask)&0xFFFF) << 9) 43 44 /* Masks for correctable error interrupts. */ 45 #define ADF_C3XXX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 46 #define ADF_C3XXX_ERRMSK1_CERR (BIT(8) | BIT(0)) 47 #define ADF_C3XXX_ERRMSK5_CERR (0) 48 49 /* Masks for uncorrectable error interrupts. */ 50 #define ADF_C3XXX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 51 #define ADF_C3XXX_ERRMSK1_UERR (BIT(9) | BIT(1)) 52 #define ADF_C3XXX_ERRMSK3_UERR \ 53 (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 54 #define ADF_C3XXX_ERRMSK5_UERR (BIT(16)) 55 56 /* RI CPP control */ 57 #define ADF_C3XXX_RICPPINTCTL (0x3A000 + 0x110) 58 /* 59 * BIT(2) enables error detection and reporting on the RI Parity Error. 60 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 61 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 62 */ 63 #define ADF_C3XXX_RICPP_EN (BIT(2) | BIT(1) | BIT(0)) 64 65 /* TI CPP control */ 66 #define ADF_C3XXX_TICPPINTCTL (0x3A400 + 0x138) 67 /* 68 * BIT(3) enables error detection and reporting on the ETR Parity Error. 69 * BIT(2) enables error detection and reporting on the TI Parity Error. 70 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 71 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 72 */ 73 #define ADF_C3XXX_TICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 74 75 /* CFC Uncorrectable Errors */ 76 #define ADF_C3XXX_CPP_CFC_ERR_CTRL (0x30000 + 0xC00) 77 /* 78 * BIT(1) enables interrupt. 79 * BIT(0) enables detecting and logging of push/pull data errors. 80 */ 81 #define ADF_C3XXX_CPP_CFC_UE (BIT(1) | BIT(0)) 82 83 #define ADF_C3XXX_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 84 /* Enabling PKE4-PKE0. */ 85 #define ADF_C3XXX_MMP_PWR_UP_MSK \ 86 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 87 88 /* CPM Uncorrectable Errors */ 89 #define ADF_C3XXX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 90 /* Disabling interrupts for correctable errors. */ 91 #define ADF_C3XXX_INTMASKSSM_UERR \ 92 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 93 94 /* MMP */ 95 /* BIT(3) enables correction. */ 96 #define ADF_C3XXX_CERRSSMMMP_EN (BIT(3)) 97 98 #define ADF_C3X_CLK_PER_SEC (343 * 1000000) 99 /* BIT(3) enables logging. */ 100 #define ADF_C3XXX_UERRSSMMMP_EN (BIT(3)) 101 102 #define ADF_C3XXX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 103 #define ADF_C3XXX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 104 105 /* Arbiter configuration */ 106 #define ADF_C3XXX_ARB_OFFSET 0x30000 107 #define ADF_C3XXX_ARB_WRK_2_SER_MAP_OFFSET 0x180 108 #define ADF_C3XXX_ARB_WQCFG_OFFSET 0x100 109 110 /* Admin Interface Reg Offset */ 111 #define ADF_C3XXX_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 112 #define ADF_C3XXX_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 113 #define ADF_C3XXX_MAILBOX_BASE_OFFSET 0x20970 114 115 /* Firmware Binary */ 116 #define ADF_C3XXX_FW "qat_c3xxx_fw" 117 #define ADF_C3XXX_MMP "qat_c3xxx_mmp_fw" 118 119 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data); 120 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data); 121 122 #define ADF_C3XXX_AE_FREQ (685 * 1000000) 123 #define ADF_C3XXX_MIN_AE_FREQ (320 * 1000000) 124 #define ADF_C3XXX_MAX_AE_FREQ (685 * 1000000) 125 126 #endif 127