1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_C4XXX_HW_DATA_H_ 4 #define ADF_C4XXX_HW_DATA_H_ 5 6 #include <adf_accel_devices.h> 7 8 /* PCIe configuration space */ 9 #define ADF_C4XXX_SRAM_BAR 0 10 #define ADF_C4XXX_PMISC_BAR 1 11 #define ADF_C4XXX_ETR_BAR 2 12 #define ADF_C4XXX_RX_RINGS_OFFSET 4 13 #define ADF_C4XXX_TX_RINGS_MASK 0xF 14 15 #define ADF_C4XXX_MAX_ACCELERATORS 12 16 #define ADF_C4XXX_MAX_ACCELUNITS 6 17 #define ADF_C4XXX_MAX_ACCELENGINES 32 18 #define ADF_C4XXX_ACCELERATORS_REG_OFFSET 16 19 20 /* Soft straps offsets */ 21 #define ADF_C4XXX_SOFTSTRAPPULL0_OFFSET (0x344) 22 #define ADF_C4XXX_SOFTSTRAPPULL1_OFFSET (0x348) 23 #define ADF_C4XXX_SOFTSTRAPPULL2_OFFSET (0x34C) 24 25 /* Physical function fuses offsets */ 26 #define ADF_C4XXX_FUSECTL0_OFFSET (0x350) 27 #define ADF_C4XXX_FUSECTL1_OFFSET (0x354) 28 #define ADF_C4XXX_FUSECTL2_OFFSET (0x358) 29 30 #define ADF_C4XXX_FUSE_PKE_MASK (0xFFF000) 31 #define ADF_C4XXX_FUSE_COMP_MASK (0x000FFF) 32 #define ADF_C4XXX_FUSE_PROD_SKU_MASK BIT(31) 33 34 #define ADF_C4XXX_LEGFUSE_BASE_SKU_MASK (BIT(2) | BIT(3)) 35 36 #define ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS BIT(12) 37 #define ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS BIT(13) 38 #define ADF_C4XXX_FUSE_DISABLE_INLINE_MASK \ 39 (ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS | \ 40 ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS) 41 42 #define ADF_C4XXX_ACCELERATORS_MASK (0xFFF) 43 #define ADF_C4XXX_ACCELENGINES_MASK (0xFFFFFFFF) 44 45 #define ADF_C4XXX_ETR_MAX_BANKS 128 46 #define ADF_C4XXX_SMIAPF0_MASK_OFFSET (0x60000 + 0x20) 47 #define ADF_C4XXX_SMIAPF1_MASK_OFFSET (0x60000 + 0x24) 48 #define ADF_C4XXX_SMIAPF2_MASK_OFFSET (0x60000 + 0x28) 49 #define ADF_C4XXX_SMIAPF3_MASK_OFFSET (0x60000 + 0x2C) 50 #define ADF_C4XXX_SMIAPF4_MASK_OFFSET (0x60000 + 0x30) 51 #define ADF_C4XXX_SMIA0_MASK 0xFFFFFFFF 52 #define ADF_C4XXX_SMIA1_MASK 0xFFFFFFFF 53 #define ADF_C4XXX_SMIA2_MASK 0xFFFFFFFF 54 #define ADF_C4XXX_SMIA3_MASK 0xFFFFFFFF 55 #define ADF_C4XXX_SMIA4_MASK 0x1 56 /* Bank and ring configuration */ 57 #define ADF_C4XXX_NUM_RINGS_PER_BANK 8 58 /* Error detection and correction */ 59 #define ADF_C4XXX_AE_CTX_ENABLES(i) (0x40818 + ((i)*0x1000)) 60 #define ADF_C4XXX_AE_MISC_CONTROL(i) (0x40960 + ((i)*0x1000)) 61 #define ADF_C4XXX_ENABLE_AE_ECC_ERR BIT(28) 62 #define ADF_C4XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 63 #define ADF_C4XXX_UERRSSMSH(i) (0x18 + ((i)*0x4000)) 64 #define ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK (~BIT(0) ^ BIT(16)) 65 #define ADF_C4XXX_CERRSSMSH(i) (0x10 + ((i)*0x4000)) 66 #define ADF_C4XXX_CERRSSMSH_INTS_CLEAR_MASK (~BIT(0)) 67 #define ADF_C4XXX_ERRSSMSH_EN BIT(3) 68 #define ADF_C4XXX_PF2VF_OFFSET(i) (0x62400 + ((i)*0x04)) 69 #define ADF_C4XXX_VINTMSK_OFFSET(i) (0x62200 + ((i)*0x04)) 70 71 /* Doorbell interrupt detection in ERRSOU11 */ 72 #define ADF_C4XXX_DOORBELL_INT_SRC BIT(10) 73 74 /* Doorbell interrupt register definitions */ 75 #define ADF_C4XXX_ETH_DOORBELL_INT (0x60108) 76 77 /* Clear <3:0> in ETH_DOORBELL_INT */ 78 #define ADF_C4XXX_ETH_DOORBELL_MASK 0xF 79 80 /* Doorbell register definitions */ 81 #define ADF_C4XXX_NUM_ETH_DOORBELL_REGS (4) 82 #define ADF_C4XXX_ETH_DOORBELL(i) (0x61500 + ((i)*0x04)) 83 84 /* Error source registers */ 85 #define ADF_C4XXX_ERRSOU0 (0x60000 + 0x40) 86 #define ADF_C4XXX_ERRSOU1 (0x60000 + 0x44) 87 #define ADF_C4XXX_ERRSOU2 (0x60000 + 0x48) 88 #define ADF_C4XXX_ERRSOU3 (0x60000 + 0x4C) 89 #define ADF_C4XXX_ERRSOU4 (0x60000 + 0x50) 90 #define ADF_C4XXX_ERRSOU5 (0x60000 + 0x54) 91 #define ADF_C4XXX_ERRSOU6 (0x60000 + 0x58) 92 #define ADF_C4XXX_ERRSOU7 (0x60000 + 0x5C) 93 #define ADF_C4XXX_ERRSOU8 (0x60000 + 0x60) 94 #define ADF_C4XXX_ERRSOU9 (0x60000 + 0x64) 95 #define ADF_C4XXX_ERRSOU10 (0x60000 + 0x68) 96 #define ADF_C4XXX_ERRSOU11 (0x60000 + 0x6C) 97 98 /* Error source mask registers */ 99 #define ADF_C4XXX_ERRMSK0 (0x60000 + 0xC0) 100 #define ADF_C4XXX_ERRMSK1 (0x60000 + 0xC4) 101 #define ADF_C4XXX_ERRMSK2 (0x60000 + 0xC8) 102 #define ADF_C4XXX_ERRMSK3 (0x60000 + 0xCC) 103 #define ADF_C4XXX_ERRMSK4 (0x60000 + 0xD0) 104 #define ADF_C4XXX_ERRMSK5 (0x60000 + 0xD4) 105 #define ADF_C4XXX_ERRMSK6 (0x60000 + 0xD8) 106 #define ADF_C4XXX_ERRMSK7 (0x60000 + 0xDC) 107 #define ADF_C4XXX_ERRMSK8 (0x60000 + 0xE0) 108 #define ADF_C4XXX_ERRMSK9 (0x60000 + 0xE4) 109 #define ADF_C4XXX_ERRMSK10 (0x60000 + 0xE8) 110 #define ADF_C4XXX_ERRMSK11 (0x60000 + 0xEC) 111 112 /* Slice Hang enabling related registers */ 113 #define ADF_C4XXX_SHINTMASKSSM (0x1018) 114 #define ADF_C4XXX_SSMWDTL (0x54) 115 #define ADF_C4XXX_SSMWDTH (0x5C) 116 #define ADF_C4XXX_SSMWDTPKEL (0x58) 117 #define ADF_C4XXX_SSMWDTPKEH (0x60) 118 #define ADF_C4XXX_SLICEHANGSTATUS (0x4C) 119 #define ADF_C4XXX_IASLICEHANGSTATUS (0x50) 120 121 #define ADF_C4XXX_SHINTMASKSSM_VAL (0x00) 122 123 /* Set default value of Slice Hang watchdogs in clock cycles */ 124 #define ADF_C4XXX_SSM_WDT_64BIT_DEFAULT_VALUE 0x3D0900 125 #define ADF_C4XXX_SSM_WDT_PKE_64BIT_DEFAULT_VALUE 0x3000000 126 127 /* Return interrupt accelerator source mask */ 128 #define ADF_C4XXX_IRQ_SRC_MASK(accel) (1 << (accel)) 129 130 /* Return address of SHINTMASKSSM register for a given accelerator */ 131 #define ADF_C4XXX_SHINTMASKSSM_OFFSET(accel) \ 132 (ADF_C4XXX_SHINTMASKSSM + ((accel)*0x4000)) 133 134 /* Return address of SSMWDTL register for a given accelerator */ 135 #define ADF_C4XXX_SSMWDTL_OFFSET(accel) (ADF_C4XXX_SSMWDTL + ((accel)*0x4000)) 136 137 /* Return address of SSMWDTH register for a given accelerator */ 138 #define ADF_C4XXX_SSMWDTH_OFFSET(accel) (ADF_C4XXX_SSMWDTH + ((accel)*0x4000)) 139 140 /* Return address of SSMWDTPKEL register for a given accelerator */ 141 #define ADF_C4XXX_SSMWDTPKEL_OFFSET(accel) \ 142 (ADF_C4XXX_SSMWDTPKEL + ((accel)*0x4000)) 143 144 /* Return address of SSMWDTPKEH register for a given accelerator */ 145 #define ADF_C4XXX_SSMWDTPKEH_OFFSET(accel) \ 146 (ADF_C4XXX_SSMWDTPKEH + ((accel)*0x4000)) 147 148 /* Return address of SLICEHANGSTATUS register for a given accelerator */ 149 #define ADF_C4XXX_SLICEHANGSTATUS_OFFSET(accel) \ 150 (ADF_C4XXX_SLICEHANGSTATUS + ((accel)*0x4000)) 151 152 /* Return address of IASLICEHANGSTATUS register for a given accelerator */ 153 #define ADF_C4XXX_IASLICEHANGSTATUS_OFFSET(accel) \ 154 (ADF_C4XXX_IASLICEHANGSTATUS + ((accel)*0x4000)) 155 156 /* RAS enabling related registers */ 157 #define ADF_C4XXX_SSMFEATREN (0x2010) 158 #define ADF_C4XXX_SSMSOFTERRORPARITY_MASK (0x1008) 159 160 /* Return address of SSMFEATREN register for given accel */ 161 #define ADF_C4XXX_GET_SSMFEATREN_OFFSET(accel) \ 162 (ADF_C4XXX_SSMFEATREN + ((accel)*0x4000)) 163 164 /* Return address of SSMSOFTERRORPARITY_MASK register for given accel */ 165 #define ADF_C4XXX_GET_SSMSOFTERRORPARITY_MASK_OFFSET(accel) \ 166 (ADF_C4XXX_SSMSOFTERRORPARITY_MASK + ((accel)*0x4000)) 167 168 /* RAS enabling related registers values to be written */ 169 #define ADF_C4XXX_SSMFEATREN_VAL (0xFD) 170 #define ADF_C4XXX_SSMSOFTERRORPARITY_MASK_VAL (0x00) 171 172 /* Enable VF2PF interrupt in ERRMSK4 to ERRMSK7 */ 173 #define ADF_C4XXX_VF2PF0_31 0x0 174 #define ADF_C4XXX_VF2PF32_63 0x0 175 #define ADF_C4XXX_VF2PF64_95 0x0 176 #define ADF_C4XXX_VF2PF96_127 0x0 177 178 /* AEx Correctable Error Mask in ERRMSK8 */ 179 #define ADF_C4XXX_ERRMSK8_COERR 0x0 180 #define ADF_C4XXX_ERRSOU8_MECORR_MASK BIT(0) 181 #define ADF_C4XXX_HI_ME_COR_ERRLOG (0x60104) 182 #define ADF_C4XXX_HI_ME_COR_ERRLOG_ENABLE (0x61600) 183 #define ADF_C4XXX_HI_ME_COR_ERRLOG_ENABLE_MASK (0xFFFFFFFF) 184 #define ADF_C4XXX_HI_ME_COR_ERRLOG_SIZE_IN_BITS (32) 185 186 /* Group of registers related to ERRSOU9 handling 187 * 188 * AEx Uncorrectable Error Mask in ERRMSK9 189 * CPP Command Parity Errors Mask in ERRMSK9 190 * RI Memory Parity Errors Mask in ERRMSK9 191 * TI Memory Parity Errors Mask in ERRMSK9 192 */ 193 #define ADF_C4XXX_ERRMSK9_IRQ_MASK 0x0 194 #define ADF_C4XXX_ME_UNCORR_ERROR BIT(0) 195 #define ADF_C4XXX_CPP_CMD_PAR_ERR BIT(1) 196 #define ADF_C4XXX_RI_MEM_PAR_ERR BIT(2) 197 #define ADF_C4XXX_TI_MEM_PAR_ERR BIT(3) 198 199 #define ADF_C4XXX_ERRSOU9_ERROR_MASK \ 200 (ADF_C4XXX_ME_UNCORR_ERROR | ADF_C4XXX_CPP_CMD_PAR_ERR | \ 201 ADF_C4XXX_RI_MEM_PAR_ERR | ADF_C4XXX_TI_MEM_PAR_ERR) 202 203 #define ADF_C4XXX_HI_ME_UNCERR_LOG (0x60100) 204 #define ADF_C4XXX_HI_ME_UNCERR_LOG_ENABLE (0x61608) 205 #define ADF_C4XXX_HI_ME_UNCERR_LOG_ENABLE_MASK (0xFFFFFFFF) 206 #define ADF_C4XXX_HI_ME_UNCOR_ERRLOG_BITS (32) 207 208 /* HI CPP Agents Command parity Error Log 209 * CSR name: hicppagentcmdparerrlog 210 */ 211 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG (0x6010C) 212 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG_ENABLE (0x61604) 213 #define ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG_ENABLE_MASK (0xFFFFFFFF) 214 #define ADF_C4XXX_TI_CMD_PAR_ERR BIT(0) 215 #define ADF_C4XXX_RI_CMD_PAR_ERR BIT(1) 216 #define ADF_C4XXX_ICI_CMD_PAR_ERR BIT(2) 217 #define ADF_C4XXX_ICE_CMD_PAR_ERR BIT(3) 218 #define ADF_C4XXX_ARAM_CMD_PAR_ERR BIT(4) 219 #define ADF_C4XXX_CFC_CMD_PAR_ERR BIT(5) 220 #define ADF_C4XXX_SSM_CMD_PAR_ERR(value) (((u32)(value) >> 6) & 0xFFF) 221 222 /* RI Memory Parity Error Status Register 223 * CSR name: rimem_parerr_sts 224 */ 225 #define ADF_C4XXX_RI_MEM_PAR_ERR_STS (0x61610) 226 #define ADF_C4XXX_RI_MEM_PAR_ERR_EN0 (0x61614) 227 #define ADF_C4XXX_RI_MEM_PAR_ERR_FERR (0x61618) 228 #define ADF_C4XXX_RI_MEM_PAR_ERR_EN0_MASK (0x7FFFFF) 229 #define ADF_C4XXX_RI_MEM_MSIX_TBL_INT_MASK (BIT(22)) 230 #define ADF_C4XXX_RI_MEM_PAR_ERR_STS_MASK \ 231 (ADF_C4XXX_RI_MEM_PAR_ERR_EN0_MASK ^ ADF_C4XXX_RI_MEM_MSIX_TBL_INT_MASK) 232 233 /* TI Memory Parity Error Status Register 234 * CSR name: ti_mem_par_err_sts0, ti_mem_par_err_sts1 235 */ 236 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS0 (0x68604) 237 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN0 (0x68608) 238 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN0_MASK (0xFFFFFFFF) 239 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS1 (0x68610) 240 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN1 (0x68614) 241 #define ADF_C4XXX_TI_MEM_PAR_ERR_EN1_MASK (0x7FFFF) 242 #define ADF_C4XXX_TI_MEM_PAR_ERR_STS1_MASK (ADF_C4XXX_TI_MEM_PAR_ERR_EN1_MASK) 243 #define ADF_C4XXX_TI_MEM_PAR_ERR_FIRST_ERROR (0x68618) 244 245 /* Enable SSM<11:0> in ERRMSK10 */ 246 #define ADF_C4XXX_ERRMSK10_SSM_ERR 0x0 247 #define ADF_C4XXX_ERRSOU10_RAS_MASK 0x1FFF 248 #define ADF_C4XXX_ERRSOU10_PUSHPULL_MASK BIT(12) 249 250 #define ADF_C4XXX_IASTATSSM_UERRSSMSH_MASK BIT(0) 251 #define ADF_C4XXX_IASTATSSM_CERRSSMSH_MASK BIT(1) 252 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP0_MASK BIT(2) 253 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP0_MASK BIT(3) 254 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP1_MASK BIT(4) 255 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP1_MASK BIT(5) 256 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP2_MASK BIT(6) 257 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP2_MASK BIT(7) 258 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP3_MASK BIT(8) 259 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP3_MASK BIT(9) 260 #define ADF_C4XXX_IASTATSSM_UERRSSMMMP4_MASK BIT(10) 261 #define ADF_C4XXX_IASTATSSM_CERRSSMMMP4_MASK BIT(11) 262 #define ADF_C4XXX_IASTATSSM_PPERR_MASK BIT(12) 263 #define ADF_C4XXX_IASTATSSM_SPPPAR_ERR_MASK BIT(14) 264 #define ADF_C4XXX_IASTATSSM_CPPPAR_ERR_MASK BIT(15) 265 #define ADF_C4XXX_IASTATSSM_RFPAR_ERR_MASK BIT(16) 266 267 #define ADF_C4XXX_IAINTSTATSSM(i) ((i)*0x4000 + 0x206C) 268 #define ADF_C4XXX_IASTATSSM_MASK 0x1DFFF 269 #define ADF_C4XXX_IASTATSSM_CLR_MASK 0xFFFE2000 270 #define ADF_C4XXX_IASTATSSM_BITS 17 271 #define ADF_C4XXX_IASTATSSM_SLICE_HANG_ERR_BIT 13 272 #define ADF_C4XXX_IASTATSSM_SPP_PAR_ERR_BIT 14 273 #define ADF_C4XXX_IASTATSSM_CPP_PAR_ERR_BIT 15 274 275 /* Accelerator Interrupt Mask (SSM) 276 * CSR name: intmaskssm[0..11] 277 * Returns address of INTMASKSSM register for a given accel. 278 * This register is used to unmask SSM interrupts to host 279 * reported by ERRSOU10. 280 */ 281 #define ADF_C4XXX_GET_INTMASKSSM_OFFSET(accel) ((accel)*0x4000) 282 283 /* Base address of SPP parity error mask register 284 * CSR name: sppparerrmsk[0..11] 285 */ 286 #define ADF_C4XXX_SPPPARERRMSK_OFFSET (0x2028) 287 288 /* Returns address of SPPPARERRMSK register for a given accel. 289 * This register is used to unmask SPP parity errors interrupts to host 290 * reported by ERRSOU10. 291 */ 292 #define ADF_C4XXX_GET_SPPPARERRMSK_OFFSET(accel) \ 293 (ADF_C4XXX_SPPPARERRMSK_OFFSET + ((accel)*0x4000)) 294 295 #define ADF_C4XXX_EXPRPSSMCPR0(i) ((i)*0x4000 + 0x400) 296 #define ADF_C4XXX_EXPRPSSMXLT0(i) ((i)*0x4000 + 0x500) 297 #define ADF_C4XXX_EXPRPSSMCPR1(i) ((i)*0x4000 + 0x1400) 298 #define ADF_C4XXX_EXPRPSSMXLT1(i) ((i)*0x4000 + 0x1500) 299 300 #define ADF_C4XXX_EXPRPSSM_FATAL_MASK BIT(2) 301 #define ADF_C4XXX_EXPRPSSM_SOFT_MASK BIT(3) 302 303 #define ADF_C4XXX_PPERR_INTS_CLEAR_MASK BIT(0) 304 305 #define ADF_C4XXX_SSMSOFTERRORPARITY(i) ((i)*0x4000 + 0x1000) 306 #define ADF_C4XXX_SSMCPPERR(i) ((i)*0x4000 + 0x2030) 307 308 /* ethernet doorbell in ERRMSK11 309 * timisc in ERRMSK11 310 * rimisc in ERRMSK11 311 * ppmiscerr in ERRMSK11 312 * cerr in ERRMSK11 313 * uerr in ERRMSK11 314 * ici in ERRMSK11 315 * ice in ERRMSK11 316 */ 317 #define ADF_C4XXX_ERRMSK11_ERR 0x0 318 /* 319 * BIT(7) disables ICI interrupt 320 * BIT(8) disables ICE interrupt 321 */ 322 #define ADF_C4XXX_ERRMSK11_ERR_DISABLE_ICI_ICE_INTR (BIT(7) | BIT(8)) 323 324 /* RAS mask for errors reported by ERRSOU11 */ 325 #define ADF_C4XXX_ERRSOU11_ERROR_MASK (0x1FF) 326 #define ADF_C4XXX_TI_MISC BIT(0) 327 #define ADF_C4XXX_RI_PUSH_PULL_PAR_ERR BIT(1) 328 #define ADF_C4XXX_TI_PUSH_PULL_PAR_ERR BIT(2) 329 #define ADF_C4XXX_ARAM_CORR_ERR BIT(3) 330 #define ADF_C4XXX_ARAM_UNCORR_ERR BIT(4) 331 #define ADF_C4XXX_TI_PULL_PAR_ERR BIT(5) 332 #define ADF_C4XXX_RI_PUSH_PAR_ERR BIT(6) 333 #define ADF_C4XXX_INLINE_INGRESS_INTR BIT(7) 334 #define ADF_C4XXX_INLINE_EGRESS_INTR BIT(8) 335 336 /* TI Misc error status */ 337 #define ADF_C4XXX_TI_MISC_STS (0x6854C) 338 #define ADF_C4XXX_TI_MISC_ERR_MASK (BIT(0)) 339 #define ADF_C4XXX_GET_TI_MISC_ERR_TYPE(status) ((status) >> 1 & 0x3) 340 #define ADF_C4XXX_TI_BME_RESP_ORDER_ERR (0x1) 341 #define ADF_C4XXX_TI_RESP_ORDER_ERR (0x2) 342 343 /* RI CPP interface status register */ 344 #define ADF_C4XXX_RI_CPP_INT_STS (0x61118) 345 #define ADF_C4XXX_RI_CPP_INT_STS_PUSH_ERR BIT(0) 346 #define ADF_C4XXX_RI_CPP_INT_STS_PULL_ERR BIT(1) 347 #define ADF_C4XXX_RI_CPP_INT_STS_PUSH_DATA_PAR_ERR BIT(2) 348 #define ADF_C4XXX_GET_CPP_BUS_FROM_STS(status) ((status) >> 31 & 0x1) 349 350 /* RI CPP interface control register. */ 351 #define ADF_C4XXX_RICPPINTCTL (0x61000 + 0x004) 352 /* 353 * BIT(3) enables error parity checking on CPP. 354 * BIT(2) enables error detection and reporting on the RI Parity Error. 355 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 356 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 357 */ 358 #define ADF_C4XXX_RICPP_EN (BIT(3) | BIT(2) | BIT(1) | BIT(0)) 359 360 /* TI CPP interface status register */ 361 #define ADF_C4XXX_TI_CPP_INT_STS (0x6853C) 362 #define ADF_C4XXX_TI_CPP_INT_STS_PUSH_ERR BIT(0) 363 #define ADF_C4XXX_TI_CPP_INT_STS_PULL_ERR BIT(1) 364 #define ADF_C4XXX_TI_CPP_INT_STS_PUSH_DATA_PAR_ERR BIT(2) 365 366 #define ADF_C4XXX_TICPPINTCTL (0x68000 + 0x538) 367 /* 368 * BIT(4) enables 'stop and scream' feature for TI RF. 369 * BIT(3) enables CPP command and pull data parity checking. 370 * BIT(2) enables data parity error detection and reporting on the TI CPP 371 * Pull interface. 372 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 373 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 374 */ 375 #define ADF_C4XXX_TICPP_EN (BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)) 376 377 /* CPP error control and logging register */ 378 #define ADF_C4XXX_CPP_CFC_ERR_CTRL (0x70000 + 0xC00) 379 380 /* 381 * BIT(1) enables generation of irqs to the PCIe endpoint 382 * for the errors specified in CPP_CFC_ERR_STATUS 383 * BIT(0) enables detecting and logging of push/pull data errors. 384 */ 385 #define ADF_C4XXX_CPP_CFC_UE (BIT(1) | BIT(0)) 386 387 /* ARAM error interrupt enable registers */ 388 #define ADF_C4XXX_ARAMCERR (0x101700) 389 #define ADF_C4XXX_ARAMUERR (0x101704) 390 #define ADF_C4XXX_CPPMEMTGTERR (0x101710) 391 #define ADF_C4XXX_ARAM_CORR_ERR_MASK (BIT(0)) 392 #define ADF_C4XXX_ARAM_UNCORR_ERR_MASK (BIT(0)) 393 #define ADF_C4XXX_CLEAR_CSR_BIT(csr, bit_num) ((csr) &= ~(BIT(bit_num))) 394 395 /* ARAM correctable errors defined in ARAMCERR 396 * Bit<3> Enable fixing and logging correctable errors by hardware. 397 * Bit<26> Enable interrupt to host for ARAM correctable errors. 398 */ 399 #define ADF_C4XXX_ARAM_CERR (BIT(3) | BIT(26)) 400 401 /* ARAM correctable errors defined in ARAMUERR 402 * Bit<3> Enable detection and logging of ARAM uncorrectable errors. 403 * Bit<19> Enable interrupt to host for ARAM uncorrectable errors. 404 */ 405 #define ADF_C4XXX_ARAM_UERR (BIT(3) | BIT(19)) 406 407 /* Misc memory target error registers in CPPMEMTGTERR 408 * Bit<2> CPP memory push/pull error enable bit 409 * Bit<7> RI push/pull error enable bit 410 * Bit<8> ARAM pull data parity check bit 411 * Bit<9> RAS push error enable bit 412 */ 413 #define ADF_C4XXX_TGT_UERR (BIT(9) | BIT(8) | BIT(7) | BIT(2)) 414 415 /* Slice power down register */ 416 #define ADF_C4XXX_SLICEPWRDOWN(i) (((i)*0x4000) + 0x2C) 417 418 /* Enabling PKE0 to PKE4. */ 419 #define ADF_C4XXX_MMP_PWR_UP_MSK \ 420 (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) 421 422 /* Error registers for MMP0-MMP4. */ 423 #define ADF_C4XXX_MAX_MMP (5) 424 425 #define ADF_C4XXX_MMP_BASE(i) ((i)*0x1000 % 0x3800) 426 #define ADF_C4XXX_CERRSSMMMP(i, n) ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x380) 427 #define ADF_C4XXX_UERRSSMMMP(i, n) ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x388) 428 #define ADF_C4XXX_UERRSSMMMPAD(i, n) \ 429 ((i)*0x4000 + ADF_C4XXX_MMP_BASE(n) + 0x38C) 430 #define ADF_C4XXX_INTMASKSSM(i) ((i)*0x4000 + 0x0) 431 432 #define ADF_C4XXX_UERRSSMMMP_INTS_CLEAR_MASK ((BIT(16) | BIT(0))) 433 #define ADF_C4XXX_CERRSSMMMP_INTS_CLEAR_MASK BIT(0) 434 435 /* Bit<3> enables logging of MMP uncorrectable errors */ 436 #define ADF_C4XXX_UERRSSMMMP_EN BIT(3) 437 438 /* Bit<3> enables logging of MMP correctable errors */ 439 #define ADF_C4XXX_CERRSSMMMP_EN BIT(3) 440 441 #define ADF_C4XXX_ERRMSK_VF2PF_OFFSET(i) (ADF_C4XXX_ERRMSK4 + ((i)*0x04)) 442 443 /* RAM base address registers */ 444 #define ADF_C4XXX_RAMBASEADDRHI 0x71020 445 446 #define ADF_C4XXX_NUM_ARAM_ENTRIES 8 447 448 /* ARAM region sizes in bytes */ 449 #define ADF_C4XXX_1MB_SIZE (1024 * 1024) 450 #define ADF_C4XXX_2MB_ARAM_SIZE (2 * ADF_C4XXX_1MB_SIZE) 451 #define ADF_C4XXX_4MB_ARAM_SIZE (4 * ADF_C4XXX_1MB_SIZE) 452 #define ADF_C4XXX_DEFAULT_MMP_REGION_SIZE (1024 * 256) 453 #define ADF_C4XXX_DEFAULT_SKM_REGION_SIZE (1024 * 256) 454 #define ADF_C4XXX_AU_COMPR_INTERM_SIZE (1024 * 128 * 2 * 2) 455 #define ADF_C4XXX_DEF_ASYM_MASK 0x1 456 457 /* Arbiter configuration */ 458 #define ADF_C4XXX_ARB_OFFSET 0x80000 459 #define ADF_C4XXX_ARB_WQCFG_OFFSET 0x200 460 461 /* Admin Interface Reg Offset */ 462 #define ADF_C4XXX_ADMINMSGUR_OFFSET (0x60000 + 0x8000 + 0x400 + 0x174) 463 #define ADF_C4XXX_ADMINMSGLR_OFFSET (0x60000 + 0x8000 + 0x400 + 0x178) 464 #define ADF_C4XXX_MAILBOX_BASE_OFFSET 0x40970 465 466 /* AE to function mapping */ 467 #define ADF_C4XXX_AE2FUNC_REG_PER_AE 8 468 #define ADF_C4XXX_AE2FUNC_MAP_OFFSET 0x68800 469 #define ADF_C4XXX_AE2FUNC_MAP_REG_SIZE 4 470 #define ADF_C4XXX_AE2FUNC_MAP_VALID BIT(8) 471 472 /* Enable each of the units on the chip */ 473 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC 0x7096C 474 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_DISABLE_ALL 0x0 475 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ICE_ENABLE BIT(4) 476 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ICI_ENABLE BIT(3) 477 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_ARAM BIT(2) 478 479 /* Clock is fully sets up after some delay */ 480 #define ADF_C4XXX_GLOBAL_CLK_ENABLE_GENERIC_RESTART_DELAY 10 481 #define ADF_C4XXX_GLOBAL_CLK_RESTART_LOOP 10 482 483 /* Reset each of the PPC units on the chip */ 484 #define ADF_C4XXX_IXP_RESET_GENERIC 0x70940 485 #define ADF_C4XXX_IXP_RESET_GENERIC_OUT_OF_RESET_TRIGGER 0x0 486 #define ADF_C4XXX_IXP_RESET_GENERIC_INLINE_INGRESS BIT(4) 487 #define ADF_C4XXX_IXP_RESET_GENERIC_INLINE_EGRESS BIT(3) 488 #define ADF_C4XXX_IXP_RESET_GENERIC_ARAM BIT(2) 489 490 /* Default accel unit configuration */ 491 #define ADF_C4XXX_NUM_CY_AU \ 492 { \ 493 [DEV_SKU_1] = 4, [DEV_SKU_1_CY] = 6, [DEV_SKU_2] = 3, \ 494 [DEV_SKU_2_CY] = 4, [DEV_SKU_3] = 1, [DEV_SKU_3_CY] = 2, \ 495 [DEV_SKU_UNKNOWN] = 0 \ 496 } 497 #define ADF_C4XXX_NUM_DC_AU \ 498 { \ 499 [DEV_SKU_1] = 2, [DEV_SKU_1_CY] = 0, [DEV_SKU_2] = 1, \ 500 [DEV_SKU_2_CY] = 0, [DEV_SKU_3] = 1, [DEV_SKU_3_CY] = 0, \ 501 [DEV_SKU_UNKNOWN] = 0 \ 502 } 503 504 #define ADF_C4XXX_NUM_ACCEL_PER_AU 2 505 #define ADF_C4XXX_NUM_INLINE_AU \ 506 { \ 507 [DEV_SKU_1] = 0, [DEV_SKU_1_CY] = 0, [DEV_SKU_2] = 0, \ 508 [DEV_SKU_2_CY] = 0, [DEV_SKU_3] = 0, [DEV_SKU_3_CY] = 0, \ 509 [DEV_SKU_UNKNOWN] = 0 \ 510 } 511 #define ADF_C4XXX_6_AE 6 512 #define ADF_C4XXX_4_AE 4 513 #define ADF_C4XXX_100 100 514 #define ADF_C4XXX_ROUND_LIMIT 5 515 #define ADF_C4XXX_PERCENTAGE "%" 516 517 #define ADF_C4XXX_ARB_CY 0x12222222 518 #define ADF_C4XXX_ARB_DC 0x00000888 519 520 /* Default accel firmware maximal object*/ 521 #define ADF_C4XXX_MAX_OBJ 4 522 523 /* Default 4 partitions for services */ 524 #define ADF_C4XXX_PART_ASYM 0 525 #define ADF_C4XXX_PART_SYM 1 526 #define ADF_C4XXX_PART_UNUSED 2 527 #define ADF_C4XXX_PART_DC 3 528 #define ADF_C4XXX_PARTS_PER_GRP 16 529 530 #define ADF_C4XXX_PARTITION_LUT_OFFSET 0x81000 531 #define ADF_C4XXX_WRKTHD2PARTMAP 0x82000 532 #define ADF_C4XXX_WQM_SIZE 0x4 533 534 #define ADF_C4XXX_DEFAULT_PARTITIONS \ 535 (ADF_C4XXX_PART_ASYM | ADF_C4XXX_PART_SYM << 8 | \ 536 ADF_C4XXX_PART_UNUSED << 16 | ADF_C4XXX_PART_DC << 24) 537 538 /* SKU configurations */ 539 #define ADF_C4XXX_HIGH_SKU_AES 32 540 #define ADF_C4XXX_MED_SKU_AES 24 541 #define ADF_C4XXX_LOW_SKU_AES 12 542 543 #define READ_CSR_WQM(csr_addr, csr_offset, index) \ 544 ADF_CSR_RD(csr_addr, (csr_offset) + ((index)*ADF_C4XXX_WQM_SIZE)) 545 546 #define WRITE_CSR_WQM(csr_addr, csr_offset, index, value) \ 547 ADF_CSR_WR(csr_addr, (csr_offset) + ((index)*ADF_C4XXX_WQM_SIZE), value) 548 549 /* Firmware Binary */ 550 #define ADF_C4XXX_FW "qat_c4xxx_fw" 551 #define ADF_C4XXX_MMP "qat_c4xxx_mmp_fw" 552 #define ADF_C4XXX_INLINE_OBJ "qat_c4xxx_inline.bin" 553 #define ADF_C4XXX_DC_OBJ "qat_c4xxx_dc.bin" 554 #define ADF_C4XXX_CY_OBJ "qat_c4xxx_cy.bin" 555 #define ADF_C4XXX_SYM_OBJ "qat_c4xxx_sym.bin" 556 557 void adf_init_hw_data_c4xxx(struct adf_hw_device_data *hw_data); 558 void adf_clean_hw_data_c4xxx(struct adf_hw_device_data *hw_data); 559 int adf_init_arb_c4xxx(struct adf_accel_dev *accel_dev); 560 void adf_exit_arb_c4xxx(struct adf_accel_dev *accel_dev); 561 562 #define ADF_C4XXX_AE_FREQ (800 * 1000000) 563 #define ADF_C4XXX_MIN_AE_FREQ (571 * 1000000) 564 #define ADF_C4XXX_MAX_AE_FREQ (800 * 1000000) 565 566 int c4xxx_init_ae_config(struct adf_accel_dev *accel_dev); 567 void c4xxx_exit_ae_config(struct adf_accel_dev *accel_dev); 568 void remove_oid(struct adf_accel_dev *accel_dev, struct sysctl_oid *oid); 569 #endif 570