1 /**************************************************************************
2
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28
29 ***************************************************************************/
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/endian.h>
34
35 #include <dev/mii/mii.h>
36
37 #ifndef _CXGB_OSDEP_H_
38 #define _CXGB_OSDEP_H_
39
40 typedef char *caddr_t;
41 #include <dev/pci/cxgb/cxgb_version.h>
42 #include <dev/pci/cxgb/cxgb_config.h>
43 #include <sys/mbuf.h>
44 #include <sys/bus.h>
45
46 #include <netinet/in_systm.h>
47 #include <netinet/in.h>
48 #include <netinet/ip.h>
49
50 #include <sys/kthread.h>
51 #include <sys/workqueue.h>
52
53 #include <sys/atomic.h>
54
55 void pci_enable_busmaster(device_t dev);
56
57 struct cxgb_task
58 {
59 const char *name;
60 void (*func)(struct work *, void *);
61 struct workqueue *wq;
62 struct work w;
63 void *context;
64 };
65
66 void cxgb_make_task(void *);
67
68 void m_cljset(struct mbuf *m, void *cl, int type);
69
70 #define mtx kmutex_t
71 #define mtx_init(a, b, c, d) { mutex_init(a, MUTEX_DEFAULT, IPL_HIGH) }
72 #define mtx_destroy(a)
73 #define mtx_lock(a) mutex_spin_enter(a)
74 #define mtx_unlock(a) mutex_spin_exit(a)
75 #define mtx_trylock(a) mutex_tryenter(a)
76 #define MA_OWNED 1
77 #define MA_NOTOWNED 0
78 #define mtx_assert(a, w)
79
80 #if 0
81 #define RT_LOCK_INIT(_rt) \
82 mtx_init(&(_rt)->rt_mtx, "rtentry", NULL, MTX_DEF | MTX_DUPOK)
83 #define RT_LOCK(_rt) mtx_lock(&(_rt)->rt_mtx)
84 #define RT_UNLOCK(_rt) mtx_unlock(&(_rt)->rt_mtx)
85 #define RT_LOCK_DESTROY(_rt) mtx_destroy(&(_rt)->rt_mtx)
86 #define RT_LOCK_ASSERT(_rt) mtx_assert(&(_rt)->rt_mtx, MA_OWNED)
87 #else
88 #define RT_LOCK_INIT(_rt)
89 #define RT_LOCK(_rt)
90 #define RT_UNLOCK(_rt)
91 #define RT_LOCK_DESTROY(_rt)
92 #define RT_LOCK_ASSERT(_rt)
93 #endif
94
95 #define RT_ADDREF(_rt) do { \
96 RT_LOCK_ASSERT(_rt); \
97 KASSERT((_rt)->rt_refcnt >= 0); \
98 (_rt)->rt_refcnt++; \
99 } while (0)
100 #define RT_REMREF(_rt) do { \
101 RT_LOCK_ASSERT(_rt); \
102 KASSERT((_rt)->rt_refcnt > 0); \
103 (_rt)->rt_refcnt--; \
104 } while (0)
105
106
107 #define EVL_VLID_MASK 0x0FFF
108
critical_enter(void)109 static __inline void critical_enter(void)
110 {
111 }
112
critical_exit(void)113 static __inline void critical_exit(void)
114 {
115 }
116
117 int atomic_fetchadd_int(volatile int *p, int v);
118 #if 0
119 int atomic_add_int(volatile int *p, int v);
120 #endif
121 int atomic_load_acq_int(volatile int *p);
122 void atomic_store_rel_int(volatile int *p, int v);
123
124 u_short in_cksum_hdr(struct ip *ih);
125
126 #define if_drv_flags if_flags
127 #define IFF_DRV_RUNNING IFF_RUNNING
128 #define IFF_DRV_OACTIVE IFF_OACTIVE
129
130 #define MJUM16BYTES (16*1024)
131 #define MJUMPAGESIZE PAGE_SIZE
132
133 #if 0
134 #define rw_rlock(x) rw_enter(x, RW_READER)
135 #define rw_runlock(x) rw_exit(x)
136 #define rw_wlock(x) rw_enter(x, RW_WRITER)
137 #define rw_wunlock(x) rw_exit(x)
138 #endif
139
140 #define callout_drain(x) callout_stop(x)
141
atomic_cmpset_ptr(volatile long * dst,long exp,long src)142 static __inline int atomic_cmpset_ptr(volatile long *dst, long exp, long src)
143 {
144 if (*dst == exp)
145 {
146 *dst = src;
147 return (1);
148 }
149 return (0);
150 }
151 #define atomic_cmpset_int(a, b, c) atomic_cmpset_ptr((volatile long *)a, (long)b, (long)c)
152
atomic_set_int(volatile int * dst,int val)153 static __inline int atomic_set_int(volatile int *dst, int val)
154 {
155 *dst = val;
156
157 return (val);
158 }
159
log(int x,...)160 static __inline void log(int x, ...)
161 {
162 }
163
164 struct cxgb_attach_args
165 {
166 int port;
167 };
168
169 #define INT3 __asm("int $3")
170
171 typedef struct adapter adapter_t;
172 struct sge_rspq;
173
174 struct t3_mbuf_hdr {
175 struct mbuf *mh_head;
176 struct mbuf *mh_tail;
177 };
178
179
180 #define PANIC_IF(exp) do { \
181 if (exp) \
182 panic("BUG: %s", exp); \
183 } while (0)
184
185
186 #define m_get_priority(m) M_GETCTX((m), uintptr_t)
187 #define m_set_priority(m, pri) M_SETCTX((m), (uintptr_t)(pri))
188
189 #define if_name(ifp) (ifp)->if_xname
190 #define M_SANITY(m, n)
191
192 /*
193 * Workaround for weird Chelsio issue
194 */
195 #define CXGB_TX_CLEANUP_THRESHOLD 32
196
197 #define LOG_WARNING 1
198 #define LOG_ERR 2
199
200 #define DPRINTF printf
201
202 #define TX_MAX_SIZE (1 << 16) /* 64KB */
203 #define TX_MAX_SEGS 36 /* maximum supported by card */
204 #define TX_MAX_DESC 4 /* max descriptors per packet */
205
206 #define TX_START_MIN_DESC (TX_MAX_DESC << 2)
207
208 #if 0
209 #define TX_START_MAX_DESC (TX_ETH_Q_SIZE >> 2) /* maximum number of descriptors */
210 #endif
211
212 #define TX_START_MAX_DESC (TX_MAX_DESC << 3) /* maximum number of descriptors
213 * call to start used per */
214
215 #define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 4) /* maximum tx descriptors
216 * to clean per iteration */
217
218
219 #if defined(__i386__) || defined(__amd64__)
220 #define mb() __asm volatile("mfence":::"memory")
221 #define rmb() __asm volatile("lfence":::"memory")
222 #define wmb() __asm volatile("sfence" ::: "memory")
223 #define smp_mb() mb()
224
225 #define L1_CACHE_BYTES 64
226 static __inline
prefetch(void * x)227 void prefetch(void *x)
228 {
229 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
230 }
231
232 extern void kdb_backtrace(void);
233
234 #define WARN_ON(condition) do { \
235 if (unlikely((condition)!=0)) { \
236 log(LOG_WARNING, "BUG: warning at %s:%d/%s()\n", __FILE__, __LINE__, __func__); \
237 kdb_backtrace(); \
238 } \
239 } while (0)
240
241
242 #else /* !i386 && !amd64 */
243 #define mb()
244 #define rmb()
245 #define wmb()
246 #define smp_mb()
247 #define prefetch(x)
248 #define L1_CACHE_BYTES 32
249 #endif
250 #define DBG_RX (1 << 0)
251 static const int debug_flags = DBG_RX;
252
253 #ifdef DEBUG_PRINT
254 #define DBG(flag, msg) do { \
255 if ((flag & debug_flags)) \
256 printf msg; \
257 } while (0)
258 #else
259 #define DBG(...)
260 #endif
261
262 #define promisc_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_PROMISC)
263 #define allmulti_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_ALLMULTI)
264
265 #define CH_ERR(adap, fmt, ...) { }
266
267 #define CH_WARN(adap, fmt, ...) { }
268 #define CH_ALERT(adap, fmt, ...) { }
269
270 #define t3_os_sleep(x) DELAY((x) * 1000)
271
272 #define test_and_clear_bit(bit, p) atomic_cmpset_int((p), ((*(p)) | bit), ((*(p)) & ~bit))
273
274
275 #define max_t(type, a, b) (type)uimax((a), (b))
276 #define net_device ifnet
277 #define cpu_to_be32 htobe32
278
279
280
281 /* Standard PHY definitions */
282 #define BMCR_LOOPBACK BMCR_LOOP
283 #define BMCR_ISOLATE BMCR_ISO
284 #define BMCR_ANENABLE BMCR_AUTOEN
285 #define BMCR_SPEED1000 BMCR_SPEED1
286 #define BMCR_SPEED100 BMCR_SPEED0
287 #define BMCR_ANRESTART BMCR_STARTNEG
288 #define BMCR_FULLDPLX BMCR_FDX
289 #define BMSR_LSTATUS BMSR_LINK
290 #define BMSR_ANEGCOMPLETE BMSR_ACOMP
291
292 #define MII_LPA MII_ANLPAR
293 #define MII_ADVERTISE MII_ANAR
294 #define MII_CTRL1000 MII_100T2CR
295
296 #define ADVERTISE_PAUSE_CAP ANAR_FC
297 #define ADVERTISE_PAUSE_ASYM 0x0800
298 #define ADVERTISE_1000HALF ANAR_X_HD
299 #define ADVERTISE_1000FULL ANAR_X_FD
300 #define ADVERTISE_10FULL ANAR_10_FD
301 #define ADVERTISE_10HALF ANAR_10
302 #define ADVERTISE_100FULL ANAR_TX_FD
303 #define ADVERTISE_100HALF ANAR_TX
304
305 /* Standard PCI Extended Capaibilities definitions */
306 #define PCI_CAP_ID_VPD 0x03
307 #define PCI_VPD_ADDR 2
308 #define PCI_VPD_ADDR_F 0x8000
309 #define PCI_VPD_DATA 4
310
311 #define PCI_CAP_ID_EXP 0x10
312 #define PCI_EXP_DEVCTL 8
313 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
314 #define PCI_EXP_LNKCTL 16
315 #define PCI_EXP_LNKSTA 18
316
317 /*
318 * Linux compatibility macros
319 */
320
321 /* Some simple translations */
322 #define __devinit
323 #define udelay(x) DELAY(x)
324 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
325 #define le32_to_cpu(x) le32toh(x)
326 #define cpu_to_le32(x) htole32(x)
327 #define swab32(x) bswap32(x)
328 #define simple_strtoul strtoul
329
330 /* More types and endian definitions */
331 typedef uint8_t u8;
332 typedef uint16_t u16;
333 typedef uint32_t u32;
334 typedef uint64_t u64;
335
336 typedef uint8_t __u8;
337 typedef uint16_t __u16;
338 typedef uint32_t __u32;
339 typedef uint8_t __be8;
340 typedef uint16_t __be16;
341 typedef uint32_t __be32;
342 typedef uint64_t __be64;
343
344 #if BYTE_ORDER == BIG_ENDIAN
345 #define __BIG_ENDIAN_BITFIELD
346 #elif BYTE_ORDER == LITTLE_ENDIAN
347 #define __LITTLE_ENDIAN_BITFIELD
348 #else
349 #error "Must set BYTE_ORDER"
350 #endif
351
352 /* Indicates what features are supported by the interface. */
353 #define SUPPORTED_10baseT_Half (1 << 0)
354 #define SUPPORTED_10baseT_Full (1 << 1)
355 #define SUPPORTED_100baseT_Half (1 << 2)
356 #define SUPPORTED_100baseT_Full (1 << 3)
357 #define SUPPORTED_1000baseT_Half (1 << 4)
358 #define SUPPORTED_1000baseT_Full (1 << 5)
359 #define SUPPORTED_Autoneg (1 << 6)
360 #define SUPPORTED_TP (1 << 7)
361 #define SUPPORTED_AUI (1 << 8)
362 #define SUPPORTED_MII (1 << 9)
363 #define SUPPORTED_FIBRE (1 << 10)
364 #define SUPPORTED_BNC (1 << 11)
365 #define SUPPORTED_10000baseT_Full (1 << 12)
366 #define SUPPORTED_Pause (1 << 13)
367 #define SUPPORTED_Asym_Pause (1 << 14)
368
369 /* Indicates what features are advertised by the interface. */
370 #define ADVERTISED_10baseT_Half (1 << 0)
371 #define ADVERTISED_10baseT_Full (1 << 1)
372 #define ADVERTISED_100baseT_Half (1 << 2)
373 #define ADVERTISED_100baseT_Full (1 << 3)
374 #define ADVERTISED_1000baseT_Half (1 << 4)
375 #define ADVERTISED_1000baseT_Full (1 << 5)
376 #define ADVERTISED_Autoneg (1 << 6)
377 #define ADVERTISED_TP (1 << 7)
378 #define ADVERTISED_AUI (1 << 8)
379 #define ADVERTISED_MII (1 << 9)
380 #define ADVERTISED_FIBRE (1 << 10)
381 #define ADVERTISED_BNC (1 << 11)
382 #define ADVERTISED_10000baseT_Full (1 << 12)
383 #define ADVERTISED_Pause (1 << 13)
384 #define ADVERTISED_Asym_Pause (1 << 14)
385
386 /* Enable or disable autonegotiation. If this is set to enable,
387 * the forced link modes above are completely ignored.
388 */
389 #define AUTONEG_DISABLE 0x00
390 #define AUTONEG_ENABLE 0x01
391
392 #define SPEED_10 10
393 #define SPEED_100 100
394 #define SPEED_1000 1000
395 #define SPEED_10000 10000
396 #define DUPLEX_HALF 0
397 #define DUPLEX_FULL 1
398
399 #endif
400