1 /*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
10 *
11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/advansys/adw_pci.c,v 1.12.2.1 2000/08/02 22:22:40 peter Exp $
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43 #include <sys/rman.h>
44
45 #include <bus/pci/pcireg.h>
46 #include <bus/pci/pcivar.h>
47
48 #include <bus/cam/cam.h>
49 #include <bus/cam/scsi/scsi_all.h>
50
51 #include "adwvar.h"
52 #include "adwlib.h"
53 #include "adwmcode.h"
54
55 #define ADW_PCI_IOBASE PCIR_MAPS /* I/O Address */
56 #define ADW_PCI_MEMBASE PCIR_MAPS + 4 /* Mem I/O Address */
57
58 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
59 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
60 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
61 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
62 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
63
64 struct adw_pci_identity;
65 typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
66 struct adw_softc *adw);
67
68 struct adw_pci_identity {
69 u_int64_t full_id;
70 u_int64_t id_mask;
71 char *name;
72 adw_device_setup_t *setup;
73 const struct adw_mcode *mcode_data;
74 const struct adw_eeprom *default_eeprom;
75 };
76
77 static adw_device_setup_t adw_asc3550_setup;
78 static adw_device_setup_t adw_asc38C0800_setup;
79 #ifdef NOTYET
80 static adw_device_setup_t adw_asc38C1600_setup;
81 #endif
82
83 struct adw_pci_identity adw_pci_ident_table[] =
84 {
85 /* asc3550 based controllers */
86 {
87 PCI_ID_ADVANSYS_3550,
88 PCI_ID_DEV_VENDOR_MASK,
89 "AdvanSys 3550 Ultra SCSI Adapter",
90 adw_asc3550_setup,
91 &adw_asc3550_mcode_data,
92 &adw_asc3550_default_eeprom
93 },
94 /* asc38C0800 based controllers */
95 {
96 PCI_ID_ADVANSYS_38C0800_REV1,
97 PCI_ID_DEV_VENDOR_MASK,
98 "AdvanSys 38C0800 Ultra2 SCSI Adapter",
99 adw_asc38C0800_setup,
100 &adw_asc38C0800_mcode_data,
101 &adw_asc38C0800_default_eeprom
102 },
103 #if 0 /* NOTYET */
104 /* XXX Disabled until I have hardware to test with */
105 /* asc38C1600 based controllers */
106 {
107 PCI_ID_ADVANSYS_38C1600_REV1,
108 PCI_ID_DEV_VENDOR_MASK,
109 "AdvanSys 38C1600 Ultra160 SCSI Adapter",
110 adw_asc38C1600_setup,
111 NULL, /* None provided by vendor thus far */
112 NULL /* None provided by vendor thus far */
113 }
114 #endif
115 };
116
117 static const int adw_num_pci_devs = NELEM(adw_pci_ident_table);
118
119 #define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
120 #define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
121
122 static int adw_pci_probe(device_t dev);
123 static int adw_pci_attach(device_t dev);
124
125 static device_method_t adw_pci_methods[] = {
126 /* Device interface */
127 DEVMETHOD(device_probe, adw_pci_probe),
128 DEVMETHOD(device_attach, adw_pci_attach),
129 DEVMETHOD_END
130 };
131
132 static driver_t adw_pci_driver = {
133 "adw",
134 adw_pci_methods,
135 sizeof(struct adw_softc)
136 };
137
138 static devclass_t adw_devclass;
139
140 DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, NULL, NULL);
141
142 static __inline u_int64_t
adw_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)143 adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
144 {
145 u_int64_t id;
146
147 id = subvendor
148 | (subdevice << 16)
149 | ((u_int64_t)vendor << 32)
150 | ((u_int64_t)device << 48);
151
152 return (id);
153 }
154
155 static struct adw_pci_identity *
adw_find_pci_device(device_t dev)156 adw_find_pci_device(device_t dev)
157 {
158 u_int64_t full_id;
159 struct adw_pci_identity *entry;
160 u_int i;
161
162 full_id = adw_compose_id(pci_get_device(dev),
163 pci_get_vendor(dev),
164 pci_get_subdevice(dev),
165 pci_get_subvendor(dev));
166
167 for (i = 0; i < adw_num_pci_devs; i++) {
168 entry = &adw_pci_ident_table[i];
169 if (entry->full_id == (full_id & entry->id_mask))
170 return (entry);
171 }
172 return (NULL);
173 }
174
175 static int
adw_pci_probe(device_t dev)176 adw_pci_probe(device_t dev)
177 {
178 struct adw_pci_identity *entry;
179
180 entry = adw_find_pci_device(dev);
181 if (entry != NULL) {
182 device_set_desc(dev, entry->name);
183 return (0);
184 }
185 return (ENXIO);
186 }
187
188 static int
adw_pci_attach(device_t dev)189 adw_pci_attach(device_t dev)
190 {
191 struct adw_softc *adw;
192 struct adw_pci_identity *entry;
193 u_int32_t command;
194 struct resource *regs;
195 int regs_type;
196 int regs_id;
197 int error;
198 int zero;
199
200 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
201 entry = adw_find_pci_device(dev);
202 if (entry == NULL)
203 return (ENXIO);
204 regs = NULL;
205 regs_type = 0;
206 regs_id = 0;
207 #ifdef ADW_ALLOW_MEMIO
208 if ((command & PCIM_CMD_MEMEN) != 0) {
209 regs_type = SYS_RES_MEMORY;
210 regs_id = ADW_PCI_MEMBASE;
211 regs = bus_alloc_resource(dev, regs_type,
212 ®s_id, 0, ~0, 1, RF_ACTIVE);
213 }
214 #endif
215 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
216 regs_type = SYS_RES_IOPORT;
217 regs_id = ADW_PCI_IOBASE;
218 regs = bus_alloc_resource(dev, regs_type,
219 ®s_id, 0, ~0, 1, RF_ACTIVE);
220 }
221
222 if (regs == NULL) {
223 device_printf(dev, "can't allocate register resources\n");
224 return (ENOMEM);
225 }
226
227 adw = adw_alloc(dev, regs, regs_type, regs_id);
228 if (adw == NULL)
229 return(ENOMEM);
230
231 /*
232 * Now that we have access to our registers, just verify that
233 * this really is an AdvanSys device.
234 */
235 if (adw_find_signature(adw) == 0) {
236 adw_free(adw);
237 return (ENXIO);
238 }
239
240 adw_reset_chip(adw);
241
242 error = entry->setup(dev, entry, adw);
243
244 if (error != 0)
245 return (error);
246
247 /* Ensure busmastering is enabled */
248 command |= PCIM_CMD_BUSMASTEREN;
249 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
250
251 /* Allocate a dmatag for our transfer DMA maps */
252 /* XXX Should be a child of the PCI bus dma tag */
253 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
254 /*boundary*/0,
255 /*lowaddr*/ADW_PCI_MAX_DMA_ADDR,
256 /*highaddr*/BUS_SPACE_MAXADDR,
257 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
258 /*nsegments*/BUS_SPACE_UNRESTRICTED,
259 /*maxsegsz*/ADW_PCI_MAX_DMA_COUNT,
260 /*flags*/0,
261 &adw->parent_dmat);
262
263 adw->init_level++;
264
265 if (error != 0) {
266 kprintf("%s: Could not allocate DMA tag - error %d\n",
267 adw_name(adw), error);
268 adw_free(adw);
269 return (error);
270 }
271
272 adw->init_level++;
273
274 error = adw_init(adw);
275 if (error != 0) {
276 adw_free(adw);
277 return (error);
278 }
279
280 /*
281 * If the PCI Configuration Command Register "Parity Error Response
282 * Control" Bit was clear (0), then set the microcode variable
283 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
284 * to ignore DMA parity errors.
285 */
286 if ((command & PCIM_CMD_PERRESPEN) == 0)
287 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
288 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
289 | ADW_MC_CONTROL_IGN_PERR);
290
291 zero = 0;
292 adw->irq_res_type = SYS_RES_IRQ;
293 adw->irq = bus_alloc_resource(dev, adw->irq_res_type, &zero,
294 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
295 if (adw->irq == NULL) {
296 adw_free(adw);
297 return (ENOMEM);
298 }
299
300 error = adw_attach(adw);
301 if (error != 0)
302 adw_free(adw);
303 return (error);
304 }
305
306 static int
adw_generic_setup(device_t dev,struct adw_pci_identity * entry,struct adw_softc * adw)307 adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
308 struct adw_softc *adw)
309 {
310 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
311 adw->chip = ADW_CHIP_NONE;
312 adw->features = ADW_FENONE;
313 adw->flags = ADW_FNONE;
314 adw->mcode_data = entry->mcode_data;
315 adw->default_eeprom = entry->default_eeprom;
316 return (0);
317 }
318
319 static int
adw_asc3550_setup(device_t dev,struct adw_pci_identity * entry,struct adw_softc * adw)320 adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
321 struct adw_softc *adw)
322 {
323 int error;
324
325 error = adw_generic_setup(dev, entry, adw);
326 if (error != 0)
327 return (error);
328 adw->chip = ADW_CHIP_ASC3550;
329 adw->features = ADW_ASC3550_FE;
330 adw->memsize = ADW_3550_MEMSIZE;
331 /*
332 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits
333 * sets a FIFO threshold of 128 bytes. This register is
334 * only accessible to the host.
335 */
336 adw_outb(adw, ADW_DMA_CFG0,
337 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
338 adw_outb(adw, ADW_MEM_CFG,
339 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
340 return (0);
341 }
342
343 static int
adw_asc38C0800_setup(device_t dev,struct adw_pci_identity * entry,struct adw_softc * adw)344 adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
345 struct adw_softc *adw)
346 {
347 int error;
348
349 error = adw_generic_setup(dev, entry, adw);
350 if (error != 0)
351 return (error);
352 /*
353 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
354 * START_CTL_TH [3:2] bits for the default FIFO threshold.
355 *
356 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
357 *
358 * For DMA Errata #4 set the BC_THRESH_ENB bit.
359 */
360 adw_outb(adw, ADW_DMA_CFG0,
361 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
362 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
363 adw_outb(adw, ADW_MEM_CFG,
364 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
365 adw->chip = ADW_CHIP_ASC38C0800;
366 adw->features = ADW_ASC38C0800_FE;
367 adw->memsize = ADW_38C0800_MEMSIZE;
368 return (error);
369 }
370
371 #ifdef NOTYET
372 static int
adw_asc38C1600_setup(device_t dev,struct adw_pci_identity * entry,struct adw_softc * adw)373 adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
374 struct adw_softc *adw)
375 {
376 int error;
377
378 error = adw_generic_setup(dev, entry, adw);
379 if (error != 0)
380 return (error);
381 adw->chip = ADW_CHIP_ASC38C1600;
382 adw->features = ADW_ASC38C1600_FE;
383 adw->memsize = ADW_38C1600_MEMSIZE;
384 return (error);
385 }
386 #endif
387