1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_C4XXX_INLINE_H_ 4 #define ADF_C4XXX_INLINE_H_ 5 6 /* Inline register addresses in SRAM BAR */ 7 #define ARAM_CSR_BAR_OFFSET 0x100000 8 #define ADF_C4XXX_REG_SA_CTRL_LOCK (ARAM_CSR_BAR_OFFSET + 0x00) 9 #define ADF_C4XXX_REG_SA_SCRATCH_0 (ARAM_CSR_BAR_OFFSET + 0x04) 10 #define ADF_C4XXX_REG_SA_SCRATCH_2 (ARAM_CSR_BAR_OFFSET + 0x0C) 11 #define ADF_C4XXX_REG_SA_ENTRY_CTRL (ARAM_CSR_BAR_OFFSET + 0x18) 12 #define ADF_C4XXX_REG_SA_DB_CTRL (ARAM_CSR_BAR_OFFSET + 0x1C) 13 #define ADF_C4XXX_REG_SA_REMAP (ARAM_CSR_BAR_OFFSET + 0x20) 14 #define ADF_C4XXX_REG_SA_INLINE_CAPABILITY (ARAM_CSR_BAR_OFFSET + 0x24) 15 #define ADF_C4XXX_REG_SA_INLINE_ENABLE (ARAM_CSR_BAR_OFFSET + 0x28) 16 #define ADF_C4XXX_REG_SA_LINK_UP (ARAM_CSR_BAR_OFFSET + 0x2C) 17 #define ADF_C4XXX_REG_SA_FUNC_LIMITS (ARAM_CSR_BAR_OFFSET + 0x38) 18 19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24) 20 #define ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) \ 21 ((accel_dev)->aram_info->sadb_region_size / 32) 22 #define ADF_C4XXX_DEFAULT_MAX_CHAIN_LEN 0 23 #define ADF_C4XXX_DEFAULT_LIMIT_CHAIN_LEN 0 24 /* SADB CTRL register bit offsets */ 25 #define ADF_C4XXX_SADB_BIT_OFFSET 6 26 #define ADF_C4XXX_MAX_CHAIN_LEN_BIT_OFFS 1 27 28 #define ADF_C4XXX_SADB_REG_VALUE(accel_dev) \ 29 ((ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) \ 30 << ADF_C4XXX_SADB_BIT_OFFSET) | \ 31 (ADF_C4XXX_DEFAULT_MAX_CHAIN_LEN \ 32 << ADF_C4XXX_MAX_CHAIN_LEN_BIT_OFFS) | \ 33 (ADF_C4XXX_DEFAULT_LIMIT_CHAIN_LEN)) 34 35 #define ADF_C4XXX_INLINE_INGRESS_OFFSET 0x0 36 #define ADF_C4XXX_INLINE_EGRESS_OFFSET 0x1000 37 38 /* MAC_CFG register access related definitions */ 39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16) 40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16) 41 #define ADF_C4XXX_UNLOCK true 42 #define ADF_C4XXX_LOCK false 43 44 /* MAC IP register access related definitions */ 45 #define ADF_C4XXX_MAC_STATS_READY BIT(0) 46 #define ADF_C4XXX_MAX_NUM_STAT_READY_READS 10 47 #define ADF_C4XXX_MAC_STATS_POLLING_INTERVAL 100 48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6) 49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7) 50 #define ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT BIT(8) 51 #define ADF_C4XXX_MAC_ERROR_RX_OVERRUN BIT(9) 52 #define ADF_C4XXX_MAC_ERROR_RX_RUNT BIT(10) 53 #define ADF_C4XXX_MAC_ERROR_RX_UNDERSIZE BIT(11) 54 #define ADF_C4XXX_MAC_ERROR_RX_JABBER BIT(12) 55 #define ADF_C4XXX_MAC_ERROR_RX_OVERSIZE BIT(13) 56 #define ADF_C4XXX_MAC_ERROR_RX_FCS BIT(14) 57 #define ADF_C4XXX_MAC_ERROR_RX_FRAME BIT(15) 58 #define ADF_C4XXX_MAC_ERROR_RX_CODE BIT(16) 59 #define ADF_C4XXX_MAC_ERROR_RX_PREAMBLE BIT(17) 60 #define ADF_C4XXX_MAC_RX_LINK_UP BIT(21) 61 #define ADF_C4XXX_MAC_INVALID_SPEED BIT(31) 62 #define ADF_C4XXX_MAC_PIA_RX_FIFO_OVERRUN (1ULL << 32) 63 #define ADF_C4XXX_MAC_PIA_TX_FIFO_OVERRUN (1ULL << 33) 64 #define ADF_C4XXX_MAC_PIA_TX_FIFO_UNDERRUN (1ULL << 34) 65 66 /* 64-bit inline control registers. It will require 67 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 68 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 69 * egress direction 70 */ 71 #define ADF_C4XXX_MAC_IP 0x8 72 #define ADF_C4XXX_MAC_CFG 0x18 73 #define ADF_C4XXX_MAC_PIA_CFG 0xA0 74 75 /* Default MAC_CFG value 76 * - MAC_LINKUP_ENABLE = 1 77 * - MAX_FRAME_LENGTH = 0x2600 78 */ 79 #define ADF_C4XXX_MAC_CFG_VALUE 0x00000000FA0C2600 80 81 /* Bit definitions for MAC_PIA_CFG register */ 82 #define ADF_C4XXX_ONPI_ENABLE BIT(0) 83 #define ADF_C4XXX_XOFF_ENABLE BIT(10) 84 85 /* New default value for MAC_PIA_CFG register */ 86 #define ADF_C4XXX_MAC_PIA_CFG_VALUE \ 87 (ADF_C4XXX_XOFF_ENABLE | ADF_C4XXX_ONPI_ENABLE) 88 89 /* 64-bit Inline statistics registers. It will require 90 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 91 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 92 * egress direction 93 */ 94 #define ADF_C4XXX_MAC_STAT_TX_OCTET 0x100 95 #define ADF_C4XXX_MAC_STAT_TX_FRAME 0x110 96 #define ADF_C4XXX_MAC_STAT_TX_BAD_FRAME 0x118 97 #define ADF_C4XXX_MAC_STAT_TX_FCS_ERROR 0x120 98 #define ADF_C4XXX_MAC_STAT_TX_64 0x130 99 #define ADF_C4XXX_MAC_STAT_TX_65 0x138 100 #define ADF_C4XXX_MAC_STAT_TX_128 0x140 101 #define ADF_C4XXX_MAC_STAT_TX_256 0x148 102 #define ADF_C4XXX_MAC_STAT_TX_512 0x150 103 #define ADF_C4XXX_MAC_STAT_TX_1024 0x158 104 #define ADF_C4XXX_MAC_STAT_TX_1519 0x160 105 #define ADF_C4XXX_MAC_STAT_TX_JABBER 0x168 106 #define ADF_C4XXX_MAC_STAT_RX_OCTET 0x200 107 #define ADF_C4XXX_MAC_STAT_RX_FRAME 0x210 108 #define ADF_C4XXX_MAC_STAT_RX_BAD_FRAME 0x218 109 #define ADF_C4XXX_MAC_STAT_RX_FCS_ERROR 0x220 110 #define ADF_C4XXX_MAC_STAT_RX_64 0x250 111 #define ADF_C4XXX_MAC_STAT_RX_65 0x258 112 #define ADF_C4XXX_MAC_STAT_RX_128 0x260 113 #define ADF_C4XXX_MAC_STAT_RX_256 0x268 114 #define ADF_C4XXX_MAC_STAT_RX_512 0x270 115 #define ADF_C4XXX_MAC_STAT_RX_1024 0x278 116 #define ADF_C4XXX_MAC_STAT_RX_1519 0x280 117 #define ADF_C4XXX_MAC_STAT_RX_OVERSIZE 0x288 118 #define ADF_C4XXX_MAC_STAT_RX_JABBER 0x290 119 120 /* 32-bit Inline statistics registers. It will require 121 * adding ADF_C4XXX_INLINE_INGRESS_OFFSET to the address for ingress 122 * direction or ADF_C4XXX_INLINE_EGRESS_OFFSET to the address for 123 * egress direction 124 */ 125 #define ADF_C4XXX_IC_PAR_IPSEC_DESC_COUNT 0xBC0 126 #define ADF_C4XXX_IC_PAR_MIXED_DESC_COUNT 0xBC4 127 #define ADF_C4XXX_IC_PAR_FULLY_CLEAR_DESC_COUNT 0xBC8 128 #define ADF_C4XXX_IC_PAR_CLR_COUNT 0xBCC 129 #define ADF_C4XXX_IC_CTPB_PKT_COUNT 0xDF4 130 #define ADF_C4XXX_RB_DATA_COUNT 0xDF8 131 #define ADF_C4XXX_IC_CLEAR_DESC_COUNT 0xDFC 132 #define ADF_C4XXX_IC_IPSEC_DESC_COUNT 0xE00 133 134 /* REG_CMD_DIS_MISC bit definitions */ 135 #define ADF_C4XXX_BYTE_SWAP_ENABLE BIT(0) 136 #define ADF_C4XXX_REG_CMD_DIS_MISC_DEFAULT_VALUE (ADF_C4XXX_BYTE_SWAP_ENABLE) 137 138 /* Command Dispatch Misc Register */ 139 #define ADF_C4XXX_INGRESS_CMD_DIS_MISC (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0x8A8) 140 141 #define ADF_C4XXX_EGRESS_CMD_DIS_MISC (ADF_C4XXX_INLINE_EGRESS_OFFSET + 0x8A8) 142 143 /* Congestion management threshold registers */ 144 #define ADF_C4XXX_NEXT_FCTHRESH_OFFSET 4 145 146 /* Number of congestion management domains */ 147 #define ADF_C4XXX_NUM_CONGEST_DOMAINS 8 148 149 #define ADF_C4XXX_BB_FCHTHRESH_OFFSET 0xB78 150 151 /* IC_BB_FCHTHRESH registers */ 152 #define ADF_C4XXX_ICI_BB_FCHTHRESH_OFFSET \ 153 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_FCHTHRESH_OFFSET) 154 155 #define ADF_C4XXX_ICE_BB_FCHTHRESH_OFFSET \ 156 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_FCHTHRESH_OFFSET) 157 158 #define ADF_C4XXX_WR_ICI_BB_FCHTHRESH(csr_base_addr, index, value) \ 159 ADF_CSR_WR(csr_base_addr, \ 160 (ADF_C4XXX_ICI_BB_FCHTHRESH_OFFSET + \ 161 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 162 value) 163 164 #define ADF_C4XXX_WR_ICE_BB_FCHTHRESH(csr_base_addr, index, value) \ 165 ADF_CSR_WR(csr_base_addr, \ 166 (ADF_C4XXX_ICE_BB_FCHTHRESH_OFFSET + \ 167 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 168 value) 169 170 #define ADF_C4XXX_BB_FCLTHRESH_OFFSET 0xB98 171 172 /* IC_BB_FCLTHRESH registers */ 173 #define ADF_C4XXX_ICI_BB_FCLTHRESH_OFFSET \ 174 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_FCLTHRESH_OFFSET) 175 176 #define ADF_C4XXX_ICE_BB_FCLTHRESH_OFFSET \ 177 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_FCLTHRESH_OFFSET) 178 179 #define ADF_C4XXX_WR_ICI_BB_FCLTHRESH(csr_base_addr, index, value) \ 180 ADF_CSR_WR(csr_base_addr, \ 181 (ADF_C4XXX_ICI_BB_FCLTHRESH_OFFSET + \ 182 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 183 value) 184 185 #define ADF_C4XXX_WR_ICE_BB_FCLTHRESH(csr_base_addr, index, value) \ 186 ADF_CSR_WR(csr_base_addr, \ 187 (ADF_C4XXX_ICE_BB_FCLTHRESH_OFFSET + \ 188 (index)*ADF_C4XXX_NEXT_FCTHRESH_OFFSET), \ 189 value) 190 191 #define ADF_C4XXX_BB_BEHTHRESH_OFFSET 0xBB8 192 #define ADF_C4XXX_BB_BELTHRESH_OFFSET 0xBBC 193 #define ADF_C4XXX_BEWIP_THRESH_OFFSET 0xDEC 194 #define ADF_C4XXX_CTPB_THRESH_OFFSET 0xDE8 195 #define ADF_C4XXX_CIRQ_OFFSET 0xDE4 196 #define ADF_C4XXX_Q2MEMAP_OFFSET 0xC04 197 198 /* IC_BB_BEHTHRESH register */ 199 #define ADF_C4XXX_ICI_BB_BEHTHRESH_OFFSET \ 200 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_BEHTHRESH_OFFSET) 201 202 #define ADF_C4XXX_ICE_BB_BEHTHRESH_OFFSET \ 203 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_BEHTHRESH_OFFSET) 204 205 /* IC_BB_BELTHRESH register */ 206 #define ADF_C4XXX_ICI_BB_BELTHRESH_OFFSET \ 207 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BB_BELTHRESH_OFFSET) 208 209 #define ADF_C4XXX_ICE_BB_BELTHRESH_OFFSET \ 210 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BB_BELTHRESH_OFFSET) 211 212 /* IC_BEWIP_THRESH register */ 213 #define ADF_C4XXX_ICI_BEWIP_THRESH_OFFSET \ 214 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_BEWIP_THRESH_OFFSET) 215 216 #define ADF_C4XXX_ICE_BEWIP_THRESH_OFFSET \ 217 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_BEWIP_THRESH_OFFSET) 218 219 /* IC_CTPB_THRESH register */ 220 #define ADF_C4XXX_ICI_CTPB_THRESH_OFFSET \ 221 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_CTPB_THRESH_OFFSET) 222 223 #define ADF_C4XXX_ICE_CTPB_THRESH_OFFSET \ 224 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_CTPB_THRESH_OFFSET) 225 226 /* ADF_C4XXX_ICI_CIRQ_OFFSET */ 227 #define ADF_C4XXX_ICI_CIRQ_OFFSET \ 228 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_CIRQ_OFFSET) 229 230 #define ADF_C4XXX_ICE_CIRQ_OFFSET \ 231 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_CIRQ_OFFSET) 232 233 /* IC_Q2MEMAP register */ 234 #define ADF_C4XXX_ICI_Q2MEMAP_OFFSET \ 235 (ADF_C4XXX_INLINE_INGRESS_OFFSET + ADF_C4XXX_Q2MEMAP_OFFSET) 236 237 #define ADF_C4XXX_ICE_Q2MEMAP_OFFSET \ 238 (ADF_C4XXX_INLINE_EGRESS_OFFSET + ADF_C4XXX_Q2MEMAP_OFFSET) 239 240 #define ADF_C4XXX_NEXT_Q2MEMAP_OFFSET 4 241 #define ADF_C4XXX_NUM_Q2MEMAP_REGISTERS 8 242 243 #define ADF_C4XXX_WR_CSR_ICI_Q2MEMAP(csr_base_addr, index, value) \ 244 ADF_CSR_WR(csr_base_addr, \ 245 (ADF_C4XXX_ICI_Q2MEMAP_OFFSET + \ 246 (index)*ADF_C4XXX_NEXT_Q2MEMAP_OFFSET), \ 247 value) 248 249 #define ADF_C4XXX_WR_CSR_ICE_Q2MEMAP(csr_base_addr, index, value) \ 250 ADF_CSR_WR(csr_base_addr, \ 251 (ADF_C4XXX_ICE_Q2MEMAP_OFFSET + \ 252 (index)*ADF_C4XXX_NEXT_Q2MEMAP_OFFSET), \ 253 value) 254 255 /* IC_PARSE_CTRL register */ 256 #define ADF_C4XXX_DEFAULT_KEY_LENGTH 21 257 #define ADF_C4XXX_DEFAULT_REL_ABS_OFFSET 1 258 #define ADF_C4XXX_DEFAULT_NUM_TUPLES 4 259 #define ADF_C4XXX_IC_PARSE_CTRL_OFFSET_DEFAULT_VALUE \ 260 ((ADF_C4XXX_DEFAULT_KEY_LENGTH << 4) | \ 261 (ADF_C4XXX_DEFAULT_REL_ABS_OFFSET << 3) | \ 262 (ADF_C4XXX_DEFAULT_NUM_TUPLES)) 263 264 /* Configuration parsing register definitions */ 265 #define ADF_C4XXX_IC_PARSE_CTRL_OFFSET (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB00) 266 267 /* Fixed data parsing register */ 268 #define ADF_C4XXX_IC_PARSE_FIXED_DATA(i) \ 269 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB04 + ((i)*4)) 270 #define ADF_C4XXX_DEFAULT_IC_PARSE_FIXED_DATA_0 0x32 271 272 /* Fixed length parsing register */ 273 #define ADF_C4XXX_IC_PARSE_FIXED_LENGTH \ 274 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB14) 275 #define ADF_C4XXX_DEFAULT_IC_PARSE_FIXED_LEN 0x0 276 277 /* IC_PARSE_IPV4 offset and length registers */ 278 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_0 \ 279 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB18) 280 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_1 \ 281 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB1C) 282 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_2 \ 283 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB20) 284 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_3 \ 285 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB24) 286 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_4 \ 287 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB28) 288 #define ADF_C4XXX_IC_PARSE_IPV4_OFFSET_5 \ 289 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB2C) 290 291 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_0 \ 292 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB30) 293 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_1 \ 294 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB34) 295 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_2 \ 296 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB38) 297 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_3 \ 298 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB3C) 299 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_4 \ 300 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB40) 301 #define ADF_C4XXX_IC_PARSE_IPV4_LENGTH_5 \ 302 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB44) 303 304 #define ADF_C4XXX_IPV4_OFFSET_0_PARSER_BASE 0x1 305 #define ADF_C4XXX_IPV4_OFFSET_0_OFFSET 0x0 306 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_0_VALUE \ 307 ((ADF_C4XXX_IPV4_OFFSET_0_PARSER_BASE << 29) | \ 308 ADF_C4XXX_IPV4_OFFSET_0_OFFSET) 309 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_0_VALUE 0 310 311 #define ADF_C4XXX_IPV4_OFFSET_1_PARSER_BASE 0x2 312 #define ADF_C4XXX_IPV4_OFFSET_1_OFFSET 0x0 313 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_1_VALUE \ 314 ((ADF_C4XXX_IPV4_OFFSET_1_PARSER_BASE << 29) | \ 315 ADF_C4XXX_IPV4_OFFSET_1_OFFSET) 316 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_1_VALUE 3 317 318 #define ADF_C4XXX_IPV4_OFFSET_2_PARSER_BASE 0x4 319 #define ADF_C4XXX_IPV4_OFFSET_2_OFFSET 0x10 320 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_2_VALUE \ 321 ((ADF_C4XXX_IPV4_OFFSET_2_PARSER_BASE << 29) | \ 322 ADF_C4XXX_IPV4_OFFSET_2_OFFSET) 323 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_2_VALUE 3 324 325 #define ADF_C4XXX_IPV4_OFFSET_3_PARSER_BASE 0x0 326 #define ADF_C4XXX_IPV4_OFFSET_3_OFFSET 0x0 327 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_OFFS_3_VALUE \ 328 ((ADF_C4XXX_IPV4_OFFSET_3_PARSER_BASE << 29) | \ 329 ADF_C4XXX_IPV4_OFFSET_3_OFFSET) 330 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV4_LEN_3_VALUE 0 331 332 /* IC_PARSE_IPV6 offset and length registers */ 333 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_0 \ 334 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB48) 335 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_1 \ 336 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB4C) 337 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_2 \ 338 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB50) 339 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_3 \ 340 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB54) 341 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_4 \ 342 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB58) 343 #define ADF_C4XXX_IC_PARSE_IPV6_OFFSET_5 \ 344 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB5C) 345 346 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_0 \ 347 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB60) 348 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_1 \ 349 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB64) 350 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_2 \ 351 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB68) 352 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_3 \ 353 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB6C) 354 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_4 \ 355 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB70) 356 #define ADF_C4XXX_IC_PARSE_IPV6_LENGTH_5 \ 357 (ADF_C4XXX_INLINE_INGRESS_OFFSET + 0xB74) 358 359 #define ADF_C4XXX_IPV6_OFFSET_0_PARSER_BASE 0x1 360 #define ADF_C4XXX_IPV6_OFFSET_0_OFFSET 0x0 361 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_0_VALUE \ 362 ((ADF_C4XXX_IPV6_OFFSET_0_PARSER_BASE << 29) | \ 363 (ADF_C4XXX_IPV6_OFFSET_0_OFFSET)) 364 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_0_VALUE 0 365 366 #define ADF_C4XXX_IPV6_OFFSET_1_PARSER_BASE 0x2 367 #define ADF_C4XXX_IPV6_OFFSET_1_OFFSET 0x0 368 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_1_VALUE \ 369 ((ADF_C4XXX_IPV6_OFFSET_1_PARSER_BASE << 29) | \ 370 (ADF_C4XXX_IPV6_OFFSET_1_OFFSET)) 371 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_1_VALUE 3 372 373 #define ADF_C4XXX_IPV6_OFFSET_2_PARSER_BASE 0x4 374 #define ADF_C4XXX_IPV6_OFFSET_2_OFFSET 0x18 375 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_2_VALUE \ 376 ((ADF_C4XXX_IPV6_OFFSET_2_PARSER_BASE << 29) | \ 377 (ADF_C4XXX_IPV6_OFFSET_2_OFFSET)) 378 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_2_VALUE 0xF 379 380 #define ADF_C4XXX_IPV6_OFFSET_3_PARSER_BASE 0x0 381 #define ADF_C4XXX_IPV6_OFFSET_3_OFFSET 0x0 382 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_OFFS_3_VALUE \ 383 ((ADF_C4XXX_IPV6_OFFSET_3_PARSER_BASE << 29) | \ 384 (ADF_C4XXX_IPV6_OFFSET_3_OFFSET)) 385 #define ADF_C4XXX_DEFAULT_IC_PARSE_IPV6_LEN_3_VALUE 0x0 386 387 /* error notification configuration registers */ 388 389 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_0 0xA00 390 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_1 0xA04 391 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_2 0xA08 392 #define ADF_C4XXX_IC_CD_RF_PARITY_ERR_3 0xA0C 393 #define ADF_C4XXX_IC_CD_CERR 0xA10 394 #define ADF_C4XXX_IC_CD_UERR 0xA14 395 396 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_0 0xF00 397 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_1 0xF04 398 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_2 0xF08 399 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_3 0xF0C 400 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_4 0xF10 401 #define ADF_C4XXX_IC_INLN_RF_PARITY_ERR_5 0xF14 402 #define ADF_C4XXX_IC_PARSER_CERR 0xF18 403 #define ADF_C4XXX_IC_PARSER_UERR 0xF1C 404 #define ADF_C4XXX_IC_CTPB_CERR 0xF28 405 #define ADF_C4XXX_IC_CTPB_UERR 0xF2C 406 #define ADF_C4XXX_IC_CPPM_ERR_STAT 0xF3C 407 #define ADF_C4XXX_IC_CONGESTION_MGMT_INT 0xF58 408 409 #define ADF_C4XXX_IC_CPPT_ERR_STAT 0x704 410 #define ADF_C4XXX_IC_MAC_IM 0x10 411 412 #define ADF_C4XXX_CD_RF_PARITY_ERR_0_VAL 0x22222222 413 #define ADF_C4XXX_CD_RF_PARITY_ERR_1_VAL 0x22222323 414 #define ADF_C4XXX_CD_RF_PARITY_ERR_2_VAL 0x00022222 415 #define ADF_C4XXX_CD_RF_PARITY_ERR_3_VAL 0x00000000 416 #define ADF_C4XXX_CD_UERR_VAL 0x00000008 417 #define ADF_C4XXX_CD_CERR_VAL 0x00000008 418 #define ADF_C4XXX_PARSER_UERR_VAL 0x00100008 419 #define ADF_C4XXX_PARSER_CERR_VAL 0x00000008 420 #define ADF_C4XXX_INLN_RF_PARITY_ERR_0_VAL 0x33333333 421 #define ADF_C4XXX_INLN_RF_PARITY_ERR_1_VAL 0x33333333 422 #define ADF_C4XXX_INLN_RF_PARITY_ERR_2_VAL 0x33333333 423 #define ADF_C4XXX_INLN_RF_PARITY_ERR_3_VAL 0x22222222 424 #define ADF_C4XXX_INLN_RF_PARITY_ERR_4_VAL 0x22222222 425 #define ADF_C4XXX_INLN_RF_PARITY_ERR_5_VAL 0x00333232 426 #define ADF_C4XXX_CTPB_UERR_VAL 0x00000008 427 #define ADF_C4XXX_CTPB_CERR_VAL 0x00000008 428 #define ADF_C4XXX_CPPM_ERR_STAT_VAL 0x00007000 429 #define ADF_C4XXX_CPPT_ERR_STAT_VAL 0x000001C0 430 #define ADF_C4XXX_CONGESTION_MGMT_INI_VAL 0x00000001 431 #define ADF_C4XXX_MAC_IM_VAL 0x000000087FDC003E 432 433 /* parser ram ecc uerr */ 434 #define ADF_C4XXX_PARSER_UERR_INTR BIT(0) 435 /* multiple err */ 436 #define ADF_C4XXX_PARSER_MUL_UERR_INTR BIT(18) 437 #define ADF_C4XXX_PARSER_DESC_UERR_INTR_ENA BIT(20) 438 439 #define ADF_C4XXX_RF_PAR_ERR_BITS 32 440 #define ADF_C4XXX_MAX_STR_LEN 64 441 #define RF_PAR_MUL_MAP(bit_num) (((bit_num)-2) / 4) 442 #define RF_PAR_MAP(bit_num) (((bit_num)-3) / 4) 443 444 /* cd rf parity error 445 * BIT(2) rf parity mul 0 446 * BIT(3) rf parity 0 447 * BIT(10) rf parity mul 2 448 * BIT(11) rf parity 2 449 */ 450 #define ADF_C4XXX_CD_RF_PAR_ERR_1_INTR (BIT(2) | BIT(3) | BIT(10) | BIT(11)) 451 452 /* inln rf parity error 453 * BIT(2) rf parity mul 0 454 * BIT(3) rf parity 0 455 * BIT(6) rf parity mul 1 456 * BIT(7) rf parity 1 457 * BIT(10) rf parity mul 2 458 * BIT(11) rf parity 2 459 * BIT(14) rf parity mul 3 460 * BIT(15) rf parity 3 461 * BIT(18) rf parity mul 4 462 * BIT(19) rf parity 4 463 * BIT(22) rf parity mul 5 464 * BIT(23) rf parity 5 465 * BIT(26) rf parity mul 6 466 * BIT(27) rf parity 6 467 * BIT(30) rf parity mul 7 468 * BIT(31) rf parity 7 469 */ 470 #define ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR \ 471 (BIT(2) | BIT(3) | BIT(6) | BIT(7) | BIT(10) | BIT(11) | BIT(14) | \ 472 BIT(15) | BIT(18) | BIT(19) | BIT(22) | BIT(23) | BIT(26) | BIT(27) | \ 473 BIT(30) | BIT(31)) 474 #define ADF_C4XXX_INLN_RF_PAR_ERR_1_INTR ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR 475 #define ADF_C4XXX_INLN_RF_PAR_ERR_2_INTR ADF_C4XXX_INLN_RF_PAR_ERR_0_INTR 476 #define ADF_C4XXX_INLN_RF_PAR_ERR_5_INTR \ 477 (BIT(6) | BIT(7) | BIT(14) | BIT(15) | BIT(18) | BIT(19) | BIT(22) | \ 478 BIT(23)) 479 480 /* Congestion mgmt events */ 481 #define ADF_C4XXX_CONGESTION_MGMT_CTPB_GLOBAL_CROSSED BIT(1) 482 #define ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_OUT BIT(2) 483 #define ADF_C4XXX_CONGESTION_MGMT_XOFF_CIRQ_IN BIT(3) 484 485 /* AEAD algorithm definitions in REG_SA_SCRATCH[0] register. 486 * Bits<6:5> are reserved for expansion. 487 */ 488 #define AES128_GCM BIT(0) 489 #define AES192_GCM BIT(1) 490 #define AES256_GCM BIT(2) 491 #define AES128_CCM BIT(3) 492 #define CHACHA20_POLY1305 BIT(4) 493 /* Cipher algorithm definitions in REG_SA_SCRATCH[0] register 494 * Bit<15> is reserved for expansion. 495 */ 496 #define CIPHER_NULL BIT(7) 497 #define AES128_CBC BIT(8) 498 #define AES192_CBC BIT(9) 499 #define AES256_CBC BIT(10) 500 #define AES128_CTR BIT(11) 501 #define AES192_CTR BIT(12) 502 #define AES256_CTR BIT(13) 503 #define _3DES_CBC BIT(14) 504 /* Authentication algorithm definitions in REG_SA_SCRATCH[0] register 505 * Bits<25:30> are reserved for expansion. 506 */ 507 #define HMAC_MD5_96 BIT(16) 508 #define HMAC_SHA1_96 BIT(17) 509 #define HMAC_SHA256_128 BIT(18) 510 #define HMAC_SHA384_192 BIT(19) 511 #define HMAC_SHA512_256 BIT(20) 512 #define AES_GMAC_AES_128 BIT(21) 513 #define AES_XCBC_MAC_96 BIT(22) 514 #define AES_CMAC_96 BIT(23) 515 #define AUTH_NULL BIT(24) 516 517 /* Algo group0:DEFAULT */ 518 #define ADF_C4XXX_DEFAULT_SUPPORTED_ALGORITHMS \ 519 (AES128_GCM | \ 520 (AES192_GCM | AES256_GCM | AES128_CCM | CHACHA20_POLY1305) | \ 521 (CIPHER_NULL | AES128_CBC | AES192_CBC | AES256_CBC) | \ 522 (AES128_CTR | AES192_CTR | AES256_CTR | _3DES_CBC) | \ 523 (HMAC_MD5_96 | HMAC_SHA1_96 | HMAC_SHA256_128) | \ 524 (HMAC_SHA384_192 | HMAC_SHA512_256 | AES_GMAC_AES_128) | \ 525 (AES_XCBC_MAC_96 | AES_CMAC_96 | AUTH_NULL)) 526 527 /* Algo group1 */ 528 #define ADF_C4XXX_SUPPORTED_ALGORITHMS_GROUP1 \ 529 (AES128_GCM | (AES256_GCM | CHACHA20_POLY1305)) 530 531 /* Supported crypto offload features in REG_SA_SCRATCH[2] register */ 532 #define ADF_C4XXX_IPSEC_ESP BIT(0) 533 #define ADF_C4XXX_IPSEC_AH BIT(1) 534 #define ADF_C4XXX_UDP_ENCAPSULATION BIT(2) 535 #define ADF_C4XXX_IPSEC_TUNNEL_MODE BIT(3) 536 #define ADF_C4XXX_IPSEC_TRANSPORT_MODE BIT(4) 537 #define ADF_C4XXX_IPSEC_EXT_SEQ_NUM BIT(5) 538 539 #define ADF_C4XXX_DEFAULT_CY_OFFLOAD_FEATURES \ 540 (ADF_C4XXX_IPSEC_ESP | \ 541 (ADF_C4XXX_UDP_ENCAPSULATION | ADF_C4XXX_IPSEC_TUNNEL_MODE) | \ 542 (ADF_C4XXX_IPSEC_TRANSPORT_MODE | ADF_C4XXX_IPSEC_EXT_SEQ_NUM)) 543 544 /* REG_SA_CTRL_LOCK default value */ 545 #define ADF_C4XXX_DEFAULT_SA_CTRL_LOCKOUT BIT(0) 546 547 /* SA ENTRY CTRL default values */ 548 #define ADF_C4XXX_DEFAULT_LU_KEY_LEN 21 549 550 /* Sa size for algo group0 */ 551 #define ADF_C4XXX_DEFAULT_SA_SIZE 6 552 553 /* Sa size for algo group1 */ 554 #define ADF_C4XXX_ALGO_GROUP1_SA_SIZE 2 555 556 /* SA size is based on 32byte granularity 557 * A value of zero indicates an SA size of 32 bytes 558 */ 559 #define ADF_C4XXX_SA_SIZE_IN_BYTES(sa_size) (((sa_size) + 1) * 32) 560 561 /* SA ENTRY CTRL register bit offsets */ 562 #define ADF_C4XXX_LU_KEY_LEN_BIT_OFFSET 5 563 564 /* REG_SA_FUNC_LIMITS default value */ 565 #define ADF_C4XXX_FUNC_LIMIT(accel_dev, sa_size) \ 566 (ADF_C4XXX_SADB_SIZE_IN_WORDS(accel_dev) / ((sa_size) + 1)) 567 568 /* REG_SA_INLINE_ENABLE bit definition */ 569 #define ADF_C4XXX_INLINE_ENABLED BIT(0) 570 571 /* REG_SA_INLINE_CAPABILITY bit definitions */ 572 #define ADF_C4XXX_INLINE_INGRESS_ENABLE BIT(0) 573 #define ADF_C4XXX_INLINE_EGRESS_ENABLE BIT(1) 574 #define ADF_C4XXX_INLINE_CAPABILITIES \ 575 (ADF_C4XXX_INLINE_INGRESS_ENABLE | ADF_C4XXX_INLINE_EGRESS_ENABLE) 576 577 /* Congestion management profile information */ 578 enum congest_mngt_profile_info { 579 CIRQ_CFG_1 = 0, 580 CIRQ_CFG_2, 581 CIRQ_CFG_3, 582 BEST_EFFORT_SINGLE_QUEUE, 583 BEST_EFFORT_8_QUEUES, 584 }; 585 586 /* IPsec Algo Group */ 587 enum ipsec_algo_group_info { 588 IPSEC_DEFAUL_ALGO_GROUP = 0, 589 IPSEC_ALGO_GROUP1, 590 IPSEC_ALGO_GROUP_DELIMITER 591 }; 592 593 int get_congestion_management_profile(struct adf_accel_dev *accel_dev, 594 u8 *profile); 595 int c4xxx_init_congestion_management(struct adf_accel_dev *accel_dev); 596 int c4xxx_init_debugfs_inline_dir(struct adf_accel_dev *accel_dev); 597 void c4xxx_exit_debugfs_inline_dir(struct adf_accel_dev *accel_dev); 598 #endif /* ADF_C4XXX_INLINE_H_ */ 599