1 /* 2 * AuthenTec AES2501 driver for libfprint 3 * Copyright (C) 2007 Cyrille Bagard 4 * 5 * Based on code from http://home.gna.org/aes2501, relicensed with permission 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #ifndef __AES2501_H 23 #define __AES2501_H 24 25 enum aes2501_regs { 26 AES2501_REG_CTRL1 = 0x80, 27 AES2501_REG_CTRL2 = 0x81, 28 AES2501_REG_EXCITCTRL = 0x82, /* excitation control */ 29 AES2501_REG_DETCTRL = 0x83, /* detect control */ 30 AES2501_REG_COLSCAN = 0x88, /* column scan rate register */ 31 AES2501_REG_MEASDRV = 0x89, /* measure drive */ 32 AES2501_REG_MEASFREQ = 0x8a, /* measure frequency */ 33 AES2501_REG_DEMODPHASE1 = 0x8d, 34 AES2501_REG_DEMODPHASE2 = 0x8c, 35 AES2501_REG_CHANGAIN = 0x8e, /* channel gain */ 36 AES2501_REG_ADREFHI = 0x91, /* A/D reference high */ 37 AES2501_REG_ADREFLO = 0x92, /* A/D reference low */ 38 AES2501_REG_STRTROW = 0x93, /* start row */ 39 AES2501_REG_ENDROW = 0x94, /* end row */ 40 AES2501_REG_STRTCOL = 0x95, /* start column */ 41 AES2501_REG_ENDCOL = 0x96, /* end column */ 42 AES2501_REG_DATFMT = 0x97, /* data format */ 43 AES2501_REG_IMAGCTRL = 0x98, /* image data */ 44 AES2501_REG_STAT = 0x9a, 45 AES2501_REG_CHWORD1 = 0x9b, /* challenge word 1 */ 46 AES2501_REG_CHWORD2 = 0x9c, 47 AES2501_REG_CHWORD3 = 0x9d, 48 AES2501_REG_CHWORD4 = 0x9e, 49 AES2501_REG_CHWORD5 = 0x9f, 50 AES2501_REG_TREG1 = 0xa1, /* test register 1 */ 51 AES2501_REG_AUTOCALOFFSET = 0xa8, 52 AES2501_REG_TREGC = 0xac, 53 AES2501_REG_TREGD = 0xad, 54 AES2501_REG_LPONT = 0xb4, /* low power oscillator on time */ 55 }; 56 57 #define FIRST_AES2501_REG AES2501_REG_CTRL1 58 #define LAST_AES2501_REG AES2501_REG_CHWORD5 59 60 #define AES2501_CTRL1_MASTER_RESET (1<<0) 61 #define AES2501_CTRL1_SCAN_RESET (1<<1) /* stop + restart scan sequencer */ 62 /* 1 = continuously updated, 0 = updated prior to starting a scan */ 63 #define AES2501_CTRL1_REG_UPDATE (1<<2) 64 65 /* 1 = continuous scans, 0 = single scans */ 66 #define AES2501_CTRL2_CONTINUOUS 0x01 67 #define AES2501_CTRL2_READ_REGS 0x02 /* dump registers */ 68 #define AES2501_CTRL2_SET_ONE_SHOT 0x04 69 #define AES2501_CTRL2_CLR_ONE_SHOT 0x08 70 #define AES2501_CTRL2_READ_ID 0x10 71 72 enum aes2501_detection_rate { 73 /* rate of detection cycles: */ 74 AES2501_DETCTRL_DRATE_CONTINUOUS = 0x00, /* continuously */ 75 AES2501_DETCTRL_DRATE_16_MS = 0x01, /* every 16.62ms */ 76 AES2501_DETCTRL_DRATE_31_MS = 0x02, /* every 31.24ms */ 77 AES2501_DETCTRL_DRATE_62_MS = 0x03, /* every 62.50ms */ 78 AES2501_DETCTRL_DRATE_125_MS = 0x04, /* every 125.0ms */ 79 AES2501_DETCTRL_DRATE_250_MS = 0x05, /* every 250.0ms */ 80 AES2501_DETCTRL_DRATE_500_MS = 0x06, /* every 500.0ms */ 81 AES2501_DETCTRL_DRATE_1_S = 0x07, /* every 1s */ 82 }; 83 84 enum aes2501_settling_delay { 85 AES2501_DETCTRL_SDELAY_31_MS = 0x00, /* 31.25ms */ 86 AES2501_DETCTRL_SSDELAY_62_MS = 0x10, /* 62.5ms */ 87 AES2501_DETCTRL_SSDELAY_125_MS = 0x20, /* 125ms */ 88 AES2501_DETCTRL_SSDELAY_250_MS = 0x30 /* 250ms */ 89 }; 90 91 enum aes2501_col_scan_rate { 92 AES2501_COLSCAN_SRATE_32_US = 0x00, /* 32us */ 93 AES2501_COLSCAN_SRATE_64_US = 0x01, /* 64us */ 94 AES2501_COLSCAN_SRATE_128_US = 0x02, /* 128us */ 95 AES2501_COLSCAN_SRATE_256_US = 0x03, /* 256us */ 96 AES2501_COLSCAN_SRATE_512_US = 0x04, /* 512us */ 97 AES2501_COLSCAN_SRATE_1024_US = 0x05, /* 1024us */ 98 AES2501_COLSCAN_SRATE_2048_US = 0x06, /* 2048us */ 99 100 }; 101 102 enum aes2501_mesure_drive { 103 AES2501_MEASDRV_MDRIVE_0_325 = 0x00, /* 0.325 Vpp */ 104 AES2501_MEASDRV_MDRIVE_0_65 = 0x01, /* 0.65 Vpp */ 105 AES2501_MEASDRV_MDRIVE_1_3 = 0x02, /* 1.3 Vpp */ 106 AES2501_MEASDRV_MDRIVE_2_6 = 0x03 /* 2.6 Vpp */ 107 108 }; 109 110 /* Select (1=square | 0=sine) wave drive during measure */ 111 #define AES2501_MEASDRV_SQUARE 0x20 112 /* 0 = use mesure drive setting, 1 = when sine wave is selected */ 113 #define AES2501_MEASDRV_MEASURE_SQUARE 0x10 114 115 enum aes2501_measure_freq { 116 AES2501_MEASFREQ_125K = 0x01, /* 125 kHz */ 117 AES2501_MEASFREQ_250K = 0x02, /* 250 kHz */ 118 AES2501_MEASFREQ_500K = 0x03, /* 500 kHz */ 119 AES2501_MEASFREQ_1M = 0x04, /* 1 MHz */ 120 AES2501_MEASFREQ_2M = 0x05 /* 2 MHz */ 121 }; 122 123 #define DEMODPHASE_NONE 0x00 124 #define DEMODPHASE_180_00 0x40 /* 180 degrees */ 125 #define DEMODPHASE_2_81 0x01 /* 2.8125 degrees */ 126 127 #define AES2501_REG_DEMODPHASE1 0x8d 128 #define DEMODPHASE_1_40 0x40 /* 1.40625 degrees */ 129 #define DEMODPHASE_0_02 0x01 /* 0.02197256 degrees */ 130 131 enum aes2501_sensor_gain1 { 132 AES2501_CHANGAIN_STAGE1_2X = 0x00, /* 2x */ 133 AES2501_CHANGAIN_STAGE1_4X = 0x01, /* 4x */ 134 AES2501_CHANGAIN_STAGE1_8X = 0x02, /* 8x */ 135 AES2501_CHANGAIN_STAGE1_16X = 0x03 /* 16x */ 136 }; 137 138 enum aes2501_sensor_gain2 { 139 AES2501_CHANGAIN_STAGE2_2X = 0x00, /* 2x */ 140 AES2501_CHANGAIN_STAGE2_4X = 0x10, /* 4x */ 141 AES2501_CHANGAIN_STAGE2_8X = 0x20, /* 8x */ 142 AES2501_CHANGAIN_STAGE2_16X = 0x30 /* 16x */ 143 }; 144 145 #define AES2501_DATFMT_EIGHT 0x40 /* 1 = 8-bit data, 0 = 4-bit data */ 146 #define AES2501_DATFMT_LOW_RES 0x20 147 #define AES2501_DATFMT_BIN_IMG 0x10 148 149 /* don't send image or authentication messages when imaging */ 150 #define AES2501_IMAGCTRL_IMG_DATA_DISABLE 0x01 151 /* send histogram when imaging */ 152 #define AES2501_IMAGCTRL_HISTO_DATA_ENABLE 0x02 153 /* send histogram at end of each row rather than each scan */ 154 #define AES2501_IMAGCTRL_HISTO_EACH_ROW 0x04 155 /* send full image array rather than 64x64 center */ 156 #define AES2501_IMAGCTRL_HISTO_FULL_ARRAY 0x08 157 /* return registers before data (rather than after) */ 158 #define AES2501_IMAGCTRL_REG_FIRST 0x10 159 /* return test registers with register dump */ 160 #define AES2501_IMAGCTRL_TST_REG_ENABLE 0x20 161 162 #define AES2501_CHWORD1_IS_FINGER 0x01 /* If set, finger is present */ 163 164 /* Enable the reading of the register in TREGD */ 165 #define AES2501_TREGC_ENABLE 0x01 166 167 #define AES2501_LPONT_MIN_VALUE 0x00 /* 0 ms */ 168 #define AES2501_LPONT_MAX_VALUE 0x1f /* About 16 ms */ 169 170 #define AES2501_ADREFHI_MIN_VALUE 0x28 171 #define AES2501_ADREFHI_MAX_VALUE 0x58 172 173 #define AES2501_SUM_HIGH_THRESH 1000 174 #define AES2501_SUM_LOW_THRESH 700 175 176 #endif /* __AES2501_H */ 177