xref: /dragonfly/sys/dev/netif/ae/if_aereg.h (revision 86d7f5d3)
1 /*-
2  * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  *
25  * $FreeBSD: src/sys/dev/ae/if_aereg.h,v 1.1.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
26  */
27 
28 /*
29  * Master configuration register
30  */
31 #define	AE_MASTER_REG		0x1400
32 
33 #define	AE_MASTER_SOFT_RESET	0x1	/* Reset adapter. */
34 #define	AE_MASTER_MTIMER_EN	0x2	/* Unknown. */
35 #define	AE_MASTER_IMT_EN	0x4	/* Interrupt moderation timer enable. */
36 #define	AE_MASTER_MANUAL_INT	0x8	/* Software manual interrupt. */
37 #define	AE_MASTER_REVNUM_SHIFT	16	/* Chip revision number. */
38 #define	AE_MASTER_REVNUM_MASK	0xff
39 #define	AE_MASTER_DEVID_SHIFT	24	/* PCI device id. */
40 #define	AE_MASTER_DEVID_MASK	0xff
41 
42 /*
43  * Interrupt status register
44  */
45 #define	AE_ISR_REG		0x1600
46 #define	AE_ISR_TIMER		0x00000001	/* Counter expired. */
47 #define	AE_ISR_MANUAL		0x00000002	/* Manual interrupt occuried. */
48 #define	AE_ISR_RXF_OVERFLOW	0x00000004	/* RxF overflow occuried. */
49 #define	AE_ISR_TXF_UNDERRUN	0x00000008	/* TxF underrun occuried. */
50 #define	AE_ISR_TXS_OVERFLOW	0x00000010	/* TxS overflow occuried. */
51 #define	AE_ISR_RXS_OVERFLOW	0x00000020	/* Internal RxS ring overflow. */
52 #define	AE_ISR_LINK_CHG		0x00000040	/* Link state changed. */
53 #define	AE_ISR_TXD_UNDERRUN	0x00000080	/* TxD underrun occuried. */
54 #define	AE_ISR_RXD_OVERFLOW	0x00000100	/* RxD overflow occuried. */
55 #define	AE_ISR_DMAR_TIMEOUT	0x00000200	/* DMA read timeout. */
56 #define	AE_ISR_DMAW_TIMEOUT	0x00000400	/* DMA write timeout. */
57 #define	AE_ISR_PHY		0x00000800	/* PHY interrupt. */
58 #define	AE_ISR_TXS_UPDATED	0x00010000	/* Tx status updated. */
59 #define	AE_ISR_RXD_UPDATED	0x00020000	/* Rx status updated. */
60 #define	AE_ISR_TX_EARLY		0x00040000	/* TxMAC started transmit. */
61 #define	AE_ISR_FIFO_UNDERRUN	0x01000000	/* FIFO underrun. */
62 #define	AE_ISR_FRAME_ERROR	0x02000000	/* Frame receive error. */
63 #define	AE_ISR_FRAME_SUCCESS	0x04000000	/* Frame receive success. */
64 #define	AE_ISR_CRC_ERROR	0x08000000	/* CRC error occuried. */
65 #define	AE_ISR_PHY_LINKDOWN	0x10000000	/* PHY link down. */
66 #define	AE_ISR_DISABLE		0x80000000	/* Disable interrupts. */
67 
68 #define	AE_ISR_TX_EVENT		(AE_ISR_TXF_UNDERRUN | AE_ISR_TXS_OVERFLOW | \
69 				 AE_ISR_TXD_UNDERRUN | AE_ISR_TXS_UPDATED | \
70 				 AE_ISR_TX_EARLY)
71 #define	AE_ISR_RX_EVENT		(AE_ISR_RXF_OVERFLOW | AE_ISR_RXS_OVERFLOW | \
72 				 AE_ISR_RXD_OVERFLOW | AE_ISR_RXD_UPDATED)
73 
74 /* Interrupt mask register. */
75 #define	AE_IMR_REG		0x1604
76 
77 #define	AE_IMR_DEFAULT		(AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | \
78 				 AE_ISR_PHY_LINKDOWN | \
79 				 AE_ISR_TXS_UPDATED | AE_ISR_RXD_UPDATED )
80 
81 /*
82  * Ethernet address register.
83  */
84 #define	AE_EADDR0_REG		0x1488	/* 5 - 2 bytes */
85 #define	AE_EADDR1_REG		0x148c	/* 1 - 0 bytes */
86 
87 /*
88  * Desriptor rings registers.
89  * L2 supports 64-bit addressing but all rings base addresses
90  * should have the same high 32 bits of address.
91  */
92 #define	AE_DESC_ADDR_HI_REG	0x1540	/* High 32 bits of ring base address. */
93 #define	AE_RXD_ADDR_LO_REG	0x1554	/* Low 32 bits of RxD ring address. */
94 #define	AE_TXD_ADDR_LO_REG	0x1544	/* Low 32 bits of TxD ring address. */
95 #define	AE_TXS_ADDR_LO_REG	0x154c	/* Low 32 bits of TxS ring address. */
96 #define	AE_RXD_COUNT_REG	0x1558	/* Number of RxD descriptors in ring.
97 					   Should be 120-byte aligned (i.e.
98 					   the 'data' field of RxD should
99 					   have 128-byte alignment). */
100 #define	AE_TXD_BUFSIZE_REG	0x1548	/* Size of TxD ring in 4-byte units.
101 					   Should be 4-byte aligned. */
102 #define	AE_TXS_COUNT_REG	0x1550	/* Number of TxS descriptors in ring.
103 					   4 byte alignment. */
104 #define	AE_RXD_COUNT_MIN	16
105 #define	AE_RXD_COUNT_MAX	512
106 #define	AE_RXD_COUNT_DEFAULT	64
107 
108 #define	AE_TXD_BUFSIZE_MIN	4096
109 #define	AE_TXD_BUFSIZE_MAX	65536
110 #define	AE_TXD_BUFSIZE_DEFAULT	8192
111 
112 #define	AE_TXS_COUNT_MIN	8	/* Not sure. */
113 #define	AE_TXS_COUNT_MAX	160
114 #define	AE_TXS_COUNT_DEFAULT	64	/* AE_TXD_BUFSIZE_DEFAULT / 128 */
115 
116 /*
117  * Inter-frame gap configuration register.
118  */
119 #define	AE_IFG_REG		0x1484
120 
121 #define	AE_IFG_TXIPG_DEFAULT	0x60	/* 96-bit IFG time. */
122 #define	AE_IFG_TXIPG_SHIFT	0
123 #define	AE_IFG_TXIPG_MASK	0x7f
124 
125 #define	AE_IFG_RXIPG_DEFAULT	0x50	/* 80-bit IFG time. */
126 #define	AE_IFG_RXIPG_SHIFT	8
127 #define	AE_IFG_RXIPG_MASK	0xff00
128 
129 #define	AE_IFG_IPGR1_DEFAULT	0x40	/* Carrier-sense window. */
130 #define	AE_IFG_IPGR1_SHIFT	16
131 #define	AE_IFG_IPGR1_MASK	0x7f0000
132 
133 #define	AE_IFG_IPGR2_DEFAULT	0x60	/* IFG window. */
134 #define	AE_IFG_IPGR2_SHIFT	24
135 #define	AE_IFG_IPGR2_MASK	0x7f000000
136 
137 /*
138  * Half-duplex mode configuration register.
139  */
140 #define	AE_HDPX_REG		0x1498
141 
142 /* Collision window. */
143 #define	AE_HDPX_LCOL_SHIFT	0
144 #define	AE_HDPX_LCOL_MASK	0x000003ff
145 #define	AE_HDPX_LCOL_DEFAULT	0x37
146 
147 /* Max retransmission time, after that the packet will be discarded. */
148 #define	AE_HDPX_RETRY_SHIFT	12
149 #define	AE_HDPX_RETRY_MASK	0x0000f000
150 #define	AE_HDPX_RETRY_DEFAULT	0x0f
151 
152 /* Alternative binary exponential back-off time. */
153 #define	AE_HDPX_ABEBT_SHIFT	20
154 #define	AE_HDPX_ABEBT_MASK	0x00f00000
155 #define	AE_HDPX_ABEBT_DEFAULT	0x0a
156 
157 /* IFG to start JAM for collision based flow control (8-bit time units).*/
158 #define	AE_HDPX_JAMIPG_SHIFT	24
159 #define	AE_HDPX_JAMIPG_MASK	0x0f000000
160 #define	AE_HDPX_JAMIPG_DEFAULT	0x07
161 
162 /* Allow the transmission of a packet which has been excessively deferred. */
163 #define	AE_HDPX_EXC_EN		0x00010000
164 /* No back-off on collision, immediately start the retransmission. */
165 #define	AE_HDPX_NO_BACK_C	0x00020000
166 /* No back-off on backpressure, immediately start the transmission. */
167 #define	AE_HDPX_NO_BACK_P	0x00040000
168 /* Alternative binary exponential back-off enable. */
169 #define	AE_HDPX_ABEBE		0x00080000
170 
171 /*
172  * Interrupt moderation timer configuration register.
173  */
174 #define	AE_IMT_REG		0x1408	/* Timer value in 2 us units. */
175 #define	AE_IMT_MAX		65000
176 #define	AE_IMT_MIN		50
177 #define	AE_IMT_DEFAULT		100	/* 200 microseconds. */
178 
179 /*
180  * Interrupt clearing timer configuration register.
181  */
182 #define	AE_ICT_REG		0x140e	/* Maximum time allowed to clear
183 					   interrupt. In 2 us units.  */
184 #define	AE_ICT_DEFAULT		50000	/* 100ms */
185 
186 /*
187  * MTU configuration register.
188  */
189 #define	AE_MTU_REG		0x149c	/* MTU size in bytes. */
190 
191 /*
192  * Cut-through configuration register.
193  */
194 #define	AE_CUT_THRESH_REG	0x1590	/* Cut-through threshold in unknown units. */
195 #define	AE_CUT_THRESH_DEFAULT   0x177
196 
197 /*
198  * Flow-control configuration registers.
199  */
200 #define	AE_FLOW_THRESH_HI_REG	0x15a8	/* High watermark of RxD
201 					   overflow threshold. */
202 #define	AE_FLOW_THRESH_LO_REG	0x15aa	/* Lower watermark of RxD
203 					   overflow threshold */
204 
205 /*
206  * Mailbox configuration registers.
207 */
208 #define	AE_MB_TXD_IDX_REG	0x15f0	/* TxD read index. */
209 #define	AE_MB_RXD_IDX_REG	0x15f4	/* RxD write index. */
210 
211 /*
212  * DMA configuration registers.
213  */
214 #define	AE_DMAREAD_REG		0x1580	/* Read DMA configuration register. */
215 #define	AE_DMAREAD_EN		1
216 #define	AE_DMAWRITE_REG		0x15a0	/* Write DMA configuration register. */
217 #define	AE_DMAWRITE_EN		1
218 
219 /*
220  * MAC configuration register.
221  */
222 #define	AE_MAC_REG		0x1480
223 
224 #define	AE_MAC_TX_EN		0x00000001	/* Enable transmit. */
225 #define	AE_MAC_RX_EN		0x00000002	/* Enable receive. */
226 #define	AE_MAC_TX_FLOW_EN	0x00000004	/* Enable Tx flow control. */
227 #define	AE_MAC_RX_FLOW_EN	0x00000008	/* Enable Rx flow control. */
228 #define	AE_MAC_LOOPBACK		0x00000010	/* Loopback at MII. */
229 #define	AE_MAC_FULL_DUPLEX	0x00000020	/* Enable full-duplex. */
230 #define	AE_MAC_TX_CRC_EN	0x00000040	/* Enable CRC generation. */
231 #define	AE_MAC_TX_AUTOPAD	0x00000080	/* Pad short frames. */
232 #define	AE_MAC_PREAMBLE_MASK	0x00003c00	/* Preamble length. */
233 #define	AE_MAC_PREAMBLE_SHIFT	10
234 #define	AE_MAC_PREAMBLE_DEFAULT	0x07		/* By standard. */
235 #define	AE_MAC_RMVLAN_EN	0x00004000	/* Remove VLAN tags in
236 						   incoming packets. */
237 #define	AE_MAC_PROMISC_EN	0x00008000	/* Enable promiscue mode. */
238 #define	AE_MAC_TX_MAXBACKOFF	0x00100000	/* Unknown. */
239 #define	AE_MAC_MCAST_EN		0x02000000	/* Pass all multicast frames. */
240 #define	AE_MAC_BCAST_EN		0x04000000	/* Pass all broadcast frames. */
241 #define	AE_MAC_CLK_PHY		0x08000000	/* If 1 uses loopback clock
242 						   PHY, if 0 - system clock. */
243 #define	AE_HALFBUF_MASK		0xf0000000	/* Half-duplex retry buffer. */
244 #define	AE_HALFBUF_SHIFT	28
245 #define	AE_HALFBUF_DEFAULT	2		/* XXX: From Linux. */
246 
247 /*
248  * MDIO control register.
249  */
250 #define	AE_MDIO_REG		0x1414
251 #define	AE_MDIO_DATA_MASK	0xffff
252 #define	AE_MDIO_DATA_SHIFT	0
253 #define	AE_MDIO_REGADDR_MASK	0x1f0000
254 #define	AE_MDIO_REGADDR_SHIFT	16
255 #define	AE_MDIO_READ		0x00200000	/* Read operation. */
256 #define	AE_MDIO_SUP_PREAMBLE	0x00400000	/* Suppress preamble. */
257 #define	AE_MDIO_START		0x00800000	/* Initiate MDIO transfer. */
258 #define	AE_MDIO_CLK_SHIFT	24		/* Clock selection. */
259 #define	AE_MDIO_CLK_MASK	0x07000000	/* Clock selection. */
260 #define	AE_MDIO_CLK_25_4	0		/* Dividers? */
261 #define	AE_MDIO_CLK_25_6	2
262 #define	AE_MDIO_CLK_25_8	3
263 #define	AE_MDIO_CLK_25_10	4
264 #define	AE_MDIO_CLK_25_14	5
265 #define	AE_MDIO_CLK_25_20	6
266 #define	AE_MDIO_CLK_25_28	7
267 #define	AE_MDIO_BUSY		0x08000000	/* MDIO is busy. */
268 
269 /*
270  * Idle status register.
271  */
272 #define	AE_IDLE_REG		0x1410
273 
274 /*
275  * Idle status bits.
276  * If bit is set then the corresponding module is in non-idle state.
277  */
278 #define	AE_IDLE_RXMAC		1
279 #define	AE_IDLE_TXMAC		2
280 #define	AE_IDLE_DMAREAD		8
281 #define	AE_IDLE_DMAWRITE	4
282 
283 /*
284  * Multicast hash tables registers.
285  */
286 #define	AE_REG_MHT0		0x1490
287 #define	AE_REG_MHT1		0x1494
288 
289 /*
290  * Wake on lan (WOL).
291  */
292 #define	AE_WOL_REG		0x14a0
293 #define	AE_WOL_MAGIC		0x00000004
294 #define	AE_WOL_MAGIC_PME	0x00000008
295 #define	AE_WOL_LNKCHG		0x00000010
296 #define	AE_WOL_LNKCHG_PME	0x00000020
297 
298 /*
299  * PCIE configuration registers. Descriptions unknown.
300  */
301 #define	AE_PCIE_LTSSM_TESTMODE_REG	0x12fc
302 #define	AE_PCIE_LTSSM_TESTMODE_DEFAULT	0x6500
303 #define	AE_PCIE_DLL_TX_CTRL_REG		0x1104
304 #define	AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK	0x0400
305 #define	AE_PCIE_DLL_TX_CTRL_DEFAULT	0x0568
306 #define	AE_PCIE_PHYMISC_REG		0x1000
307 #define	AE_PCIE_PHYMISC_FORCE_RCV_DET	0x4
308 
309 /*
310  * PHY enable register.
311  */
312 #define	AE_PHY_ENABLE_REG	0x140c
313 #define	AE_PHY_ENABLE		1
314 
315 /*
316  * VPD registers.
317  */
318 #define	AE_VPD_CAP_REG		0x6c	/* Command register. */
319 #define	AE_VPD_CAP_ID_MASK	0xff
320 #define	AE_VPD_CAP_ID_SHIFT	0
321 #define	AE_VPD_CAP_NEXT_MASK	0xff00
322 #define	AE_VPD_CAP_NEXT_SHIFT	8
323 #define	AE_VPD_CAP_ADDR_MASK	0x7fff0000
324 #define	AE_VPD_CAP_ADDR_SHIFT	16
325 #define	AE_VPD_CAP_DONE		0x80000000
326 #define	AE_VPD_DATA_REG		0x70	/* Data register. */
327 
328 #define	AE_VPD_NREGS		64	/* Maximum number of VPD regs. */
329 #define	AE_VPD_SIG_MASK		0xff
330 #define	AE_VPD_SIG		0x5a	/* VPD block signature. */
331 #define	AE_VPD_REG_SHIFT	16	/* Register id offset. */
332 
333 /*
334  * SPI registers.
335  */
336 #define	AE_SPICTL_REG		0x200
337 #define	AE_SPICTL_VPD_EN	0x2000	/* Enable VPD. */
338 
339 /*
340  * PHY-specific registers constants.
341  */
342 #define	AE_PHY_DBG_ADDR		0x1d
343 #define	AE_PHY_DBG_DATA		0x1e
344 #define	AE_PHY_DBG_POWERSAVE	0x1000
345 
346 /*
347  * TxD flags.
348  */
349 #define	AE_TXD_INSERT_VTAG	0x8000	/* Insert VLAN tag on transfer. */
350 
351 /*
352  * TxS flags.
353  */
354 #define	AE_TXS_SUCCESS		0x0001	/* Packed transmitted successfully. */
355 #define	AE_TXS_BCAST		0x0002	/* Transmitted broadcast frame. */
356 #define	AE_TXS_MCAST		0x0004	/* Transmitted multicast frame. */
357 #define	AE_TXS_PAUSE		0x0008	/* Transmitted pause frame. */
358 #define	AE_TXS_CTRL		0x0010	/* Transmitted control frame. */
359 #define	AE_TXS_DEFER		0x0020	/* Frame transmitted with defer. */
360 #define	AE_TXS_EXCDEFER		0x0040	/* Excessive collision. */
361 #define	AE_TXS_SINGLECOL	0x0080	/* Single collision occuried. */
362 #define	AE_TXS_MULTICOL		0x0100	/* Multiple collisions occuried. */
363 #define	AE_TXS_LATECOL		0x0200	/* Late collision occuried. */
364 #define	AE_TXS_ABORTCOL		0x0400	/* Frame abort due to collisions. */
365 #define	AE_TXS_UNDERRUN		0x0800	/* Tx SRAM underrun occuried. */
366 #define	AE_TXS_UPDATE		0x8000
367 
368 /*
369  * RxD flags.
370  */
371 #define	AE_RXD_SUCCESS		0x0001
372 #define	AE_RXD_BCAST		0x0002	/* Broadcast frame received. */
373 #define	AE_RXD_MCAST		0x0004	/* Multicast frame received. */
374 #define	AE_RXD_PAUSE		0x0008	/* Pause frame received. */
375 #define	AE_RXD_CTRL		0x0010	/* Control frame received. */
376 #define	AE_RXD_CRCERR		0x0020	/* Invalid frame CRC. */
377 #define	AE_RXD_CODEERR		0x0040	/* Invalid frame opcode. */
378 #define	AE_RXD_RUNT		0x0080	/* Runt frame received. */
379 #define	AE_RXD_FRAG		0x0100	/* Collision fragment received. */
380 #define	AE_RXD_TRUNC		0x0200	/* The frame was truncated due
381 					   to Rx SRAM underrun. */
382 #define	AE_RXD_ALIGN		0x0400	/* Frame alignment error. */
383 #define	AE_RXD_HAS_VLAN		0x0800	/* VLAN tag present. */
384 #define	AE_RXD_UPDATE		0x8000
385