xref: /freebsd/sys/dev/age/if_agereg.h (revision 95ee2897)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice unmodified, this list of conditions, and the following
12  *    disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 #ifndef	_IF_AGEREG_H
31 #define	_IF_AGEREG_H
32 
33 /*
34  * Attansic Technology Corp. PCI vendor ID
35  */
36 #define	VENDORID_ATTANSIC		0x1969
37 
38 /*
39  * Attansic L1 device ID
40  */
41 #define	DEVICEID_ATTANSIC_L1		0x1048
42 
43 #define	AGE_VPD_REG_CONF_START		0x0100
44 #define	AGE_VPD_REG_CONF_END		0x01FF
45 #define	AGE_VPD_REG_CONF_SIG		0x5A
46 
47 #define	AGE_SPI_CTRL			0x200
48 #define	SPI_STAT_NOT_READY		0x00000001
49 #define	SPI_STAT_WR_ENB			0x00000002
50 #define	SPI_STAT_WRP_ENB		0x00000080
51 #define	SPI_INST_MASK			0x000000FF
52 #define	SPI_START			0x00000100
53 #define	SPI_INST_START			0x00000800
54 #define	SPI_VPD_ENB			0x00002000
55 #define	SPI_LOADER_START		0x00008000
56 #define	SPI_CS_HI_MASK			0x00030000
57 #define	SPI_CS_HOLD_MASK		0x000C0000
58 #define	SPI_CLK_LO_MASK			0x00300000
59 #define	SPI_CLK_HI_MASK			0x00C00000
60 #define	SPI_CS_SETUP_MASK		0x03000000
61 #define	SPI_EPROM_PG_MASK		0x0C000000
62 #define	SPI_INST_SHIFT			8
63 #define	SPI_CS_HI_SHIFT			16
64 #define	SPI_CS_HOLD_SHIFT		18
65 #define	SPI_CLK_LO_SHIFT		20
66 #define	SPI_CLK_HI_SHIFT		22
67 #define	SPI_CS_SETUP_SHIFT		24
68 #define	SPI_EPROM_PG_SHIFT		26
69 #define	SPI_WAIT_READY			0x10000000
70 
71 #define	AGE_SPI_ADDR			0x204	/* 16bits */
72 
73 #define	AGE_SPI_DATA			0x208
74 
75 #define	AGE_SPI_CONFIG			0x20C
76 
77 #define	AGE_SPI_OP_PROGRAM		0x210	/* 8bits */
78 
79 #define	AGE_SPI_OP_SC_ERASE		0x211	/* 8bits */
80 
81 #define	AGE_SPI_OP_CHIP_ERASE		0x212	/* 8bits */
82 
83 #define	AGE_SPI_OP_RDID			0x213	/* 8bits */
84 
85 #define	AGE_SPI_OP_WREN			0x214	/* 8bits */
86 
87 #define	AGE_SPI_OP_RDSR			0x215	/* 8bits */
88 
89 #define	AGE_SPI_OP_WRSR			0x216	/* 8bits */
90 
91 #define	AGE_SPI_OP_READ			0x217	/* 8bits */
92 
93 #define	AGE_TWSI_CTRL			0x218
94 #define	TWSI_CTRL_SW_LD_START		0x00000800
95 #define	TWSI_CTRL_HW_LD_START		0x00001000
96 #define	TWSI_CTRL_LD_EXIST		0x00400000
97 
98 #define AGE_DEV_MISC_CTRL		0x21C
99 
100 #define	AGE_MASTER_CFG			0x1400
101 #define	MASTER_RESET			0x00000001
102 #define	MASTER_MTIMER_ENB		0x00000002
103 #define	MASTER_ITIMER_ENB		0x00000004
104 #define	MASTER_MANUAL_INT_ENB		0x00000008
105 #define	MASTER_CHIP_REV_MASK		0x00FF0000
106 #define	MASTER_CHIP_ID_MASK		0xFF000000
107 #define	MASTER_CHIP_REV_SHIFT		16
108 #define	MASTER_CHIP_ID_SHIFT		24
109 
110 /* Number of ticks per usec for L1. */
111 #define	AGE_TICK_USECS			2
112 #define	AGE_USECS(x)			((x) / AGE_TICK_USECS)
113 
114 #define	AGE_MANUAL_TIMER		0x1404
115 
116 #define	AGE_IM_TIMER			0x1408	/* 16bits */
117 #define	AGE_IM_TIMER_MIN		0
118 #define	AGE_IM_TIMER_MAX		130000	/* 130ms */
119 #define	AGE_IM_TIMER_DEFAULT		100
120 
121 #define	AGE_GPHY_CTRL			0x140C	/* 16bits */
122 #define	GPHY_CTRL_RST			0x0000
123 #define	GPHY_CTRL_CLR			0x0001
124 
125 #define	AGE_INTR_CLR_TIMER		0x140E	/* 16bits */
126 
127 #define	AGE_IDLE_STATUS			0x1410
128 #define	IDLE_STATUS_RXMAC		0x00000001
129 #define	IDLE_STATUS_TXMAC		0x00000002
130 #define	IDLE_STATUS_RXQ			0x00000004
131 #define	IDLE_STATUS_TXQ			0x00000008
132 #define	IDLE_STATUS_DMARD		0x00000010
133 #define	IDLE_STATUS_DMAWR		0x00000020
134 #define	IDLE_STATUS_SMB			0x00000040
135 #define	IDLE_STATUS_CMB			0x00000080
136 
137 #define	AGE_MDIO			0x1414
138 #define	MDIO_DATA_MASK			0x0000FFFF
139 #define	MDIO_REG_ADDR_MASK		0x001F0000
140 #define	MDIO_OP_READ			0x00200000
141 #define	MDIO_OP_WRITE			0x00000000
142 #define	MDIO_SUP_PREAMBLE		0x00400000
143 #define	MDIO_OP_EXECUTE			0x00800000
144 #define	MDIO_CLK_25_4			0x00000000
145 #define	MDIO_CLK_25_6			0x02000000
146 #define	MDIO_CLK_25_8			0x03000000
147 #define	MDIO_CLK_25_10			0x04000000
148 #define	MDIO_CLK_25_14			0x05000000
149 #define	MDIO_CLK_25_20			0x06000000
150 #define	MDIO_CLK_25_28			0x07000000
151 #define	MDIO_OP_BUSY			0x08000000
152 #define	MDIO_DATA_SHIFT			0
153 #define	MDIO_REG_ADDR_SHIFT		16
154 
155 #define	MDIO_REG_ADDR(x)	\
156 	(((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
157 /* Default PHY address. */
158 #define	AGE_PHY_ADDR			0
159 
160 #define	AGE_PHY_STATUS			0x1418
161 
162 #define	AGE_BIST0			0x141C
163 #define	BIST0_ENB			0x00000001
164 #define	BIST0_SRAM_FAIL			0x00000002
165 #define	BIST0_FUSE_FLAG			0x00000004
166 
167 #define	AGE_BIST1			0x1420
168 #define	BIST1_ENB			0x00000001
169 #define	BIST1_SRAM_FAIL			0x00000002
170 #define	BIST1_FUSE_FLAG			0x00000004
171 
172 #define	AGE_MAC_CFG			0x1480
173 #define	MAC_CFG_TX_ENB			0x00000001
174 #define	MAC_CFG_RX_ENB			0x00000002
175 #define	MAC_CFG_TX_FC			0x00000004
176 #define	MAC_CFG_RX_FC			0x00000008
177 #define	MAC_CFG_LOOP			0x00000010
178 #define	MAC_CFG_FULL_DUPLEX		0x00000020
179 #define	MAC_CFG_TX_CRC_ENB		0x00000040
180 #define	MAC_CFG_TX_AUTO_PAD		0x00000080
181 #define	MAC_CFG_TX_LENCHK		0x00000100
182 #define	MAC_CFG_RX_JUMBO_ENB		0x00000200
183 #define	MAC_CFG_PREAMBLE_MASK		0x00003C00
184 #define	MAC_CFG_VLAN_TAG_STRIP		0x00004000
185 #define	MAC_CFG_PROMISC			0x00008000
186 #define	MAC_CFG_TX_PAUSE		0x00010000
187 #define	MAC_CFG_SCNT			0x00020000
188 #define	MAC_CFG_SYNC_RST_TX		0x00040000
189 #define	MAC_CFG_SPEED_MASK		0x00300000
190 #define	MAC_CFG_SPEED_10_100		0x00100000
191 #define	MAC_CFG_SPEED_1000		0x00200000
192 #define	MAC_CFG_DBG_TX_BACKOFF		0x00400000
193 #define	MAC_CFG_TX_JUMBO_ENB		0x00800000
194 #define	MAC_CFG_RXCSUM_ENB		0x01000000
195 #define	MAC_CFG_ALLMULTI		0x02000000
196 #define	MAC_CFG_BCAST			0x04000000
197 #define	MAC_CFG_DBG			0x08000000
198 #define	MAC_CFG_PREAMBLE_SHIFT		10
199 #define	MAC_CFG_PREAMBLE_DEFAULT	7
200 
201 #define	AGE_IPG_IFG_CFG			0x1484
202 #define	IPG_IFG_IPGT_MASK		0x0000007F
203 #define	IPG_IFG_MIFG_MASK		0x0000FF00
204 #define	IPG_IFG_IPG1_MASK		0x007F0000
205 #define	IPG_IFG_IPG2_MASK		0x7F000000
206 #define	IPG_IFG_IPGT_SHIFT		0
207 #define	IPG_IFG_IPGT_DEFAULT		0x60
208 #define	IPG_IFG_MIFG_SHIFT		8
209 #define	IPG_IFG_MIFG_DEFAULT		0x50
210 #define	IPG_IFG_IPG1_SHIFT		16
211 #define	IPG_IFG_IPG1_DEFAULT		0x40
212 #define	IPG_IFG_IPG2_SHIFT		24
213 #define	IPG_IFG_IPG2_DEFAULT		0x60
214 
215 /* station address */
216 #define	AGE_PAR0			0x1488
217 #define	AGE_PAR1			0x148C
218 
219 /* 64bit multicast hash register. */
220 #define	AGE_MAR0			0x1490
221 #define	AGE_MAR1			0x1494
222 
223 /* half-duplex parameter configuration. */
224 #define	AGE_HDPX_CFG			0x1498
225 #define	HDPX_CFG_LCOL_MASK		0x000003FF
226 #define	HDPX_CFG_RETRY_MASK		0x0000F000
227 #define	HDPX_CFG_EXC_DEF_EN		0x00010000
228 #define	HDPX_CFG_NO_BACK_C		0x00020000
229 #define	HDPX_CFG_NO_BACK_P		0x00040000
230 #define	HDPX_CFG_ABEBE			0x00080000
231 #define	HDPX_CFG_ABEBT_MASK		0x00F00000
232 #define	HDPX_CFG_JAMIPG_MASK		0x0F000000
233 #define	HDPX_CFG_LCOL_SHIFT		0
234 #define	HDPX_CFG_LCOL_DEFAULT		0x37
235 #define	HDPX_CFG_RETRY_SHIFT		12
236 #define	HDPX_CFG_RETRY_DEFAULT		0x0F
237 #define	HDPX_CFG_ABEBT_SHIFT		20
238 #define	HDPX_CFG_ABEBT_DEFAULT		0x0A
239 #define	HDPX_CFG_JAMIPG_SHIFT		24
240 #define	HDPX_CFG_JAMIPG_DEFAULT		0x07
241 
242 #define	AGE_FRAME_SIZE			0x149C
243 
244 #define	AGE_WOL_CFG			0x14A0
245 #define	WOL_CFG_PATTERN			0x00000001
246 #define	WOL_CFG_PATTERN_ENB		0x00000002
247 #define	WOL_CFG_MAGIC			0x00000004
248 #define	WOL_CFG_MAGIC_ENB		0x00000008
249 #define	WOL_CFG_LINK_CHG		0x00000010
250 #define	WOL_CFG_LINK_CHG_ENB		0x00000020
251 #define	WOL_CFG_PATTERN_DET		0x00000100
252 #define	WOL_CFG_MAGIC_DET		0x00000200
253 #define	WOL_CFG_LINK_CHG_DET		0x00000400
254 #define	WOL_CFG_CLK_SWITCH_ENB		0x00008000
255 #define	WOL_CFG_PATTERN0		0x00010000
256 #define	WOL_CFG_PATTERN1		0x00020000
257 #define	WOL_CFG_PATTERN2		0x00040000
258 #define	WOL_CFG_PATTERN3		0x00080000
259 #define	WOL_CFG_PATTERN4		0x00100000
260 #define	WOL_CFG_PATTERN5		0x00200000
261 #define	WOL_CFG_PATTERN6		0x00400000
262 
263 /* WOL pattern length. */
264 #define	AGE_PATTERN_CFG0		0x14A4
265 #define	PATTERN_CFG_0_LEN_MASK		0x0000007F
266 #define	PATTERN_CFG_1_LEN_MASK		0x00007F00
267 #define	PATTERN_CFG_2_LEN_MASK		0x007F0000
268 #define	PATTERN_CFG_3_LEN_MASK		0x7F000000
269 
270 #define	AGE_PATTERN_CFG1		0x14A8
271 #define	PATTERN_CFG_4_LEN_MASK		0x0000007F
272 #define	PATTERN_CFG_5_LEN_MASK		0x00007F00
273 #define	PATTERN_CFG_6_LEN_MASK		0x007F0000
274 
275 #define	AGE_SRAM_RD_ADDR		0x1500
276 
277 #define	AGE_SRAM_RD_LEN			0x1504
278 
279 #define	AGE_SRAM_RRD_ADDR		0x1508
280 
281 #define	AGE_SRAM_RRD_LEN		0x150C
282 
283 #define	AGE_SRAM_TPD_ADDR		0x1510
284 
285 #define	AGE_SRAM_TPD_LEN		0x1514
286 
287 #define	AGE_SRAM_TRD_ADDR		0x1518
288 
289 #define	AGE_SRAM_TRD_LEN		0x151C
290 
291 #define	AGE_SRAM_RX_FIFO_ADDR		0x1520
292 
293 #define	AGE_SRAM_RX_FIFO_LEN		0x1524
294 
295 #define	AGE_SRAM_TX_FIFO_ADDR		0x1528
296 
297 #define	AGE_SRAM_TX_FIFO_LEN		0x152C
298 
299 #define	AGE_SRAM_TCPH_ADDR		0x1530
300 #define	SRAM_TCPH_ADDR_MASK		0x00000FFF
301 #define	SRAM_PATH_ADDR_MASK		0x0FFF0000
302 #define	SRAM_TCPH_ADDR_SHIFT		0
303 #define	SRAM_PATH_ADDR_SHIFT		16
304 
305 #define	AGE_DMA_BLOCK			0x1534
306 #define	DMA_BLOCK_LOAD			0x00000001
307 
308 /*
309  * All descriptors and CMB/SMB share the same high address.
310  */
311 #define	AGE_DESC_ADDR_HI		0x1540
312 
313 #define	AGE_DESC_RD_ADDR_LO		0x1544
314 
315 #define	AGE_DESC_RRD_ADDR_LO		0x1548
316 
317 #define	AGE_DESC_TPD_ADDR_LO		0x154C
318 
319 #define	AGE_DESC_CMB_ADDR_LO		0x1550
320 
321 #define	AGE_DESC_SMB_ADDR_LO		0x1554
322 
323 #define	AGE_DESC_RRD_RD_CNT		0x1558
324 #define	DESC_RD_CNT_MASK		0x000007FF
325 #define	DESC_RRD_CNT_MASK		0x07FF0000
326 #define	DESC_RD_CNT_SHIFT		0
327 #define	DESC_RRD_CNT_SHIFT		16
328 
329 #define	AGE_DESC_TPD_CNT		0x155C
330 #define	DESC_TPD_CNT_MASK		0x00003FF
331 #define	DESC_TPD_CNT_SHIFT		0
332 
333 #define	AGE_TXQ_CFG			0x1580
334 #define	TXQ_CFG_TPD_BURST_MASK		0x0000001F
335 #define	TXQ_CFG_ENB			0x00000020
336 #define	TXQ_CFG_ENHANCED_MODE		0x00000040
337 #define	TXQ_CFG_TPD_FETCH_THRESH_MASK	0x00003F00
338 #define	TXQ_CFG_TX_FIFO_BURST_MASK	0xFFFF0000
339 #define	TXQ_CFG_TPD_BURST_SHIFT		0
340 #define	TXQ_CFG_TPD_BURST_DEFAULT	4
341 #define	TXQ_CFG_TPD_FETCH_THRESH_SHIFT	8
342 #define	TXQ_CFG_TPD_FETCH_DEFAULT	16
343 #define	TXQ_CFG_TX_FIFO_BURST_SHIFT	16
344 #define	TXQ_CFG_TX_FIFO_BURST_DEFAULT	256
345 
346 #define	AGE_TX_JUMBO_TPD_TH_IPG		0x1584
347 #define	TX_JUMBO_TPD_TH_MASK		0x000007FF
348 #define	TX_JUMBO_TPD_IPG_MASK		0x001F0000
349 #define	TX_JUMBO_TPD_TH_SHIFT		0
350 #define	TX_JUMBO_TPD_IPG_SHIFT		16
351 #define	TX_JUMBO_TPD_IPG_DEFAULT	1
352 
353 #define	AGE_RXQ_CFG			0x15A0
354 #define	RXQ_CFG_RD_BURST_MASK		0x000000FF
355 #define	RXQ_CFG_RRD_BURST_THRESH_MASK	0x0000FF00
356 #define	RXQ_CFG_RD_PREF_MIN_IPG_MASK	0x001F0000
357 #define	RXQ_CFG_CUT_THROUGH_ENB		0x40000000
358 #define	RXQ_CFG_ENB			0x80000000
359 #define	RXQ_CFG_RD_BURST_SHIFT		0
360 #define	RXQ_CFG_RD_BURST_DEFAULT	8
361 #define	RXQ_CFG_RRD_BURST_THRESH_SHIFT	8
362 #define	RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
363 #define	RXQ_CFG_RD_PREF_MIN_IPG_SHIFT	16
364 #define	RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT	1
365 
366 #define	AGE_RXQ_JUMBO_CFG		0x15A4
367 #define	RXQ_JUMBO_CFG_SZ_THRESH_MASK	0x000007FF
368 #define	RXQ_JUMBO_CFG_LKAH_MASK		0x00007800
369 #define	RXQ_JUMBO_CFG_RRD_TIMER_MASK	0xFFFF0000
370 #define	RXQ_JUMBO_CFG_SZ_THRESH_SHIFT	0
371 #define	RXQ_JUMBO_CFG_LKAH_SHIFT	11
372 #define	RXQ_JUMBO_CFG_LKAH_DEFAULT	0x01
373 #define	RXQ_JUMBO_CFG_RRD_TIMER_SHIFT	16
374 
375 #define	AGE_RXQ_FIFO_PAUSE_THRESH	0x15A8
376 #define	RXQ_FIFO_PAUSE_THRESH_LO_MASK	0x00000FFF
377 #define	RXQ_FIFO_PAUSE_THRESH_HI_MASK	0x0FFF000
378 #define	RXQ_FIFO_PAUSE_THRESH_LO_SHIFT	0
379 #define	RXQ_FIFO_PAUSE_THRESH_HI_SHIFT	16
380 
381 #define	AGE_RXQ_RRD_PAUSE_THRESH	0x15AC
382 #define	RXQ_RRD_PAUSE_THRESH_HI_MASK	0x00000FFF
383 #define	RXQ_RRD_PAUSE_THRESH_LO_MASK	0x0FFF0000
384 #define	RXQ_RRD_PAUSE_THRESH_HI_SHIFT	0
385 #define	RXQ_RRD_PAUSE_THRESH_LO_SHIFT	16
386 
387 #define	AGE_DMA_CFG			0x15C0
388 #define	DMA_CFG_IN_ORDER		0x00000001
389 #define	DMA_CFG_ENH_ORDER		0x00000002
390 #define	DMA_CFG_OUT_ORDER		0x00000004
391 #define	DMA_CFG_RCB_64			0x00000000
392 #define	DMA_CFG_RCB_128			0x00000008
393 #define	DMA_CFG_RD_BURST_128		0x00000000
394 #define	DMA_CFG_RD_BURST_256		0x00000010
395 #define	DMA_CFG_RD_BURST_512		0x00000020
396 #define	DMA_CFG_RD_BURST_1024		0x00000030
397 #define	DMA_CFG_RD_BURST_2048		0x00000040
398 #define	DMA_CFG_RD_BURST_4096		0x00000050
399 #define	DMA_CFG_WR_BURST_128		0x00000000
400 #define	DMA_CFG_WR_BURST_256		0x00000080
401 #define	DMA_CFG_WR_BURST_512		0x00000100
402 #define	DMA_CFG_WR_BURST_1024		0x00000180
403 #define	DMA_CFG_WR_BURST_2048		0x00000200
404 #define	DMA_CFG_WR_BURST_4096		0x00000280
405 #define	DMA_CFG_RD_ENB			0x00000400
406 #define	DMA_CFG_WR_ENB			0x00000800
407 #define	DMA_CFG_RD_BURST_MASK		0x07
408 #define	DMA_CFG_RD_BURST_SHIFT		4
409 #define	DMA_CFG_WR_BURST_MASK		0x07
410 #define	DMA_CFG_WR_BURST_SHIFT		7
411 
412 #define	AGE_CSMB_CTRL			0x15D0
413 #define	CSMB_CTRL_CMB_KICK		0x00000001
414 #define	CSMB_CTRL_SMB_KICK		0x00000002
415 #define	CSMB_CTRL_CMB_ENB		0x00000004
416 #define	CSMB_CTRL_SMB_ENB		0x00000008
417 
418 /* CMB DMA Write Threshold Register */
419 #define	AGE_CMB_WR_THRESH		0x15D4
420 #define	CMB_WR_THRESH_RRD_MASK		0x000007FF
421 #define	CMB_WR_THRESH_TPD_MASK		0x07FF0000
422 #define	CMB_WR_THRESH_RRD_SHIFT		0
423 #define	CMB_WR_THRESH_RRD_DEFAULT	4
424 #define	CMB_WR_THRESH_TPD_SHIFT		16
425 #define	CMB_WR_THRESH_TPD_DEFAULT	4
426 
427 /* RX/TX count-down timer to trigger CMB-write. */
428 #define	AGE_CMB_WR_TIMER		0x15D8
429 #define	CMB_WR_TIMER_RX_MASK		0x0000FFFF
430 #define	CMB_WR_TIMER_TX_MASK		0xFFFF0000
431 #define	CMB_WR_TIMER_RX_SHIFT		0
432 #define	CMB_WR_TIMER_TX_SHIFT		16
433 
434 /* Number of packet received since last CMB write */
435 #define	AGE_CMB_RX_PKT_CNT		0x15DC
436 
437 /* Number of packet transmitted since last CMB write */
438 #define	AGE_CMB_TX_PKT_CNT		0x15E0
439 
440 /* SMB auto DMA timer register */
441 #define	AGE_SMB_TIMER			0x15E4
442 
443 #define	AGE_MBOX			0x15F0
444 #define	MBOX_RD_PROD_IDX_MASK		0x000007FF
445 #define	MBOX_RRD_CONS_IDX_MASK		0x003FF800
446 #define	MBOX_TD_PROD_IDX_MASK		0xFFC00000
447 #define	MBOX_RD_PROD_IDX_SHIFT		0
448 #define	MBOX_RRD_CONS_IDX_SHIFT		11
449 #define	MBOX_TD_PROD_IDX_SHIFT		22
450 
451 #define	AGE_INTR_STATUS			0x1600
452 #define	INTR_SMB			0x00000001
453 #define	INTR_MOD_TIMER			0x00000002
454 #define	INTR_MANUAL_TIMER		0x00000004
455 #define	INTR_RX_FIFO_OFLOW		0x00000008
456 #define	INTR_RD_UNDERRUN		0x00000010
457 #define	INTR_RRD_OFLOW			0x00000020
458 #define	INTR_TX_FIFO_UNDERRUN		0x00000040
459 #define	INTR_LINK_CHG			0x00000080
460 #define	INTR_HOST_RD_UNDERRUN		0x00000100
461 #define	INTR_HOST_RRD_OFLOW		0x00000200
462 #define	INTR_DMA_RD_TO_RST		0x00000400
463 #define	INTR_DMA_WR_TO_RST		0x00000800
464 #define	INTR_GPHY			0x00001000
465 #define	INTR_RX_PKT			0x00010000
466 #define	INTR_TX_PKT			0x00020000
467 #define	INTR_TX_DMA			0x00040000
468 #define	INTR_RX_DMA			0x00080000
469 #define	INTR_CMB_RX			0x00100000
470 #define	INTR_CMB_TX			0x00200000
471 #define	INTR_MAC_RX			0x00400000
472 #define	INTR_MAC_TX			0x00800000
473 #define	INTR_UNDERRUN			0x01000000
474 #define	INTR_FRAME_ERROR		0x02000000
475 #define	INTR_FRAME_OK			0x04000000
476 #define	INTR_CSUM_ERROR			0x08000000
477 #define	INTR_PHY_LINK_DOWN		0x10000000
478 #define	INTR_DIS_SMB			0x20000000
479 #define	INTR_DIS_DMA			0x40000000
480 #define	INTR_DIS_INT			0x80000000
481 
482 /* Interrupt Mask Register */
483 #define	AGE_INTR_MASK			0x1604
484 
485 #define	AGE_INTRS						\
486 	(INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |	\
487 	INTR_CMB_TX | INTR_CMB_RX)
488 
489 /* Statistics counters collected by the MAC. */
490 struct smb {
491 	/* Rx stats. */
492 	uint32_t rx_frames;
493 	uint32_t rx_bcast_frames;
494 	uint32_t rx_mcast_frames;
495 	uint32_t rx_pause_frames;
496 	uint32_t rx_control_frames;
497 	uint32_t rx_crcerrs;
498 	uint32_t rx_lenerrs;
499 	uint32_t rx_bytes;
500 	uint32_t rx_runts;
501 	uint32_t rx_fragments;
502 	uint32_t rx_pkts_64;
503 	uint32_t rx_pkts_65_127;
504 	uint32_t rx_pkts_128_255;
505 	uint32_t rx_pkts_256_511;
506 	uint32_t rx_pkts_512_1023;
507 	uint32_t rx_pkts_1024_1518;
508 	uint32_t rx_pkts_1519_max;
509 	uint32_t rx_pkts_truncated;
510 	uint32_t rx_fifo_oflows;
511 	uint32_t rx_desc_oflows;
512 	uint32_t rx_alignerrs;
513 	uint32_t rx_bcast_bytes;
514 	uint32_t rx_mcast_bytes;
515 	uint32_t rx_pkts_filtered;
516 	/* Tx stats. */
517 	uint32_t tx_frames;
518 	uint32_t tx_bcast_frames;
519 	uint32_t tx_mcast_frames;
520 	uint32_t tx_pause_frames;
521 	uint32_t tx_excess_defer;
522 	uint32_t tx_control_frames;
523 	uint32_t tx_deferred;
524 	uint32_t tx_bytes;
525 	uint32_t tx_pkts_64;
526 	uint32_t tx_pkts_65_127;
527 	uint32_t tx_pkts_128_255;
528 	uint32_t tx_pkts_256_511;
529 	uint32_t tx_pkts_512_1023;
530 	uint32_t tx_pkts_1024_1518;
531 	uint32_t tx_pkts_1519_max;
532 	uint32_t tx_single_colls;
533 	uint32_t tx_multi_colls;
534 	uint32_t tx_late_colls;
535 	uint32_t tx_excess_colls;
536 	uint32_t tx_underrun;
537 	uint32_t tx_desc_underrun;
538 	uint32_t tx_lenerrs;
539 	uint32_t tx_pkts_truncated;
540 	uint32_t tx_bcast_bytes;
541 	uint32_t tx_mcast_bytes;
542 	uint32_t updated;
543 } __packed;
544 
545 /* Coalescing message block */
546 struct cmb {
547 	uint32_t intr_status;
548 	uint32_t rprod_cons;
549 #define	RRD_PROD_MASK			0x0000FFFF
550 #define	RD_CONS_MASK			0xFFFF0000
551 #define	RRD_PROD_SHIFT			0
552 #define	RD_CONS_SHIFT			16
553 	uint32_t tpd_cons;
554 #define	CMB_UPDATED			0x00000001
555 #define	TPD_CONS_MASK			0xFFFF0000
556 #define	TPD_CONS_SHIFT			16
557 } __packed;
558 
559 /* Rx return descriptor */
560 struct rx_rdesc {
561 	uint32_t index;
562 #define	AGE_RRD_NSEGS_MASK		0x000000FF
563 #define	AGE_RRD_CONS_MASK		0xFFFF0000
564 #define	AGE_RRD_NSEGS_SHIFT		0
565 #define	AGE_RRD_CONS_SHIFT		16
566 	uint32_t len;
567 #define	AGE_RRD_CSUM_MASK		0x0000FFFF
568 #define	AGE_RRD_LEN_MASK		0xFFFF0000
569 #define	AGE_RRD_CSUM_SHIFT		0
570 #define	AGE_RRD_LEN_SHIFT		16
571 	uint32_t flags;
572 #define	AGE_RRD_ETHERNET		0x00000080
573 #define	AGE_RRD_VLAN			0x00000100
574 #define	AGE_RRD_ERROR			0x00000200
575 #define	AGE_RRD_IPV4			0x00000400
576 #define	AGE_RRD_UDP			0x00000800
577 #define	AGE_RRD_TCP			0x00001000
578 #define	AGE_RRD_BCAST			0x00002000
579 #define	AGE_RRD_MCAST			0x00004000
580 #define	AGE_RRD_PAUSE			0x00008000
581 #define	AGE_RRD_CRC			0x00010000
582 #define	AGE_RRD_CODE			0x00020000
583 #define	AGE_RRD_DRIBBLE			0x00040000
584 #define	AGE_RRD_RUNT			0x00080000
585 #define	AGE_RRD_OFLOW			0x00100000
586 #define	AGE_RRD_TRUNC			0x00200000
587 #define	AGE_RRD_IPCSUM_NOK		0x00400000
588 #define	AGE_RRD_TCP_UDPCSUM_NOK		0x00800000
589 #define	AGE_RRD_LENGTH_NOK		0x01000000
590 #define	AGE_RRD_DES_ADDR_FILTERED	0x02000000
591 	uint32_t vtags;
592 #define	AGE_RRD_VLAN_MASK		0xFFFF0000
593 #define	AGE_RRD_VLAN_SHIFT		16
594 } __packed;
595 
596 #define	AGE_RX_NSEGS(x)		\
597 	(((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT)
598 #define	AGE_RX_CONS(x)		\
599 	(((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT)
600 #define	AGE_RX_CSUM(x)		\
601 	(((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT)
602 #define	AGE_RX_BYTES(x)		\
603 	(((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT)
604 #define	AGE_RX_VLAN(x)		\
605 	(((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT)
606 #define	AGE_RX_VLAN_TAG(x)	\
607 	(((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9))
608 
609 /* Rx descriptor. */
610 struct rx_desc {
611 	uint64_t addr;
612 	uint32_t len;
613 #define	AGE_RD_LEN_MASK			0x0000FFFF
614 #define	AGE_CONS_UPD_REQ_MASK		0xFFFF0000
615 #define	AGE_RD_LEN_SHIFT		0
616 #define	AGE_CONS_UPD_REQ_SHIFT		16
617 } __packed;
618 
619 /* Tx descriptor. */
620 struct tx_desc {
621 	uint64_t addr;
622 	uint32_t len;
623 #define	AGE_TD_VLAN_MASK		0xFFFF0000
624 #define	AGE_TD_PKT_INT			0x00008000
625 #define	AGE_TD_DMA_INT			0x00004000
626 #define	AGE_TD_BUFLEN_MASK		0x00003FFF
627 #define	AGE_TD_VLAN_SHIFT		16
628 #define	AGE_TX_VLAN_TAG(x)	\
629 	(((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8))
630 #define	AGE_TD_BUFLEN_SHIFT		0
631 #define	AGE_TX_BYTES(x)		\
632 	(((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK)
633 	uint32_t flags;
634 #define	AGE_TD_TSO_MSS			0xFFF80000
635 #define	AGE_TD_TSO_HDR			0x00040000
636 #define	AGE_TD_TSO_TCPHDR_LEN		0x0003C000
637 #define	AGE_TD_IPHDR_LEN		0x00003C00
638 #define	AGE_TD_LLC_SNAP			0x00000200
639 #define	AGE_TD_VLAN_TAGGED		0x00000100
640 #define	AGE_TD_UDPCSUM			0x00000080
641 #define	AGE_TD_TCPCSUM			0x00000040
642 #define	AGE_TD_IPCSUM			0x00000020
643 #define	AGE_TD_TSO_IPV4			0x00000010
644 #define	AGE_TD_TSO_IPV6			0x00000012
645 #define	AGE_TD_CSUM			0x00000008
646 #define	AGE_TD_INSERT_VLAN_TAG		0x00000004
647 #define	AGE_TD_COALESCE			0x00000002
648 #define	AGE_TD_EOP			0x00000001
649 
650 #define	AGE_TD_CSUM_PLOADOFFSET		0x00FF0000
651 #define	AGE_TD_CSUM_XSUMOFFSET		0xFF000000
652 #define	AGE_TD_CSUM_XSUMOFFSET_SHIFT	24
653 #define	AGE_TD_CSUM_PLOADOFFSET_SHIFT	16
654 #define	AGE_TD_TSO_MSS_SHIFT		19
655 #define	AGE_TD_TSO_TCPHDR_LEN_SHIFT	14
656 #define	AGE_TD_IPHDR_LEN_SHIFT		10
657 } __packed;
658 
659 #endif	/* _IF_AGEREG_H */
660