1 /* $NetBSD: ahcisatavar.h,v 1.27 2021/11/19 23:46:55 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <dev/ic/ahcisatareg.h> 29 30 #define AHCI_DEBUG 31 32 #define DEBUG_INTR 0x01 33 #define DEBUG_XFERS 0x02 34 #define DEBUG_FUNCS 0x08 35 #define DEBUG_PROBE 0x10 36 #define DEBUG_DETACH 0x20 37 #ifdef AHCI_DEBUG 38 extern int ahcidebug_mask; 39 #define AHCIDEBUG_PRINT(args, level) \ 40 if (ahcidebug_mask & (level)) \ 41 printf args 42 #else 43 #define AHCIDEBUG_PRINT(args, level) 44 #endif 45 46 struct ahci_softc { 47 struct atac_softc sc_atac; 48 bus_space_tag_t sc_ahcit; /* ahci registers mapping */ 49 bus_space_handle_t sc_ahcih; 50 bus_size_t sc_ahcis; 51 bus_dma_tag_t sc_dmat; /* DMA memory mappings: */ 52 void *sc_cmd_hdr; /* command tables and received FIS */ 53 bus_dmamap_t sc_cmd_hdrd; 54 bus_dma_segment_t sc_cmd_hdr_seg; 55 int sc_cmd_hdr_nseg; 56 int sc_atac_capflags; 57 int sc_ahci_quirks; 58 #define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 59 #define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */ 60 #define AHCI_QUIRK_BADPMP __BIT(2) /* broken PMP support, ignore */ 61 #define AHCI_QUIRK_BADNCQ __BIT(3) /* possibly broken NCQ support, ignore */ 62 #define AHCI_QUIRK_EXTRA_DELAY __BIT(4) /* needs extra delay */ 63 64 uint32_t sc_ahci_cap; /* copy of AHCI_CAP */ 65 int sc_ncmds; /* number of command slots */ 66 uint32_t sc_ahci_ports; 67 struct ata_channel *sc_chanarray[AHCI_MAX_PORTS]; 68 struct ahci_channel { 69 struct ata_channel ata_channel; /* generic part */ 70 bus_space_handle_t ahcic_scontrol; 71 bus_space_handle_t ahcic_sstatus; 72 bus_space_handle_t ahcic_serror; 73 /* pointers allocated from sc_cmd_hdrd */ 74 struct ahci_r_fis *ahcic_rfis; /* received FIS */ 75 bus_addr_t ahcic_bus_rfis; 76 struct ahci_cmd_header *ahcic_cmdh; /* command headers */ 77 bus_addr_t ahcic_bus_cmdh; 78 /* command tables (allocated per-channel) */ 79 bus_dmamap_t ahcic_cmd_tbld; 80 bus_dma_segment_t ahcic_cmd_tbl_seg; 81 int ahcic_cmd_tbl_nseg; 82 struct ahci_cmd_tbl *ahcic_cmd_tbl[AHCI_MAX_CMDS]; 83 bus_addr_t ahcic_bus_cmd_tbl[AHCI_MAX_CMDS]; 84 bus_dmamap_t ahcic_datad[AHCI_MAX_CMDS]; 85 } sc_channels[AHCI_MAX_PORTS]; 86 87 void (*sc_channel_start)(struct ahci_softc *, struct ata_channel *); 88 void (*sc_channel_stop)(struct ahci_softc *, struct ata_channel *); 89 int (*sc_intr_establish)(struct ahci_softc *, int); 90 91 bool sc_ghc_mrsm; 92 bool sc_save_init_data; 93 struct { 94 uint32_t cap; 95 uint32_t cap2; 96 uint32_t ports; 97 } sc_init_data; 98 }; 99 100 #define AHCINAME(sc) (device_xname((sc)->sc_atac.atac_dev)) 101 102 #define AHCI_CMDH_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \ 103 (sc)->sc_cmd_hdrd, \ 104 (char *)(&(achp)->ahcic_cmdh[(cmd)]) - (char *)(sc)->sc_cmd_hdr, \ 105 sizeof(struct ahci_cmd_header), (op)) 106 #define AHCI_RFIS_SYNC(sc, achp, op) bus_dmamap_sync((sc)->sc_dmat, \ 107 (sc)->sc_cmd_hdrd, \ 108 (char *)(achp)->ahcic_rfis - (char *)(sc)->sc_cmd_hdr, \ 109 AHCI_RFIS_SIZE, (op)) 110 #define AHCI_CMDTBL_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \ 111 (achp)->ahcic_cmd_tbld, AHCI_CMDTBL_SIZE * (cmd), \ 112 AHCI_CMDTBL_SIZE, (op)) 113 114 #define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \ 115 (sc)->sc_ahcih, (reg)) 116 #define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \ 117 (sc)->sc_ahcih, (reg), (val)) 118 119 #define AHCI_CH2SC(chp) (struct ahci_softc *)((chp)->ch_atac) 120 121 void ahci_attach(struct ahci_softc *); 122 int ahci_detach(struct ahci_softc *, int); 123 void ahci_childdetached(struct ahci_softc *, device_t); 124 void ahci_resume(struct ahci_softc *); 125 126 int ahci_intr(void *); 127 int ahci_intr_port(void *); 128 129