1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 2, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to the 21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 /* Note that some other tm.h files include this one and then override 25 many of the definitions. */ 26 27 /* Definitions for the object file format. These are set at 28 compile-time. */ 29 30 #define OBJECT_XCOFF 1 31 #define OBJECT_ELF 2 32 #define OBJECT_PEF 3 33 #define OBJECT_MACHO 4 34 35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 39 40 #ifndef TARGET_AIX 41 #define TARGET_AIX 0 42 #endif 43 44 /* Control whether function entry points use a "dot" symbol when 45 ABI_AIX. */ 46 #define DOT_SYMBOLS 1 47 48 /* Default string to use for cpu if not specified. */ 49 #ifndef TARGET_CPU_DEFAULT 50 #define TARGET_CPU_DEFAULT ((char *)0) 51 #endif 52 53 /* If configured for PPC405, support PPC405CR Erratum77. */ 54 #ifdef CONFIG_PPC405CR 55 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 56 #else 57 #define PPC405_ERRATUM77 0 58 #endif 59 60 /* Common ASM definitions used by ASM_SPEC among the various targets 61 for handling -mcpu=xxx switches. */ 62 #define ASM_CPU_SPEC \ 63 "%{!mcpu*: \ 64 %{mpower: %{!mpower2: -mpwr}} \ 65 %{mpower2: -mpwrx} \ 66 %{mpowerpc64*: -mppc64} \ 67 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ 68 %{mno-power: %{!mpowerpc*: -mcom}} \ 69 %{!mno-power: %{!mpower*: %(asm_default)}}} \ 70 %{mcpu=common: -mcom} \ 71 %{mcpu=power: -mpwr} \ 72 %{mcpu=power2: -mpwrx} \ 73 %{mcpu=power3: -mppc64} \ 74 %{mcpu=power4: -mpower4} \ 75 %{mcpu=power5: -mpower4} \ 76 %{mcpu=power5+: -mpower4} \ 77 %{mcpu=power6: -mpower4 -maltivec} \ 78 %{mcpu=powerpc: -mppc} \ 79 %{mcpu=rios: -mpwr} \ 80 %{mcpu=rios1: -mpwr} \ 81 %{mcpu=rios2: -mpwrx} \ 82 %{mcpu=rsc: -mpwr} \ 83 %{mcpu=rsc1: -mpwr} \ 84 %{mcpu=rs64a: -mppc64} \ 85 %{mcpu=401: -mppc} \ 86 %{mcpu=403: -m403} \ 87 %{mcpu=405: -m405} \ 88 %{mcpu=405fp: -m405} \ 89 %{mcpu=440: -m440} \ 90 %{mcpu=440fp: -m440} \ 91 %{mcpu=505: -mppc} \ 92 %{mcpu=601: -m601} \ 93 %{mcpu=602: -mppc} \ 94 %{mcpu=603: -mppc} \ 95 %{mcpu=603e: -mppc} \ 96 %{mcpu=ec603e: -mppc} \ 97 %{mcpu=604: -mppc} \ 98 %{mcpu=604e: -mppc} \ 99 %{mcpu=620: -mppc64} \ 100 %{mcpu=630: -mppc64} \ 101 %{mcpu=740: -mppc} \ 102 %{mcpu=750: -mppc} \ 103 %{mcpu=G3: -mppc} \ 104 %{mcpu=7400: -mppc -maltivec} \ 105 %{mcpu=7450: -mppc -maltivec} \ 106 %{mcpu=G4: -mppc -maltivec} \ 107 %{mcpu=801: -mppc} \ 108 %{mcpu=821: -mppc} \ 109 %{mcpu=823: -mppc} \ 110 %{mcpu=860: -mppc} \ 111 %{mcpu=970: -mpower4 -maltivec} \ 112 %{mcpu=G5: -mpower4 -maltivec} \ 113 %{mcpu=8540: -me500} \ 114 %{maltivec: -maltivec} \ 115 -many" 116 117 #define CPP_DEFAULT_SPEC "" 118 119 #define ASM_DEFAULT_SPEC "" 120 121 /* This macro defines names of additional specifications to put in the specs 122 that can be used in various specifications like CC1_SPEC. Its definition 123 is an initializer with a subgrouping for each command option. 124 125 Each subgrouping contains a string constant, that defines the 126 specification name, and a string constant that used by the GCC driver 127 program. 128 129 Do not define this macro if it does not need to do anything. */ 130 131 #define SUBTARGET_EXTRA_SPECS 132 133 #define EXTRA_SPECS \ 134 { "cpp_default", CPP_DEFAULT_SPEC }, \ 135 { "asm_cpu", ASM_CPU_SPEC }, \ 136 { "asm_default", ASM_DEFAULT_SPEC }, \ 137 SUBTARGET_EXTRA_SPECS 138 139 /* Architecture type. */ 140 141 /* Define TARGET_MFCRF if the target assembler does not support the 142 optional field operand for mfcr. */ 143 144 #ifndef HAVE_AS_MFCRF 145 #undef TARGET_MFCRF 146 #define TARGET_MFCRF 0 147 #endif 148 149 /* Define TARGET_POPCNTB if the target assembler does not support the 150 popcount byte instruction. */ 151 152 #ifndef HAVE_AS_POPCNTB 153 #undef TARGET_POPCNTB 154 #define TARGET_POPCNTB 0 155 #endif 156 157 /* Define TARGET_FPRND if the target assembler does not support the 158 fp rounding instructions. */ 159 160 #ifndef HAVE_AS_FPRND 161 #undef TARGET_FPRND 162 #define TARGET_FPRND 0 163 #endif 164 165 #ifndef TARGET_SECURE_PLT 166 #define TARGET_SECURE_PLT 0 167 #endif 168 169 #define TARGET_32BIT (! TARGET_64BIT) 170 171 #ifndef HAVE_AS_TLS 172 #define HAVE_AS_TLS 0 173 #endif 174 175 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 176 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 177 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 178 179 #ifdef IN_LIBGCC2 180 /* For libgcc2 we make sure this is a compile time constant */ 181 #if defined (__64BIT__) || defined (__powerpc64__) 182 #undef TARGET_POWERPC64 183 #define TARGET_POWERPC64 1 184 #else 185 #undef TARGET_POWERPC64 186 #define TARGET_POWERPC64 0 187 #endif 188 #else 189 /* The option machinery will define this. */ 190 #endif 191 192 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) 193 194 /* Processor type. Order must match cpu attribute in MD file. */ 195 enum processor_type 196 { 197 PROCESSOR_RIOS1, 198 PROCESSOR_RIOS2, 199 PROCESSOR_RS64A, 200 PROCESSOR_MPCCORE, 201 PROCESSOR_PPC403, 202 PROCESSOR_PPC405, 203 PROCESSOR_PPC440, 204 PROCESSOR_PPC601, 205 PROCESSOR_PPC603, 206 PROCESSOR_PPC604, 207 PROCESSOR_PPC604e, 208 PROCESSOR_PPC620, 209 PROCESSOR_PPC630, 210 PROCESSOR_PPC750, 211 PROCESSOR_PPC7400, 212 PROCESSOR_PPC7450, 213 PROCESSOR_PPC8540, 214 PROCESSOR_POWER4, 215 PROCESSOR_POWER5 216 }; 217 218 extern enum processor_type rs6000_cpu; 219 220 /* Recast the processor type to the cpu attribute. */ 221 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 222 223 /* Define generic processor types based upon current deployment. */ 224 #define PROCESSOR_COMMON PROCESSOR_PPC601 225 #define PROCESSOR_POWER PROCESSOR_RIOS1 226 #define PROCESSOR_POWERPC PROCESSOR_PPC604 227 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 228 229 /* Define the default processor. This is overridden by other tm.h files. */ 230 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 231 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 232 233 /* Specify the dialect of assembler to use. New mnemonics is dialect one 234 and the old mnemonics are dialect zero. */ 235 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) 236 237 /* Types of costly dependences. */ 238 enum rs6000_dependence_cost 239 { 240 max_dep_latency = 1000, 241 no_dep_costly, 242 all_deps_costly, 243 true_store_to_load_dep_costly, 244 store_to_load_dep_costly 245 }; 246 247 /* Types of nop insertion schemes in sched target hook sched_finish. */ 248 enum rs6000_nop_insertion 249 { 250 sched_finish_regroup_exact = 1000, 251 sched_finish_pad_groups, 252 sched_finish_none 253 }; 254 255 /* Dispatch group termination caused by an insn. */ 256 enum group_termination 257 { 258 current_group, 259 previous_group 260 }; 261 262 /* Support for a compile-time default CPU, et cetera. The rules are: 263 --with-cpu is ignored if -mcpu is specified. 264 --with-tune is ignored if -mtune is specified. 265 --with-float is ignored if -mhard-float or -msoft-float are 266 specified. */ 267 #define OPTION_DEFAULT_SPECS \ 268 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 269 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 270 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } 271 272 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ 273 struct rs6000_cpu_select 274 { 275 const char *string; 276 const char *name; 277 int set_tune_p; 278 int set_arch_p; 279 }; 280 281 extern struct rs6000_cpu_select rs6000_select[]; 282 283 /* Debug support */ 284 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ 285 extern int rs6000_debug_stack; /* debug stack applications */ 286 extern int rs6000_debug_arg; /* debug argument handling */ 287 288 #define TARGET_DEBUG_STACK rs6000_debug_stack 289 #define TARGET_DEBUG_ARG rs6000_debug_arg 290 291 extern const char *rs6000_traceback_name; /* Type of traceback table. */ 292 293 /* These are separate from target_flags because we've run out of bits 294 there. */ 295 extern int rs6000_long_double_type_size; 296 extern int rs6000_ieeequad; 297 extern int rs6000_altivec_abi; 298 extern int rs6000_spe_abi; 299 extern int rs6000_float_gprs; 300 extern int rs6000_alignment_flags; 301 extern const char *rs6000_sched_insert_nops_str; 302 extern enum rs6000_nop_insertion rs6000_sched_insert_nops; 303 304 /* Alignment options for fields in structures for sub-targets following 305 AIX-like ABI. 306 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 307 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 308 309 Override the macro definitions when compiling libobjc to avoid undefined 310 reference to rs6000_alignment_flags due to library's use of GCC alignment 311 macros which use the macros below. */ 312 313 #ifndef IN_TARGET_LIBS 314 #define MASK_ALIGN_POWER 0x00000000 315 #define MASK_ALIGN_NATURAL 0x00000001 316 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 317 #else 318 #define TARGET_ALIGN_NATURAL 0 319 #endif 320 321 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 322 #define TARGET_IEEEQUAD rs6000_ieeequad 323 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 324 325 #define TARGET_SPE_ABI 0 326 #define TARGET_SPE 0 327 #define TARGET_E500 0 328 #define TARGET_ISEL 0 329 #define TARGET_FPRS 1 330 #define TARGET_E500_SINGLE 0 331 #define TARGET_E500_DOUBLE 0 332 333 /* Sometimes certain combinations of command options do not make sense 334 on a particular target machine. You can define a macro 335 `OVERRIDE_OPTIONS' to take account of this. This macro, if 336 defined, is executed once just after all the command options have 337 been parsed. 338 339 Do not use this macro to turn on various extra optimizations for 340 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. 341 342 On the RS/6000 this is used to define the target cpu type. */ 343 344 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) 345 346 /* Define this to change the optimizations performed by default. */ 347 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) 348 349 /* Show we can debug even without a frame pointer. */ 350 #define CAN_DEBUG_WITHOUT_FP 351 352 /* Target pragma. */ 353 #define REGISTER_TARGET_PRAGMAS() do { \ 354 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 355 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 356 } while (0) 357 358 /* Target #defines. */ 359 #define TARGET_CPU_CPP_BUILTINS() \ 360 rs6000_cpu_cpp_builtins (pfile) 361 362 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 363 we're compiling for. Some configurations may need to override it. */ 364 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 365 do \ 366 { \ 367 if (BYTES_BIG_ENDIAN) \ 368 { \ 369 builtin_define ("__BIG_ENDIAN__"); \ 370 builtin_define ("_BIG_ENDIAN"); \ 371 builtin_assert ("machine=bigendian"); \ 372 } \ 373 else \ 374 { \ 375 builtin_define ("__LITTLE_ENDIAN__"); \ 376 builtin_define ("_LITTLE_ENDIAN"); \ 377 builtin_assert ("machine=littleendian"); \ 378 } \ 379 } \ 380 while (0) 381 382 /* Target machine storage layout. */ 383 384 /* Define this macro if it is advisable to hold scalars in registers 385 in a wider mode than that declared by the program. In such cases, 386 the value is constrained to be within the bounds of the declared 387 type, but kept valid in the wider mode. The signedness of the 388 extension may differ from that of the type. */ 389 390 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 391 if (GET_MODE_CLASS (MODE) == MODE_INT \ 392 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 393 (MODE) = TARGET_32BIT ? SImode : DImode; 394 395 /* Define this if most significant bit is lowest numbered 396 in instructions that operate on numbered bit-fields. */ 397 /* That is true on RS/6000. */ 398 #define BITS_BIG_ENDIAN 1 399 400 /* Define this if most significant byte of a word is the lowest numbered. */ 401 /* That is true on RS/6000. */ 402 #define BYTES_BIG_ENDIAN 1 403 404 /* Define this if most significant word of a multiword number is lowest 405 numbered. 406 407 For RS/6000 we can decide arbitrarily since there are no machine 408 instructions for them. Might as well be consistent with bits and bytes. */ 409 #define WORDS_BIG_ENDIAN 1 410 411 #define MAX_BITS_PER_WORD 64 412 413 /* Width of a word, in units (bytes). */ 414 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 415 #ifdef IN_LIBGCC2 416 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 417 #else 418 #define MIN_UNITS_PER_WORD 4 419 #endif 420 #define UNITS_PER_FP_WORD 8 421 #define UNITS_PER_ALTIVEC_WORD 16 422 #define UNITS_PER_SPE_WORD 8 423 424 /* Type used for ptrdiff_t, as a string used in a declaration. */ 425 #define PTRDIFF_TYPE "int" 426 427 /* Type used for size_t, as a string used in a declaration. */ 428 #define SIZE_TYPE "long unsigned int" 429 430 /* Type used for wchar_t, as a string used in a declaration. */ 431 #define WCHAR_TYPE "short unsigned int" 432 433 /* Width of wchar_t in bits. */ 434 #define WCHAR_TYPE_SIZE 16 435 436 /* A C expression for the size in bits of the type `short' on the 437 target machine. If you don't define this, the default is half a 438 word. (If this would be less than one storage unit, it is 439 rounded up to one unit.) */ 440 #define SHORT_TYPE_SIZE 16 441 442 /* A C expression for the size in bits of the type `int' on the 443 target machine. If you don't define this, the default is one 444 word. */ 445 #define INT_TYPE_SIZE 32 446 447 /* A C expression for the size in bits of the type `long' on the 448 target machine. If you don't define this, the default is one 449 word. */ 450 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 451 452 /* A C expression for the size in bits of the type `long long' on the 453 target machine. If you don't define this, the default is two 454 words. */ 455 #define LONG_LONG_TYPE_SIZE 64 456 457 /* A C expression for the size in bits of the type `float' on the 458 target machine. If you don't define this, the default is one 459 word. */ 460 #define FLOAT_TYPE_SIZE 32 461 462 /* A C expression for the size in bits of the type `double' on the 463 target machine. If you don't define this, the default is two 464 words. */ 465 #define DOUBLE_TYPE_SIZE 64 466 467 /* A C expression for the size in bits of the type `long double' on 468 the target machine. If you don't define this, the default is two 469 words. */ 470 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 471 472 /* Define this to set long double type size to use in libgcc2.c, which can 473 not depend on target_flags. */ 474 #ifdef __LONG_DOUBLE_128__ 475 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 476 #else 477 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 478 #endif 479 480 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 481 #define WIDEST_HARDWARE_FP_SIZE 64 482 483 /* Width in bits of a pointer. 484 See also the macro `Pmode' defined below. */ 485 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) 486 487 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 488 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 489 490 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 491 #define STACK_BOUNDARY \ 492 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128) 493 494 /* Allocation boundary (in *bits*) for the code of a function. */ 495 #define FUNCTION_BOUNDARY 32 496 497 /* No data type wants to be aligned rounder than this. */ 498 #define BIGGEST_ALIGNMENT 128 499 500 /* A C expression to compute the alignment for a variables in the 501 local store. TYPE is the data type, and ALIGN is the alignment 502 that the object would ordinarily have. */ 503 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 504 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ 505 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \ 506 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) 507 508 /* Alignment of field after `int : 0' in a structure. */ 509 #define EMPTY_FIELD_BOUNDARY 32 510 511 /* Every structure's size must be a multiple of this. */ 512 #define STRUCTURE_SIZE_BOUNDARY 8 513 514 /* Return 1 if a structure or array containing FIELD should be 515 accessed using `BLKMODE'. 516 517 For the SPE, simd types are V2SI, and gcc can be tempted to put the 518 entire thing in a DI and use subregs to access the internals. 519 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the 520 back-end. Because a single GPR can hold a V2SI, but not a DI, the 521 best thing to do is set structs to BLKmode and avoid Severe Tire 522 Damage. 523 524 On e500 v2, DF and DI modes suffer from the same anomaly. DF can 525 fit into 1, whereas DI still needs two. */ 526 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 527 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ 528 || (TARGET_E500_DOUBLE && (MODE) == DFmode)) 529 530 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 531 #define PCC_BITFIELD_TYPE_MATTERS 1 532 533 /* Make strings word-aligned so strcpy from constants will be faster. 534 Make vector constants quadword aligned. */ 535 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 536 (TREE_CODE (EXP) == STRING_CST \ 537 && (ALIGN) < BITS_PER_WORD \ 538 ? BITS_PER_WORD \ 539 : (ALIGN)) 540 541 /* Make arrays of chars word-aligned for the same reasons. 542 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 543 64 bits. */ 544 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 545 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ 546 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \ 547 : TREE_CODE (TYPE) == ARRAY_TYPE \ 548 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 549 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 550 551 /* Nonzero if move instructions will actually fail to work 552 when given unaligned data. */ 553 #define STRICT_ALIGNMENT 0 554 555 /* Define this macro to be the value 1 if unaligned accesses have a cost 556 many times greater than aligned accesses, for example if they are 557 emulated in a trap handler. */ 558 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 559 (STRICT_ALIGNMENT \ 560 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 561 || (MODE) == DImode) \ 562 && (ALIGN) < 32)) 563 564 /* Standard register usage. */ 565 566 /* Number of actual hardware registers. 567 The hardware registers are assigned numbers for the compiler 568 from 0 to just below FIRST_PSEUDO_REGISTER. 569 All registers that the compiler knows about must be given numbers, 570 even those that are not normally considered general registers. 571 572 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 573 an MQ register, a count register, a link register, and 8 condition 574 register fields, which we view here as separate registers. AltiVec 575 adds 32 vector registers and a VRsave register. 576 577 In addition, the difference between the frame and argument pointers is 578 a function of the number of registers saved, so we need to have a 579 register for AP that will later be eliminated in favor of SP or FP. 580 This is a normal register, but it is fixed. 581 582 We also create a pseudo register for float/int conversions, that will 583 really represent the memory location used. It is represented here as 584 a register, in order to work around problems in allocating stack storage 585 in inline functions. 586 587 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 588 pointer, which is eventually eliminated in favor of SP or FP. */ 589 590 #define FIRST_PSEUDO_REGISTER 114 591 592 /* This must be included for pre gcc 3.0 glibc compatibility. */ 593 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 594 595 /* Add 32 dwarf columns for synthetic SPE registers. */ 596 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) 597 598 /* The SPE has an additional 32 synthetic registers, with DWARF debug 599 info numbering for these registers starting at 1200. While eh_frame 600 register numbering need not be the same as the debug info numbering, 601 we choose to number these regs for eh_frame at 1200 too. This allows 602 future versions of the rs6000 backend to add hard registers and 603 continue to use the gcc hard register numbering for eh_frame. If the 604 extra SPE registers in eh_frame were numbered starting from the 605 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER 606 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to 607 avoid invalidating older SPE eh_frame info. 608 609 We must map them here to avoid huge unwinder tables mostly consisting 610 of unused space. */ 611 #define DWARF_REG_TO_UNWIND_COLUMN(r) \ 612 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) 613 614 /* Use gcc hard register numbering for eh_frame. */ 615 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 616 617 /* 1 for registers that have pervasive standard uses 618 and are not available for the register allocator. 619 620 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 621 as a local register; for all other OS's r2 is the TOC pointer. 622 623 cr5 is not supposed to be used. 624 625 On System V implementations, r13 is fixed and not available for use. */ 626 627 #define FIXED_REGISTERS \ 628 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 632 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 633 /* AltiVec registers. */ \ 634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 636 1, 1 \ 637 , 1, 1, 1 \ 638 } 639 640 /* 1 for registers not available across function calls. 641 These must include the FIXED_REGISTERS and also any 642 registers that can be used without being saved. 643 The latter must include the registers where values are returned 644 and the register where structure-value addresses are passed. 645 Aside from that, you can include as many other registers as you like. */ 646 647 #define CALL_USED_REGISTERS \ 648 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 650 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 651 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 652 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 653 /* AltiVec registers. */ \ 654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 655 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 656 1, 1 \ 657 , 1, 1, 1 \ 658 } 659 660 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 661 the entire set of `FIXED_REGISTERS' be included. 662 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 663 This macro is optional. If not specified, it defaults to the value 664 of `CALL_USED_REGISTERS'. */ 665 666 #define CALL_REALLY_USED_REGISTERS \ 667 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 669 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 670 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 671 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 672 /* AltiVec registers. */ \ 673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 674 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 675 0, 0 \ 676 , 0, 0, 0 \ 677 } 678 679 #define MQ_REGNO 64 680 #define CR0_REGNO 68 681 #define CR1_REGNO 69 682 #define CR2_REGNO 70 683 #define CR3_REGNO 71 684 #define CR4_REGNO 72 685 #define MAX_CR_REGNO 75 686 #define XER_REGNO 76 687 #define FIRST_ALTIVEC_REGNO 77 688 #define LAST_ALTIVEC_REGNO 108 689 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 690 #define VRSAVE_REGNO 109 691 #define VSCR_REGNO 110 692 #define SPE_ACC_REGNO 111 693 #define SPEFSCR_REGNO 112 694 695 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 696 #define FIRST_SAVED_FP_REGNO (14+32) 697 #define FIRST_SAVED_GP_REGNO 13 698 699 /* List the order in which to allocate registers. Each register must be 700 listed once, even those in FIXED_REGISTERS. 701 702 We allocate in the following order: 703 fp0 (not saved or used for anything) 704 fp13 - fp2 (not saved; incoming fp arg registers) 705 fp1 (not saved; return value) 706 fp31 - fp14 (saved; order given to save least number) 707 cr7, cr6 (not saved or special) 708 cr1 (not saved, but used for FP operations) 709 cr0 (not saved, but used for arithmetic operations) 710 cr4, cr3, cr2 (saved) 711 r0 (not saved; cannot be base reg) 712 r9 (not saved; best for TImode) 713 r11, r10, r8-r4 (not saved; highest used first to make less conflict) 714 r3 (not saved; return value register) 715 r31 - r13 (saved; order given to save least number) 716 r12 (not saved; if used for DImode or DFmode would use r13) 717 mq (not saved; best to use it if we can) 718 ctr (not saved; when we have the choice ctr is better) 719 lr (saved) 720 cr5, r1, r2, ap, xer (fixed) 721 v0 - v1 (not saved or used for anything) 722 v13 - v3 (not saved; incoming vector arg registers) 723 v2 (not saved; incoming vector arg reg; return value) 724 v19 - v14 (not saved or used for anything) 725 v31 - v20 (saved; order given to save least number) 726 vrsave, vscr (fixed) 727 spe_acc, spefscr (fixed) 728 sfp (fixed) 729 */ 730 731 #if FIXED_R2 == 1 732 #define MAYBE_R2_AVAILABLE 733 #define MAYBE_R2_FIXED 2, 734 #else 735 #define MAYBE_R2_AVAILABLE 2, 736 #define MAYBE_R2_FIXED 737 #endif 738 739 #define REG_ALLOC_ORDER \ 740 {32, \ 741 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 742 33, \ 743 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 744 50, 49, 48, 47, 46, \ 745 75, 74, 69, 68, 72, 71, 70, \ 746 0, MAYBE_R2_AVAILABLE \ 747 9, 11, 10, 8, 7, 6, 5, 4, \ 748 3, \ 749 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 750 18, 17, 16, 15, 14, 13, 12, \ 751 64, 66, 65, \ 752 73, 1, MAYBE_R2_FIXED 67, 76, \ 753 /* AltiVec registers. */ \ 754 77, 78, \ 755 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 756 79, \ 757 96, 95, 94, 93, 92, 91, \ 758 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 759 109, 110, \ 760 111, 112, 113 \ 761 } 762 763 /* True if register is floating-point. */ 764 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 765 766 /* True if register is a condition register. */ 767 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) 768 769 /* True if register is a condition register, but not cr0. */ 770 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) 771 772 /* True if register is an integer register. */ 773 #define INT_REGNO_P(N) \ 774 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 775 776 /* SPE SIMD registers are just the GPRs. */ 777 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) 778 779 /* True if register is the XER register. */ 780 #define XER_REGNO_P(N) ((N) == XER_REGNO) 781 782 /* True if register is an AltiVec register. */ 783 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 784 785 /* Return number of consecutive hard regs needed starting at reg REGNO 786 to hold something of mode MODE. */ 787 788 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE)) 789 790 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 791 ((TARGET_32BIT && TARGET_POWERPC64 \ 792 && (GET_MODE_SIZE (MODE) > 4) \ 793 && INT_REGNO_P (REGNO)) ? 1 : 0) 794 795 #define ALTIVEC_VECTOR_MODE(MODE) \ 796 ((MODE) == V16QImode \ 797 || (MODE) == V8HImode \ 798 || (MODE) == V4SFmode \ 799 || (MODE) == V4SImode) 800 801 #define SPE_VECTOR_MODE(MODE) \ 802 ((MODE) == V4HImode \ 803 || (MODE) == V2SFmode \ 804 || (MODE) == V1DImode \ 805 || (MODE) == V2SImode) 806 807 #define UNITS_PER_SIMD_WORD \ 808 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \ 809 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD)) 810 811 /* Value is TRUE if hard register REGNO can hold a value of 812 machine-mode MODE. */ 813 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 814 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 815 816 /* Value is 1 if it is a good idea to tie two pseudo registers 817 when one has mode MODE1 and one has mode MODE2. 818 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 819 for any hard reg, then this must be 0 for correct output. */ 820 #define MODES_TIEABLE_P(MODE1, MODE2) \ 821 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 822 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 823 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 824 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 825 : GET_MODE_CLASS (MODE1) == MODE_CC \ 826 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 827 : GET_MODE_CLASS (MODE2) == MODE_CC \ 828 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 829 : SPE_VECTOR_MODE (MODE1) \ 830 ? SPE_VECTOR_MODE (MODE2) \ 831 : SPE_VECTOR_MODE (MODE2) \ 832 ? SPE_VECTOR_MODE (MODE1) \ 833 : ALTIVEC_VECTOR_MODE (MODE1) \ 834 ? ALTIVEC_VECTOR_MODE (MODE2) \ 835 : ALTIVEC_VECTOR_MODE (MODE2) \ 836 ? ALTIVEC_VECTOR_MODE (MODE1) \ 837 : 1) 838 839 /* Post-reload, we can't use any new AltiVec registers, as we already 840 emitted the vrsave mask. */ 841 842 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 843 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST]) 844 845 /* A C expression returning the cost of moving data from a register of class 846 CLASS1 to one of CLASS2. */ 847 848 #define REGISTER_MOVE_COST rs6000_register_move_cost 849 850 /* A C expressions returning the cost of moving data of MODE from a register to 851 or from memory. */ 852 853 #define MEMORY_MOVE_COST rs6000_memory_move_cost 854 855 /* Specify the cost of a branch insn; roughly the number of extra insns that 856 should be added to avoid a branch. 857 858 Set this to 3 on the RS/6000 since that is roughly the average cost of an 859 unscheduled conditional branch. */ 860 861 #define BRANCH_COST 3 862 863 /* Override BRANCH_COST heuristic which empirically produces worse 864 performance for removing short circuiting from the logical ops. */ 865 866 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 867 868 /* A fixed register used at prologue and epilogue generation to fix 869 addressing modes. The SPE needs heavy addressing fixes at the last 870 minute, and it's best to save a register for it. 871 872 AltiVec also needs fixes, but we've gotten around using r11, which 873 is actually wrong because when use_backchain_to_restore_sp is true, 874 we end up clobbering r11. 875 876 The AltiVec case needs to be fixed. Dunno if we should break ABI 877 compatibility and reserve a register for it as well.. */ 878 879 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) 880 881 /* Define this macro to change register usage conditional on target 882 flags. */ 883 884 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage () 885 886 /* Specify the registers used for certain standard purposes. 887 The values of these macros are register numbers. */ 888 889 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 890 /* #define PC_REGNUM */ 891 892 /* Register to use for pushing function arguments. */ 893 #define STACK_POINTER_REGNUM 1 894 895 /* Base register for access to local variables of the function. */ 896 #define HARD_FRAME_POINTER_REGNUM 31 897 898 /* Base register for access to local variables of the function. */ 899 #define FRAME_POINTER_REGNUM 113 900 901 /* Value should be nonzero if functions must have frame pointers. 902 Zero means the frame pointer need not be set up (and parms 903 may be accessed via the stack pointer) in functions that seem suitable. 904 This is computed in `reload', in reload1.c. */ 905 #define FRAME_POINTER_REQUIRED 0 906 907 /* Base register for access to arguments of the function. */ 908 #define ARG_POINTER_REGNUM 67 909 910 /* Place to put static chain when calling a function that requires it. */ 911 #define STATIC_CHAIN_REGNUM 11 912 913 /* Link register number. */ 914 #define LINK_REGISTER_REGNUM 65 915 916 /* Count register number. */ 917 #define COUNT_REGISTER_REGNUM 66 918 919 /* Define the classes of registers for register constraints in the 920 machine description. Also define ranges of constants. 921 922 One of the classes must always be named ALL_REGS and include all hard regs. 923 If there is more than one class, another class must be named NO_REGS 924 and contain no registers. 925 926 The name GENERAL_REGS must be the name of a class (or an alias for 927 another name such as ALL_REGS). This is the class of registers 928 that is allowed by "g" or "r" in a register constraint. 929 Also, registers outside this class are allocated only when 930 instructions express preferences for them. 931 932 The classes must be numbered in nondecreasing order; that is, 933 a larger-numbered class must never be contained completely 934 in a smaller-numbered class. 935 936 For any two classes, it is very desirable that there be another 937 class that represents their union. */ 938 939 /* The RS/6000 has three types of registers, fixed-point, floating-point, 940 and condition registers, plus three special registers, MQ, CTR, and the 941 link register. AltiVec adds a vector register class. 942 943 However, r0 is special in that it cannot be used as a base register. 944 So make a class for registers valid as base registers. 945 946 Also, cr0 is the only condition code register that can be used in 947 arithmetic insns, so make a separate class for it. */ 948 949 enum reg_class 950 { 951 NO_REGS, 952 BASE_REGS, 953 GENERAL_REGS, 954 FLOAT_REGS, 955 ALTIVEC_REGS, 956 VRSAVE_REGS, 957 VSCR_REGS, 958 SPE_ACC_REGS, 959 SPEFSCR_REGS, 960 NON_SPECIAL_REGS, 961 MQ_REGS, 962 LINK_REGS, 963 CTR_REGS, 964 LINK_OR_CTR_REGS, 965 SPECIAL_REGS, 966 SPEC_OR_GEN_REGS, 967 CR0_REGS, 968 CR_REGS, 969 NON_FLOAT_REGS, 970 XER_REGS, 971 ALL_REGS, 972 LIM_REG_CLASSES 973 }; 974 975 #define N_REG_CLASSES (int) LIM_REG_CLASSES 976 977 /* Give names of register classes as strings for dump file. */ 978 979 #define REG_CLASS_NAMES \ 980 { \ 981 "NO_REGS", \ 982 "BASE_REGS", \ 983 "GENERAL_REGS", \ 984 "FLOAT_REGS", \ 985 "ALTIVEC_REGS", \ 986 "VRSAVE_REGS", \ 987 "VSCR_REGS", \ 988 "SPE_ACC_REGS", \ 989 "SPEFSCR_REGS", \ 990 "NON_SPECIAL_REGS", \ 991 "MQ_REGS", \ 992 "LINK_REGS", \ 993 "CTR_REGS", \ 994 "LINK_OR_CTR_REGS", \ 995 "SPECIAL_REGS", \ 996 "SPEC_OR_GEN_REGS", \ 997 "CR0_REGS", \ 998 "CR_REGS", \ 999 "NON_FLOAT_REGS", \ 1000 "XER_REGS", \ 1001 "ALL_REGS" \ 1002 } 1003 1004 /* Define which registers fit in which classes. 1005 This is an initializer for a vector of HARD_REG_SET 1006 of length N_REG_CLASSES. */ 1007 1008 #define REG_CLASS_CONTENTS \ 1009 { \ 1010 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1011 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ 1012 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ 1013 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1014 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1015 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1016 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1017 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1018 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1019 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ 1020 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ 1021 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1022 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1023 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1024 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ 1025 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ 1026 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1027 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1028 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ 1029 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ 1030 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ 1031 } 1032 1033 /* The same information, inverted: 1034 Return the class number of the smallest class containing 1035 reg number REGNO. This could be a conditional expression 1036 or could index an array. */ 1037 1038 #define REGNO_REG_CLASS(REGNO) \ 1039 ((REGNO) == 0 ? GENERAL_REGS \ 1040 : (REGNO) < 32 ? BASE_REGS \ 1041 : FP_REGNO_P (REGNO) ? FLOAT_REGS \ 1042 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ 1043 : (REGNO) == CR0_REGNO ? CR0_REGS \ 1044 : CR_REGNO_P (REGNO) ? CR_REGS \ 1045 : (REGNO) == MQ_REGNO ? MQ_REGS \ 1046 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ 1047 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ 1048 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ 1049 : (REGNO) == XER_REGNO ? XER_REGS \ 1050 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ 1051 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ 1052 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ 1053 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ 1054 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \ 1055 : NO_REGS) 1056 1057 /* The class value for index registers, and the one for base regs. */ 1058 #define INDEX_REG_CLASS GENERAL_REGS 1059 #define BASE_REG_CLASS BASE_REGS 1060 1061 /* Get reg_class from a letter such as appears in the machine description. */ 1062 1063 #define REG_CLASS_FROM_LETTER(C) \ 1064 ((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \ 1065 : (C) == 'b' ? BASE_REGS \ 1066 : (C) == 'h' ? SPECIAL_REGS \ 1067 : (C) == 'q' ? MQ_REGS \ 1068 : (C) == 'c' ? CTR_REGS \ 1069 : (C) == 'l' ? LINK_REGS \ 1070 : (C) == 'v' ? ALTIVEC_REGS \ 1071 : (C) == 'x' ? CR0_REGS \ 1072 : (C) == 'y' ? CR_REGS \ 1073 : (C) == 'z' ? XER_REGS \ 1074 : NO_REGS) 1075 1076 /* The letters I, J, K, L, M, N, and P in a register constraint string 1077 can be used to stand for particular ranges of immediate operands. 1078 This macro defines what the ranges are. 1079 C is the letter, and VALUE is a constant value. 1080 Return 1 if VALUE is in the range specified by C. 1081 1082 `I' is a signed 16-bit constant 1083 `J' is a constant with only the high-order 16 bits nonzero 1084 `K' is a constant with only the low-order 16 bits nonzero 1085 `L' is a signed 16-bit constant shifted left 16 bits 1086 `M' is a constant that is greater than 31 1087 `N' is a positive constant that is an exact power of two 1088 `O' is the constant zero 1089 `P' is a constant whose negation is a signed 16-bit constant */ 1090 1091 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1092 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ 1093 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ 1094 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ 1095 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ 1096 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ 1097 : (C) == 'M' ? (VALUE) > 31 \ 1098 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ 1099 : (C) == 'O' ? (VALUE) == 0 \ 1100 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ 1101 : 0) 1102 1103 /* Similar, but for floating constants, and defining letters G and H. 1104 Here VALUE is the CONST_DOUBLE rtx itself. 1105 1106 We flag for special constants when we can copy the constant into 1107 a general register in two insns for DF/DI and one insn for SF. 1108 1109 'H' is used for DI/DF constants that take 3 insns. */ 1110 1111 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1112 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ 1113 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ 1114 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ 1115 : 0) 1116 1117 /* Optional extra constraints for this machine. 1118 1119 'Q' means that is a memory operand that is just an offset from a reg. 1120 'R' is for AIX TOC entries. 1121 'S' is a constant that can be placed into a 64-bit mask operand. 1122 'T' is a constant that can be placed into a 32-bit mask operand. 1123 'U' is for V.4 small data references. 1124 'W' is a vector constant that can be easily generated (no mem refs). 1125 'Y' is an indexed or word-aligned displacement memory operand. 1126 'Z' is an indexed or indirect memory operand. 1127 'a' is an indexed or indirect address operand. 1128 't' is for AND masks that can be performed by two rldic{l,r} insns 1129 (but excluding those that could match other constraints of anddi3.) */ 1130 1131 #define EXTRA_CONSTRAINT(OP, C) \ 1132 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 1133 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \ 1134 : (C) == 'S' ? mask64_operand (OP, DImode) \ 1135 : (C) == 'T' ? mask_operand (OP, GET_MODE (OP)) \ 1136 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ 1137 && small_data_operand (OP, GET_MODE (OP))) \ 1138 : (C) == 't' ? (mask64_2_operand (OP, DImode) \ 1139 && (fixed_regs[CR0_REGNO] \ 1140 || !logical_operand (OP, DImode)) \ 1141 && !mask_operand (OP, DImode) \ 1142 && !mask64_operand (OP, DImode)) \ 1143 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \ 1144 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \ 1145 : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \ 1146 : (C) == 'a' ? (indexed_or_indirect_address (OP, GET_MODE (OP))) \ 1147 : 0) 1148 1149 /* Define which constraints are memory constraints. Tell reload 1150 that any memory address can be reloaded by copying the 1151 memory address into a base register if required. */ 1152 1153 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ 1154 ((C) == 'Q' || (C) == 'Y' || (C) == 'Z') 1155 1156 /* Define which constraints should be treated like address constraints 1157 by the reload pass. */ 1158 1159 #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \ 1160 ((C) == 'a') 1161 1162 /* Given an rtx X being reloaded into a reg required to be 1163 in class CLASS, return the class of reg to actually use. 1164 In general this is just CLASS; but on some machines 1165 in some cases it is preferable to use a more restrictive class. 1166 1167 On the RS/6000, we have to return NO_REGS when we want to reload a 1168 floating-point CONST_DOUBLE to force it to be copied to memory. 1169 1170 We also don't want to reload integer values into floating-point 1171 registers if we can at all help it. In fact, this can 1172 cause reload to die, if it tries to generate a reload of CTR 1173 into a FP register and discovers it doesn't have the memory location 1174 required. 1175 1176 ??? Would it be a good idea to have reload do the converse, that is 1177 try to reload floating modes into FP registers if possible? 1178 */ 1179 1180 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1181 ((CONSTANT_P (X) \ 1182 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \ 1183 ? NO_REGS \ 1184 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 1185 && (CLASS) == NON_SPECIAL_REGS) \ 1186 ? GENERAL_REGS \ 1187 : (CLASS)) 1188 1189 /* Return the register class of a scratch register needed to copy IN into 1190 or out of a register in CLASS in MODE. If it can be done directly, 1191 NO_REGS is returned. */ 1192 1193 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1194 secondary_reload_class (CLASS, MODE, IN) 1195 1196 /* If we are copying between FP or AltiVec registers and anything 1197 else, we need a memory location. */ 1198 1199 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1200 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ 1201 || (CLASS2) == FLOAT_REGS \ 1202 || (CLASS1) == ALTIVEC_REGS \ 1203 || (CLASS2) == ALTIVEC_REGS)) 1204 1205 /* Return the maximum number of consecutive registers 1206 needed to represent mode MODE in a register of class CLASS. 1207 1208 On RS/6000, this is the size of MODE in words, 1209 except in the FP regs, where a single reg is enough for two words. */ 1210 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1211 (((CLASS) == FLOAT_REGS) \ 1212 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 1213 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \ 1214 ? 1 \ 1215 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1216 1217 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1218 1219 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1220 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1221 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \ 1222 || TARGET_IEEEQUAD) \ 1223 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \ 1224 : (((TARGET_E500_DOUBLE \ 1225 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \ 1226 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \ 1227 || (TARGET_SPE \ 1228 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \ 1229 && reg_classes_intersect_p (GENERAL_REGS, CLASS))) 1230 1231 /* Stack layout; function entry, exit and calling. */ 1232 1233 /* Enumeration to give which calling sequence to use. */ 1234 enum rs6000_abi { 1235 ABI_NONE, 1236 ABI_AIX, /* IBM's AIX */ 1237 ABI_V4, /* System V.4/eabi */ 1238 ABI_DARWIN /* Apple's Darwin (OS X kernel) */ 1239 }; 1240 1241 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ 1242 1243 /* Define this if pushing a word on the stack 1244 makes the stack pointer a smaller address. */ 1245 #define STACK_GROWS_DOWNWARD 1246 1247 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1248 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1249 1250 /* Define this to nonzero if the nominal address of the stack frame 1251 is at the high-address end of the local variables; 1252 that is, each additional local variable allocated 1253 goes at a more negative offset in the frame. 1254 1255 On the RS/6000, we grow upwards, from the area after the outgoing 1256 arguments. */ 1257 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0) 1258 1259 /* Size of the outgoing register save area */ 1260 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1261 || DEFAULT_ABI == ABI_DARWIN) \ 1262 ? (TARGET_64BIT ? 64 : 32) \ 1263 : 0) 1264 1265 /* Size of the fixed area on the stack */ 1266 #define RS6000_SAVE_AREA \ 1267 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1268 << (TARGET_64BIT ? 1 : 0)) 1269 1270 /* MEM representing address to save the TOC register */ 1271 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1272 plus_constant (stack_pointer_rtx, \ 1273 (TARGET_32BIT ? 20 : 40))) 1274 1275 /* Align an address */ 1276 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1277 1278 /* Offset within stack frame to start allocating local variables at. 1279 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1280 first local allocated. Otherwise, it is the offset to the BEGINNING 1281 of the first local allocated. 1282 1283 On the RS/6000, the frame pointer is the same as the stack pointer, 1284 except for dynamic allocations. So we start after the fixed area and 1285 outgoing parameter area. */ 1286 1287 #define STARTING_FRAME_OFFSET \ 1288 (FRAME_GROWS_DOWNWARD \ 1289 ? 0 \ 1290 : (RS6000_ALIGN (current_function_outgoing_args_size, \ 1291 TARGET_ALTIVEC ? 16 : 8) \ 1292 + RS6000_SAVE_AREA)) 1293 1294 /* Offset from the stack pointer register to an item dynamically 1295 allocated on the stack, e.g., by `alloca'. 1296 1297 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1298 length of the outgoing arguments. The default is correct for most 1299 machines. See `function.c' for details. */ 1300 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1301 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1302 TARGET_ALTIVEC ? 16 : 8) \ 1303 + (STACK_POINTER_OFFSET)) 1304 1305 /* If we generate an insn to push BYTES bytes, 1306 this says how many the stack pointer really advances by. 1307 On RS/6000, don't define this because there are no push insns. */ 1308 /* #define PUSH_ROUNDING(BYTES) */ 1309 1310 /* Offset of first parameter from the argument pointer register value. 1311 On the RS/6000, we define the argument pointer to the start of the fixed 1312 area. */ 1313 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1314 1315 /* Offset from the argument pointer register value to the top of 1316 stack. This is different from FIRST_PARM_OFFSET because of the 1317 register save area. */ 1318 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1319 1320 /* Define this if stack space is still allocated for a parameter passed 1321 in a register. The value is the number of bytes allocated to this 1322 area. */ 1323 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1324 1325 /* Define this if the above stack space is to be considered part of the 1326 space allocated by the caller. */ 1327 #define OUTGOING_REG_PARM_STACK_SPACE 1328 1329 /* This is the difference between the logical top of stack and the actual sp. 1330 1331 For the RS/6000, sp points past the fixed area. */ 1332 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1333 1334 /* Define this if the maximum size of all the outgoing args is to be 1335 accumulated and pushed during the prologue. The amount can be 1336 found in the variable current_function_outgoing_args_size. */ 1337 #define ACCUMULATE_OUTGOING_ARGS 1 1338 1339 /* Value is the number of bytes of arguments automatically 1340 popped when returning from a subroutine call. 1341 FUNDECL is the declaration node of the function (as a tree), 1342 FUNTYPE is the data type of the function (as a tree), 1343 or for a library call it is an identifier node for the subroutine name. 1344 SIZE is the number of bytes of arguments passed on the stack. */ 1345 1346 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1347 1348 /* Define how to find the value returned by a function. 1349 VALTYPE is the data type of the value (as a tree). 1350 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1351 otherwise, FUNC is 0. */ 1352 1353 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC)) 1354 1355 /* Define how to find the value returned by a library function 1356 assuming the value has mode MODE. */ 1357 1358 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1359 1360 /* DRAFT_V4_STRUCT_RET defaults off. */ 1361 #define DRAFT_V4_STRUCT_RET 0 1362 1363 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1364 #define DEFAULT_PCC_STRUCT_RETURN 0 1365 1366 /* Mode of stack savearea. 1367 FUNCTION is VOIDmode because calling convention maintains SP. 1368 BLOCK needs Pmode for SP. 1369 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1370 #define STACK_SAVEAREA_MODE(LEVEL) \ 1371 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1372 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1373 1374 /* Minimum and maximum general purpose registers used to hold arguments. */ 1375 #define GP_ARG_MIN_REG 3 1376 #define GP_ARG_MAX_REG 10 1377 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1378 1379 /* Minimum and maximum floating point registers used to hold arguments. */ 1380 #define FP_ARG_MIN_REG 33 1381 #define FP_ARG_AIX_MAX_REG 45 1382 #define FP_ARG_V4_MAX_REG 40 1383 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1384 || DEFAULT_ABI == ABI_DARWIN) \ 1385 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1386 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1387 1388 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1389 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1390 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1391 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1392 1393 /* Return registers */ 1394 #define GP_ARG_RETURN GP_ARG_MIN_REG 1395 #define FP_ARG_RETURN FP_ARG_MIN_REG 1396 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1397 1398 /* Flags for the call/call_value rtl operations set up by function_arg */ 1399 #define CALL_NORMAL 0x00000000 /* no special processing */ 1400 /* Bits in 0x00000001 are unused. */ 1401 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1402 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1403 #define CALL_LONG 0x00000008 /* always call indirect */ 1404 #define CALL_LIBCALL 0x00000010 /* libcall */ 1405 1406 /* We don't have prologue and epilogue functions to save/restore 1407 everything for most ABIs. */ 1408 #define WORLD_SAVE_P(INFO) 0 1409 1410 /* 1 if N is a possible register number for a function value 1411 as seen by the caller. 1412 1413 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1414 #define FUNCTION_VALUE_REGNO_P(N) \ 1415 ((N) == GP_ARG_RETURN \ 1416 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1417 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1418 1419 /* 1 if N is a possible register number for function argument passing. 1420 On RS/6000, these are r3-r10 and fp1-fp13. 1421 On AltiVec, v2 - v13 are used for passing vectors. */ 1422 #define FUNCTION_ARG_REGNO_P(N) \ 1423 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1424 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1425 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1426 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1427 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1428 1429 /* Define a data type for recording info about an argument list 1430 during the scan of that argument list. This data type should 1431 hold all necessary information about the function itself 1432 and about the args processed so far, enough to enable macros 1433 such as FUNCTION_ARG to determine where the next arg should go. 1434 1435 On the RS/6000, this is a structure. The first element is the number of 1436 total argument words, the second is used to store the next 1437 floating-point register number, and the third says how many more args we 1438 have prototype types for. 1439 1440 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1441 the next available GP register, `fregno' is the next available FP 1442 register, and `words' is the number of words used on the stack. 1443 1444 The varargs/stdarg support requires that this structure's size 1445 be a multiple of sizeof(int). */ 1446 1447 typedef struct rs6000_args 1448 { 1449 int words; /* # words used for passing GP registers */ 1450 int fregno; /* next available FP register */ 1451 int vregno; /* next available AltiVec register */ 1452 int nargs_prototype; /* # args left in the current prototype */ 1453 int prototype; /* Whether a prototype was defined */ 1454 int stdarg; /* Whether function is a stdarg function. */ 1455 int call_cookie; /* Do special things for this call */ 1456 int sysv_gregno; /* next available GP register */ 1457 int intoffset; /* running offset in struct (darwin64) */ 1458 int use_stack; /* any part of struct on stack (darwin64) */ 1459 int named; /* false for varargs params */ 1460 } CUMULATIVE_ARGS; 1461 1462 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1463 for a call to a function whose data type is FNTYPE. 1464 For a library call, FNTYPE is 0. */ 1465 1466 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1467 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS) 1468 1469 /* Similar, but when scanning the definition of a procedure. We always 1470 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1471 1472 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1473 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000) 1474 1475 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1476 1477 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1478 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0) 1479 1480 /* Update the data in CUM to advance over an argument 1481 of mode MODE and data type TYPE. 1482 (TYPE is null for libcalls where that information may not be available.) */ 1483 1484 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1485 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0) 1486 1487 /* Determine where to put an argument to a function. 1488 Value is zero to push the argument on the stack, 1489 or a hard register in which to store the argument. 1490 1491 MODE is the argument's machine mode. 1492 TYPE is the data type of the argument (as a tree). 1493 This is null for libcalls where that information may 1494 not be available. 1495 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1496 the preceding args and about the function being called. 1497 NAMED is nonzero if this argument is a named parameter 1498 (otherwise it is an extra parameter matching an ellipsis). 1499 1500 On RS/6000 the first eight words of non-FP are normally in registers 1501 and the rest are pushed. The first 13 FP args are in registers. 1502 1503 If this is floating-point and no prototype is specified, we use 1504 both an FP and integer register (or possibly FP reg and stack). Library 1505 functions (when TYPE is zero) always have the proper types for args, 1506 so we can pass the FP value just in one register. emit_library_function 1507 doesn't support EXPR_LIST anyway. */ 1508 1509 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1510 function_arg (&CUM, MODE, TYPE, NAMED) 1511 1512 /* If defined, a C expression which determines whether, and in which 1513 direction, to pad out an argument with extra space. The value 1514 should be of type `enum direction': either `upward' to pad above 1515 the argument, `downward' to pad below, or `none' to inhibit 1516 padding. */ 1517 1518 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1519 1520 /* If defined, a C expression that gives the alignment boundary, in bits, 1521 of an argument with the specified mode and type. If it is not defined, 1522 PARM_BOUNDARY is used for all arguments. */ 1523 1524 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1525 function_arg_boundary (MODE, TYPE) 1526 1527 /* Implement `va_start' for varargs and stdarg. */ 1528 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1529 rs6000_va_start (valist, nextarg) 1530 1531 #define PAD_VARARGS_DOWN \ 1532 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1533 1534 /* Output assembler code to FILE to increment profiler label # LABELNO 1535 for profiling a function entry. */ 1536 1537 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1538 output_function_profiler ((FILE), (LABELNO)); 1539 1540 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1541 the stack pointer does not matter. No definition is equivalent to 1542 always zero. 1543 1544 On the RS/6000, this is nonzero because we can restore the stack from 1545 its backpointer, which we maintain. */ 1546 #define EXIT_IGNORE_STACK 1 1547 1548 /* Define this macro as a C expression that is nonzero for registers 1549 that are used by the epilogue or the return' pattern. The stack 1550 and frame pointer registers are already be assumed to be used as 1551 needed. */ 1552 1553 #define EPILOGUE_USES(REGNO) \ 1554 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ 1555 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1556 || (current_function_calls_eh_return \ 1557 && TARGET_AIX \ 1558 && (REGNO) == 2)) 1559 1560 1561 /* TRAMPOLINE_TEMPLATE deleted */ 1562 1563 /* Length in units of the trampoline for entering a nested function. */ 1564 1565 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1566 1567 /* Emit RTL insns to initialize the variable parts of a trampoline. 1568 FNADDR is an RTX for the address of the function's pure code. 1569 CXT is an RTX for the static chain value for the function. */ 1570 1571 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ 1572 rs6000_initialize_trampoline (ADDR, FNADDR, CXT) 1573 1574 /* Definitions for __builtin_return_address and __builtin_frame_address. 1575 __builtin_return_address (0) should give link register (65), enable 1576 this. */ 1577 /* This should be uncommented, so that the link register is used, but 1578 currently this would result in unmatched insns and spilling fixed 1579 registers so we'll leave it for another day. When these problems are 1580 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1581 (mrs) */ 1582 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1583 1584 /* Number of bytes into the frame return addresses can be found. See 1585 rs6000_stack_info in rs6000.c for more information on how the different 1586 abi's store the return address. */ 1587 #define RETURN_ADDRESS_OFFSET \ 1588 ((DEFAULT_ABI == ABI_AIX \ 1589 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ 1590 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1591 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1592 1593 /* The current return address is in link register (65). The return address 1594 of anything farther back is accessed normally at an offset of 8 from the 1595 frame pointer. */ 1596 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1597 (rs6000_return_addr (COUNT, FRAME)) 1598 1599 1600 /* Definitions for register eliminations. 1601 1602 We have two registers that can be eliminated on the RS/6000. First, the 1603 frame pointer register can often be eliminated in favor of the stack 1604 pointer register. Secondly, the argument pointer register can always be 1605 eliminated; it is replaced with either the stack or frame pointer. 1606 1607 In addition, we use the elimination mechanism to see if r30 is needed 1608 Initially we assume that it isn't. If it is, we spill it. This is done 1609 by making it an eliminable register. We replace it with itself so that 1610 if it isn't needed, then existing uses won't be modified. */ 1611 1612 /* This is an array of structures. Each structure initializes one pair 1613 of eliminable registers. The "from" register number is given first, 1614 followed by "to". Eliminations of the same "from" register are listed 1615 in order of preference. */ 1616 #define ELIMINABLE_REGS \ 1617 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1618 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1619 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1620 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1621 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1622 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1623 1624 /* Given FROM and TO register numbers, say whether this elimination is allowed. 1625 Frame pointer elimination is automatically handled. 1626 1627 For the RS/6000, if frame pointer elimination is being done, we would like 1628 to convert ap into fp, not sp. 1629 1630 We need r30 if -mminimal-toc was specified, and there are constant pool 1631 references. */ 1632 1633 #define CAN_ELIMINATE(FROM, TO) \ 1634 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 1635 ? ! frame_pointer_needed \ 1636 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ 1637 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ 1638 : 1) 1639 1640 /* Define the offset between two registers, one to be eliminated, and the other 1641 its replacement, at the start of a routine. */ 1642 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1643 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1644 1645 /* Addressing modes, and classification of registers for them. */ 1646 1647 #define HAVE_PRE_DECREMENT 1 1648 #define HAVE_PRE_INCREMENT 1 1649 1650 /* Macros to check register numbers against specific register classes. */ 1651 1652 /* These assume that REGNO is a hard or pseudo reg number. 1653 They give nonzero only if REGNO is a hard reg of the suitable class 1654 or a pseudo reg currently allocated to a suitable hard reg. 1655 Since they use reg_renumber, they are safe only once reg_renumber 1656 has been allocated, which happens in local-alloc.c. */ 1657 1658 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1659 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1660 ? (REGNO) <= 31 || (REGNO) == 67 \ 1661 || (REGNO) == FRAME_POINTER_REGNUM \ 1662 : (reg_renumber[REGNO] >= 0 \ 1663 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1664 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1665 1666 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1667 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1668 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1669 || (REGNO) == FRAME_POINTER_REGNUM \ 1670 : (reg_renumber[REGNO] > 0 \ 1671 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1672 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1673 1674 /* Maximum number of registers that can appear in a valid memory address. */ 1675 1676 #define MAX_REGS_PER_ADDRESS 2 1677 1678 /* Recognize any constant value that is a valid address. */ 1679 1680 #define CONSTANT_ADDRESS_P(X) \ 1681 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1682 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1683 || GET_CODE (X) == HIGH) 1684 1685 /* Nonzero if the constant value X is a legitimate general operand. 1686 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1687 1688 On the RS/6000, all integer constants are acceptable, most won't be valid 1689 for particular insns, though. Only easy FP constants are 1690 acceptable. */ 1691 1692 #define LEGITIMATE_CONSTANT_P(X) \ 1693 (((GET_CODE (X) != CONST_DOUBLE \ 1694 && GET_CODE (X) != CONST_VECTOR) \ 1695 || GET_MODE (X) == VOIDmode \ 1696 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ 1697 || easy_fp_constant (X, GET_MODE (X)) \ 1698 || easy_vector_constant (X, GET_MODE (X))) \ 1699 && !rs6000_tls_referenced_p (X)) 1700 1701 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1702 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1703 && EASY_VECTOR_15((n) >> 1) \ 1704 && ((n) & 1) == 0) 1705 1706 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1707 and check its validity for a certain class. 1708 We have two alternate definitions for each of them. 1709 The usual definition accepts all pseudo regs; the other rejects 1710 them unless they have been allocated suitable hard regs. 1711 The symbol REG_OK_STRICT causes the latter definition to be used. 1712 1713 Most source files want to accept pseudo regs in the hope that 1714 they will get allocated to the class that the insn wants them to be in. 1715 Source files for reload pass need to be strict. 1716 After reload, it makes no difference, since pseudo regs have 1717 been eliminated by then. */ 1718 1719 #ifdef REG_OK_STRICT 1720 # define REG_OK_STRICT_FLAG 1 1721 #else 1722 # define REG_OK_STRICT_FLAG 0 1723 #endif 1724 1725 /* Nonzero if X is a hard reg that can be used as an index 1726 or if it is a pseudo reg in the non-strict case. */ 1727 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1728 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1729 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1730 1731 /* Nonzero if X is a hard reg that can be used as a base reg 1732 or if it is a pseudo reg in the non-strict case. */ 1733 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1734 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1735 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1736 1737 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) 1738 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) 1739 1740 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1741 that is a valid memory address for an instruction. 1742 The MODE argument is the machine mode for the MEM expression 1743 that wants to use this address. 1744 1745 On the RS/6000, there are four valid address: a SYMBOL_REF that 1746 refers to a constant pool entry of an address (or the sum of it 1747 plus a constant), a short (16-bit signed) constant plus a register, 1748 the sum of two registers, or a register indirect, possibly with an 1749 auto-increment. For DFmode and DImode with a constant plus register, 1750 we must ensure that both words are addressable or PowerPC64 with offset 1751 word aligned. 1752 1753 For modes spanning multiple registers (DFmode in 32-bit GPRs, 1754 32-bit DImode, TImode), indexed addressing cannot be used because 1755 adjacent memory cells are accessed by adding word-sized offsets 1756 during assembly output. */ 1757 1758 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1759 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ 1760 goto ADDR; \ 1761 } 1762 1763 /* Try machine-dependent ways of modifying an illegitimate address 1764 to be legitimate. If we find one, return the new, valid address. 1765 This macro is used in only one place: `memory_address' in explow.c. 1766 1767 OLDX is the address as it was before break_out_memory_refs was called. 1768 In some cases it is useful to look at this to decide what needs to be done. 1769 1770 MODE and WIN are passed so that this macro can use 1771 GO_IF_LEGITIMATE_ADDRESS. 1772 1773 It is always safe for this macro to do nothing. It exists to recognize 1774 opportunities to optimize the output. 1775 1776 On RS/6000, first check for the sum of a register with a constant 1777 integer that is out of range. If so, generate code to add the 1778 constant with the low-order 16 bits masked to the register and force 1779 this result into another register (this can be done with `cau'). 1780 Then generate an address of REG+(CONST&0xffff), allowing for the 1781 possibility of bit 16 being a one. 1782 1783 Then check for the sum of a register and something not constant, try to 1784 load the other things into a register and return the sum. */ 1785 1786 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1787 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ 1788 if (result != NULL_RTX) \ 1789 { \ 1790 (X) = result; \ 1791 goto WIN; \ 1792 } \ 1793 } 1794 1795 /* Try a machine-dependent way of reloading an illegitimate address 1796 operand. If we find one, push the reload and jump to WIN. This 1797 macro is used in only one place: `find_reloads_address' in reload.c. 1798 1799 Implemented on rs6000 by rs6000_legitimize_reload_address. 1800 Note that (X) is evaluated twice; this is safe in current usage. */ 1801 1802 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1803 do { \ 1804 int win; \ 1805 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1806 (int)(TYPE), (IND_LEVELS), &win); \ 1807 if ( win ) \ 1808 goto WIN; \ 1809 } while (0) 1810 1811 /* Go to LABEL if ADDR (a legitimate address expression) 1812 has an effect that depends on the machine mode it is used for. */ 1813 1814 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1815 do { \ 1816 if (rs6000_mode_dependent_address (ADDR)) \ 1817 goto LABEL; \ 1818 } while (0) 1819 1820 /* The register number of the register used to address a table of 1821 static data addresses in memory. In some cases this register is 1822 defined by a processor's "application binary interface" (ABI). 1823 When this macro is defined, RTL is generated for this register 1824 once, as with the stack pointer and frame pointer registers. If 1825 this macro is not defined, it is up to the machine-dependent files 1826 to allocate such a register (if necessary). */ 1827 1828 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1829 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 1830 1831 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1832 1833 /* Define this macro if the register defined by 1834 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1835 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1836 1837 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1838 1839 /* A C expression that is nonzero if X is a legitimate immediate 1840 operand on the target machine when generating position independent 1841 code. You can assume that X satisfies `CONSTANT_P', so you need 1842 not check this. You can also assume FLAG_PIC is true, so you need 1843 not check it either. You need not define this macro if all 1844 constants (including `SYMBOL_REF') can be immediate operands when 1845 generating position independent code. */ 1846 1847 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1848 1849 /* Define this if some processing needs to be done immediately before 1850 emitting code for an insn. */ 1851 1852 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ 1853 1854 /* Specify the machine mode that this machine uses 1855 for the index in the tablejump instruction. */ 1856 #define CASE_VECTOR_MODE SImode 1857 1858 /* Define as C expression which evaluates to nonzero if the tablejump 1859 instruction expects the table to contain offsets from the address of the 1860 table. 1861 Do not define this if the table should contain absolute addresses. */ 1862 #define CASE_VECTOR_PC_RELATIVE 1 1863 1864 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1865 #define DEFAULT_SIGNED_CHAR 0 1866 1867 /* This flag, if defined, says the same insns that convert to a signed fixnum 1868 also convert validly to an unsigned one. */ 1869 1870 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ 1871 1872 /* An integer expression for the size in bits of the largest integer machine 1873 mode that should actually be used. */ 1874 1875 /* Allow pairs of registers to be used, which is the intent of the default. */ 1876 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1877 1878 /* Max number of bytes we can move from memory to memory 1879 in one reasonably fast instruction. */ 1880 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1881 #define MAX_MOVE_MAX 8 1882 1883 /* Nonzero if access to memory by bytes is no faster than for words. 1884 Also nonzero if doing byte operations (specifically shifts) in registers 1885 is undesirable. */ 1886 #define SLOW_BYTE_ACCESS 1 1887 1888 /* Define if operations between registers always perform the operation 1889 on the full register even if a narrower mode is specified. */ 1890 #define WORD_REGISTER_OPERATIONS 1891 1892 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1893 will either zero-extend or sign-extend. The value of this macro should 1894 be the code that says which one of the two operations is implicitly 1895 done, UNKNOWN if none. */ 1896 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1897 1898 /* Define if loading short immediate values into registers sign extends. */ 1899 #define SHORT_IMMEDIATES_SIGN_EXTEND 1900 1901 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1902 is done just by pretending it is already truncated. */ 1903 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1904 1905 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1906 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1907 ((VALUE) = ((MODE) == SImode ? 32 : 64)) 1908 1909 /* The CTZ patterns return -1 for input of zero. */ 1910 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1) 1911 1912 /* Specify the machine mode that pointers have. 1913 After generation of rtl, the compiler makes no further distinction 1914 between pointers and any other objects of this machine mode. */ 1915 #define Pmode (TARGET_32BIT ? SImode : DImode) 1916 1917 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1918 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1919 1920 /* Mode of a function address in a call instruction (for indexing purposes). 1921 Doesn't matter on RS/6000. */ 1922 #define FUNCTION_MODE SImode 1923 1924 /* Define this if addresses of constant functions 1925 shouldn't be put through pseudo regs where they can be cse'd. 1926 Desirable on machines where ordinary constants are expensive 1927 but a CALL with constant address is cheap. */ 1928 #define NO_FUNCTION_CSE 1929 1930 /* Define this to be nonzero if shift instructions ignore all but the low-order 1931 few bits. 1932 1933 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1934 have been dropped from the PowerPC architecture. */ 1935 1936 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) 1937 1938 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 1939 should be adjusted to reflect any required changes. This macro is used when 1940 there is some systematic length adjustment required that would be difficult 1941 to express in the length attribute. */ 1942 1943 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 1944 1945 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 1946 COMPARE, return the mode to be used for the comparison. For 1947 floating-point, CCFPmode should be used. CCUNSmode should be used 1948 for unsigned comparisons. CCEQmode should be used when we are 1949 doing an inequality comparison on the result of a 1950 comparison. CCmode should be used in all other cases. */ 1951 1952 #define SELECT_CC_MODE(OP,X,Y) \ 1953 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ 1954 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1955 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1956 ? CCEQmode : CCmode)) 1957 1958 /* Can the condition code MODE be safely reversed? This is safe in 1959 all cases on this port, because at present it doesn't use the 1960 trapping FP comparisons (fcmpo). */ 1961 #define REVERSIBLE_CC_MODE(MODE) 1 1962 1963 /* Given a condition code and a mode, return the inverse condition. */ 1964 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1965 1966 /* Define the information needed to generate branch and scc insns. This is 1967 stored from the compare operation. */ 1968 1969 extern GTY(()) rtx rs6000_compare_op0; 1970 extern GTY(()) rtx rs6000_compare_op1; 1971 extern int rs6000_compare_fp_p; 1972 1973 /* Control the assembler format that we output. */ 1974 1975 /* A C string constant describing how to begin a comment in the target 1976 assembler language. The compiler assumes that the comment will end at 1977 the end of the line. */ 1978 #define ASM_COMMENT_START " #" 1979 1980 /* Flag to say the TOC is initialized */ 1981 extern int toc_initialized; 1982 1983 /* Macro to output a special constant pool entry. Go to WIN if we output 1984 it. Otherwise, it is written the usual way. 1985 1986 On the RS/6000, toc entries are handled this way. */ 1987 1988 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1989 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1990 { \ 1991 output_toc (FILE, X, LABELNO, MODE); \ 1992 goto WIN; \ 1993 } \ 1994 } 1995 1996 #ifdef HAVE_GAS_WEAK 1997 #define RS6000_WEAK 1 1998 #else 1999 #define RS6000_WEAK 0 2000 #endif 2001 2002 #if RS6000_WEAK 2003 /* Used in lieu of ASM_WEAKEN_LABEL. */ 2004 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2005 do \ 2006 { \ 2007 fputs ("\t.weak\t", (FILE)); \ 2008 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2009 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2010 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2011 { \ 2012 if (TARGET_XCOFF) \ 2013 fputs ("[DS]", (FILE)); \ 2014 fputs ("\n\t.weak\t.", (FILE)); \ 2015 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2016 } \ 2017 fputc ('\n', (FILE)); \ 2018 if (VAL) \ 2019 { \ 2020 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2021 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2022 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2023 { \ 2024 fputs ("\t.set\t.", (FILE)); \ 2025 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2026 fputs (",.", (FILE)); \ 2027 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2028 fputc ('\n', (FILE)); \ 2029 } \ 2030 } \ 2031 } \ 2032 while (0) 2033 #endif 2034 2035 #if HAVE_GAS_WEAKREF 2036 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2037 do \ 2038 { \ 2039 fputs ("\t.weakref\t", (FILE)); \ 2040 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2041 fputs (", ", (FILE)); \ 2042 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2043 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2044 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2045 { \ 2046 fputs ("\n\t.weakref\t.", (FILE)); \ 2047 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2048 fputs (", .", (FILE)); \ 2049 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2050 } \ 2051 fputc ('\n', (FILE)); \ 2052 } while (0) 2053 #endif 2054 2055 /* This implements the `alias' attribute. */ 2056 #undef ASM_OUTPUT_DEF_FROM_DECLS 2057 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2058 do \ 2059 { \ 2060 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2061 const char *name = IDENTIFIER_POINTER (TARGET); \ 2062 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2063 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2064 { \ 2065 if (TREE_PUBLIC (DECL)) \ 2066 { \ 2067 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2068 { \ 2069 fputs ("\t.globl\t.", FILE); \ 2070 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2071 putc ('\n', FILE); \ 2072 } \ 2073 } \ 2074 else if (TARGET_XCOFF) \ 2075 { \ 2076 fputs ("\t.lglobl\t.", FILE); \ 2077 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2078 putc ('\n', FILE); \ 2079 } \ 2080 fputs ("\t.set\t.", FILE); \ 2081 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2082 fputs (",.", FILE); \ 2083 RS6000_OUTPUT_BASENAME (FILE, name); \ 2084 fputc ('\n', FILE); \ 2085 } \ 2086 ASM_OUTPUT_DEF (FILE, alias, name); \ 2087 } \ 2088 while (0) 2089 2090 #define TARGET_ASM_FILE_START rs6000_file_start 2091 2092 /* Output to assembler file text saying following lines 2093 may contain character constants, extra white space, comments, etc. */ 2094 2095 #define ASM_APP_ON "" 2096 2097 /* Output to assembler file text saying following lines 2098 no longer contain unusual constructs. */ 2099 2100 #define ASM_APP_OFF "" 2101 2102 /* How to refer to registers in assembler output. 2103 This sequence is indexed by compiler's hard-register-number (see above). */ 2104 2105 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2106 2107 #define REGISTER_NAMES \ 2108 { \ 2109 &rs6000_reg_names[ 0][0], /* r0 */ \ 2110 &rs6000_reg_names[ 1][0], /* r1 */ \ 2111 &rs6000_reg_names[ 2][0], /* r2 */ \ 2112 &rs6000_reg_names[ 3][0], /* r3 */ \ 2113 &rs6000_reg_names[ 4][0], /* r4 */ \ 2114 &rs6000_reg_names[ 5][0], /* r5 */ \ 2115 &rs6000_reg_names[ 6][0], /* r6 */ \ 2116 &rs6000_reg_names[ 7][0], /* r7 */ \ 2117 &rs6000_reg_names[ 8][0], /* r8 */ \ 2118 &rs6000_reg_names[ 9][0], /* r9 */ \ 2119 &rs6000_reg_names[10][0], /* r10 */ \ 2120 &rs6000_reg_names[11][0], /* r11 */ \ 2121 &rs6000_reg_names[12][0], /* r12 */ \ 2122 &rs6000_reg_names[13][0], /* r13 */ \ 2123 &rs6000_reg_names[14][0], /* r14 */ \ 2124 &rs6000_reg_names[15][0], /* r15 */ \ 2125 &rs6000_reg_names[16][0], /* r16 */ \ 2126 &rs6000_reg_names[17][0], /* r17 */ \ 2127 &rs6000_reg_names[18][0], /* r18 */ \ 2128 &rs6000_reg_names[19][0], /* r19 */ \ 2129 &rs6000_reg_names[20][0], /* r20 */ \ 2130 &rs6000_reg_names[21][0], /* r21 */ \ 2131 &rs6000_reg_names[22][0], /* r22 */ \ 2132 &rs6000_reg_names[23][0], /* r23 */ \ 2133 &rs6000_reg_names[24][0], /* r24 */ \ 2134 &rs6000_reg_names[25][0], /* r25 */ \ 2135 &rs6000_reg_names[26][0], /* r26 */ \ 2136 &rs6000_reg_names[27][0], /* r27 */ \ 2137 &rs6000_reg_names[28][0], /* r28 */ \ 2138 &rs6000_reg_names[29][0], /* r29 */ \ 2139 &rs6000_reg_names[30][0], /* r30 */ \ 2140 &rs6000_reg_names[31][0], /* r31 */ \ 2141 \ 2142 &rs6000_reg_names[32][0], /* fr0 */ \ 2143 &rs6000_reg_names[33][0], /* fr1 */ \ 2144 &rs6000_reg_names[34][0], /* fr2 */ \ 2145 &rs6000_reg_names[35][0], /* fr3 */ \ 2146 &rs6000_reg_names[36][0], /* fr4 */ \ 2147 &rs6000_reg_names[37][0], /* fr5 */ \ 2148 &rs6000_reg_names[38][0], /* fr6 */ \ 2149 &rs6000_reg_names[39][0], /* fr7 */ \ 2150 &rs6000_reg_names[40][0], /* fr8 */ \ 2151 &rs6000_reg_names[41][0], /* fr9 */ \ 2152 &rs6000_reg_names[42][0], /* fr10 */ \ 2153 &rs6000_reg_names[43][0], /* fr11 */ \ 2154 &rs6000_reg_names[44][0], /* fr12 */ \ 2155 &rs6000_reg_names[45][0], /* fr13 */ \ 2156 &rs6000_reg_names[46][0], /* fr14 */ \ 2157 &rs6000_reg_names[47][0], /* fr15 */ \ 2158 &rs6000_reg_names[48][0], /* fr16 */ \ 2159 &rs6000_reg_names[49][0], /* fr17 */ \ 2160 &rs6000_reg_names[50][0], /* fr18 */ \ 2161 &rs6000_reg_names[51][0], /* fr19 */ \ 2162 &rs6000_reg_names[52][0], /* fr20 */ \ 2163 &rs6000_reg_names[53][0], /* fr21 */ \ 2164 &rs6000_reg_names[54][0], /* fr22 */ \ 2165 &rs6000_reg_names[55][0], /* fr23 */ \ 2166 &rs6000_reg_names[56][0], /* fr24 */ \ 2167 &rs6000_reg_names[57][0], /* fr25 */ \ 2168 &rs6000_reg_names[58][0], /* fr26 */ \ 2169 &rs6000_reg_names[59][0], /* fr27 */ \ 2170 &rs6000_reg_names[60][0], /* fr28 */ \ 2171 &rs6000_reg_names[61][0], /* fr29 */ \ 2172 &rs6000_reg_names[62][0], /* fr30 */ \ 2173 &rs6000_reg_names[63][0], /* fr31 */ \ 2174 \ 2175 &rs6000_reg_names[64][0], /* mq */ \ 2176 &rs6000_reg_names[65][0], /* lr */ \ 2177 &rs6000_reg_names[66][0], /* ctr */ \ 2178 &rs6000_reg_names[67][0], /* ap */ \ 2179 \ 2180 &rs6000_reg_names[68][0], /* cr0 */ \ 2181 &rs6000_reg_names[69][0], /* cr1 */ \ 2182 &rs6000_reg_names[70][0], /* cr2 */ \ 2183 &rs6000_reg_names[71][0], /* cr3 */ \ 2184 &rs6000_reg_names[72][0], /* cr4 */ \ 2185 &rs6000_reg_names[73][0], /* cr5 */ \ 2186 &rs6000_reg_names[74][0], /* cr6 */ \ 2187 &rs6000_reg_names[75][0], /* cr7 */ \ 2188 \ 2189 &rs6000_reg_names[76][0], /* xer */ \ 2190 \ 2191 &rs6000_reg_names[77][0], /* v0 */ \ 2192 &rs6000_reg_names[78][0], /* v1 */ \ 2193 &rs6000_reg_names[79][0], /* v2 */ \ 2194 &rs6000_reg_names[80][0], /* v3 */ \ 2195 &rs6000_reg_names[81][0], /* v4 */ \ 2196 &rs6000_reg_names[82][0], /* v5 */ \ 2197 &rs6000_reg_names[83][0], /* v6 */ \ 2198 &rs6000_reg_names[84][0], /* v7 */ \ 2199 &rs6000_reg_names[85][0], /* v8 */ \ 2200 &rs6000_reg_names[86][0], /* v9 */ \ 2201 &rs6000_reg_names[87][0], /* v10 */ \ 2202 &rs6000_reg_names[88][0], /* v11 */ \ 2203 &rs6000_reg_names[89][0], /* v12 */ \ 2204 &rs6000_reg_names[90][0], /* v13 */ \ 2205 &rs6000_reg_names[91][0], /* v14 */ \ 2206 &rs6000_reg_names[92][0], /* v15 */ \ 2207 &rs6000_reg_names[93][0], /* v16 */ \ 2208 &rs6000_reg_names[94][0], /* v17 */ \ 2209 &rs6000_reg_names[95][0], /* v18 */ \ 2210 &rs6000_reg_names[96][0], /* v19 */ \ 2211 &rs6000_reg_names[97][0], /* v20 */ \ 2212 &rs6000_reg_names[98][0], /* v21 */ \ 2213 &rs6000_reg_names[99][0], /* v22 */ \ 2214 &rs6000_reg_names[100][0], /* v23 */ \ 2215 &rs6000_reg_names[101][0], /* v24 */ \ 2216 &rs6000_reg_names[102][0], /* v25 */ \ 2217 &rs6000_reg_names[103][0], /* v26 */ \ 2218 &rs6000_reg_names[104][0], /* v27 */ \ 2219 &rs6000_reg_names[105][0], /* v28 */ \ 2220 &rs6000_reg_names[106][0], /* v29 */ \ 2221 &rs6000_reg_names[107][0], /* v30 */ \ 2222 &rs6000_reg_names[108][0], /* v31 */ \ 2223 &rs6000_reg_names[109][0], /* vrsave */ \ 2224 &rs6000_reg_names[110][0], /* vscr */ \ 2225 &rs6000_reg_names[111][0], /* spe_acc */ \ 2226 &rs6000_reg_names[112][0], /* spefscr */ \ 2227 &rs6000_reg_names[113][0], /* sfp */ \ 2228 } 2229 2230 /* Table of additional register names to use in user input. */ 2231 2232 #define ADDITIONAL_REGISTER_NAMES \ 2233 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2234 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2235 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2236 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2237 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2238 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2239 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2240 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2241 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2242 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2243 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2244 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2245 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2246 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2247 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2248 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2249 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2250 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2251 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2252 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2253 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2254 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2255 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2256 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2257 {"vrsave", 109}, {"vscr", 110}, \ 2258 {"spe_acc", 111}, {"spefscr", 112}, \ 2259 /* no additional names for: mq, lr, ctr, ap */ \ 2260 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2261 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2262 {"cc", 68}, {"sp", 1}, {"toc", 2} } 2263 2264 /* Text to write out after a CALL that may be replaced by glue code by 2265 the loader. This depends on the AIX version. */ 2266 #define RS6000_CALL_GLUE "cror 31,31,31" 2267 2268 /* This is how to output an element of a case-vector that is relative. */ 2269 2270 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2271 do { char buf[100]; \ 2272 fputs ("\t.long ", FILE); \ 2273 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2274 assemble_name (FILE, buf); \ 2275 putc ('-', FILE); \ 2276 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2277 assemble_name (FILE, buf); \ 2278 putc ('\n', FILE); \ 2279 } while (0) 2280 2281 /* This is how to output an assembler line 2282 that says to advance the location counter 2283 to a multiple of 2**LOG bytes. */ 2284 2285 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2286 if ((LOG) != 0) \ 2287 fprintf (FILE, "\t.align %d\n", (LOG)) 2288 2289 /* Pick up the return address upon entry to a procedure. Used for 2290 dwarf2 unwind information. This also enables the table driven 2291 mechanism. */ 2292 2293 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 2294 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) 2295 2296 /* Describe how we implement __builtin_eh_return. */ 2297 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2298 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2299 2300 /* Print operand X (an rtx) in assembler syntax to file FILE. 2301 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2302 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2303 2304 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2305 2306 /* Define which CODE values are valid. */ 2307 2308 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2309 ((CODE) == '.' || (CODE) == '&') 2310 2311 /* Print a memory address as an operand to reference that memory location. */ 2312 2313 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2314 2315 /* uncomment for disabling the corresponding default options */ 2316 /* #define MACHINE_no_sched_interblock */ 2317 /* #define MACHINE_no_sched_speculative */ 2318 /* #define MACHINE_no_sched_speculative_load */ 2319 2320 /* General flags. */ 2321 extern int flag_pic; 2322 extern int optimize; 2323 extern int flag_expensive_optimizations; 2324 extern int frame_pointer_needed; 2325 2326 enum rs6000_builtins 2327 { 2328 /* AltiVec builtins. */ 2329 ALTIVEC_BUILTIN_ST_INTERNAL_4si, 2330 ALTIVEC_BUILTIN_LD_INTERNAL_4si, 2331 ALTIVEC_BUILTIN_ST_INTERNAL_8hi, 2332 ALTIVEC_BUILTIN_LD_INTERNAL_8hi, 2333 ALTIVEC_BUILTIN_ST_INTERNAL_16qi, 2334 ALTIVEC_BUILTIN_LD_INTERNAL_16qi, 2335 ALTIVEC_BUILTIN_ST_INTERNAL_4sf, 2336 ALTIVEC_BUILTIN_LD_INTERNAL_4sf, 2337 ALTIVEC_BUILTIN_VADDUBM, 2338 ALTIVEC_BUILTIN_VADDUHM, 2339 ALTIVEC_BUILTIN_VADDUWM, 2340 ALTIVEC_BUILTIN_VADDFP, 2341 ALTIVEC_BUILTIN_VADDCUW, 2342 ALTIVEC_BUILTIN_VADDUBS, 2343 ALTIVEC_BUILTIN_VADDSBS, 2344 ALTIVEC_BUILTIN_VADDUHS, 2345 ALTIVEC_BUILTIN_VADDSHS, 2346 ALTIVEC_BUILTIN_VADDUWS, 2347 ALTIVEC_BUILTIN_VADDSWS, 2348 ALTIVEC_BUILTIN_VAND, 2349 ALTIVEC_BUILTIN_VANDC, 2350 ALTIVEC_BUILTIN_VAVGUB, 2351 ALTIVEC_BUILTIN_VAVGSB, 2352 ALTIVEC_BUILTIN_VAVGUH, 2353 ALTIVEC_BUILTIN_VAVGSH, 2354 ALTIVEC_BUILTIN_VAVGUW, 2355 ALTIVEC_BUILTIN_VAVGSW, 2356 ALTIVEC_BUILTIN_VCFUX, 2357 ALTIVEC_BUILTIN_VCFSX, 2358 ALTIVEC_BUILTIN_VCTSXS, 2359 ALTIVEC_BUILTIN_VCTUXS, 2360 ALTIVEC_BUILTIN_VCMPBFP, 2361 ALTIVEC_BUILTIN_VCMPEQUB, 2362 ALTIVEC_BUILTIN_VCMPEQUH, 2363 ALTIVEC_BUILTIN_VCMPEQUW, 2364 ALTIVEC_BUILTIN_VCMPEQFP, 2365 ALTIVEC_BUILTIN_VCMPGEFP, 2366 ALTIVEC_BUILTIN_VCMPGTUB, 2367 ALTIVEC_BUILTIN_VCMPGTSB, 2368 ALTIVEC_BUILTIN_VCMPGTUH, 2369 ALTIVEC_BUILTIN_VCMPGTSH, 2370 ALTIVEC_BUILTIN_VCMPGTUW, 2371 ALTIVEC_BUILTIN_VCMPGTSW, 2372 ALTIVEC_BUILTIN_VCMPGTFP, 2373 ALTIVEC_BUILTIN_VEXPTEFP, 2374 ALTIVEC_BUILTIN_VLOGEFP, 2375 ALTIVEC_BUILTIN_VMADDFP, 2376 ALTIVEC_BUILTIN_VMAXUB, 2377 ALTIVEC_BUILTIN_VMAXSB, 2378 ALTIVEC_BUILTIN_VMAXUH, 2379 ALTIVEC_BUILTIN_VMAXSH, 2380 ALTIVEC_BUILTIN_VMAXUW, 2381 ALTIVEC_BUILTIN_VMAXSW, 2382 ALTIVEC_BUILTIN_VMAXFP, 2383 ALTIVEC_BUILTIN_VMHADDSHS, 2384 ALTIVEC_BUILTIN_VMHRADDSHS, 2385 ALTIVEC_BUILTIN_VMLADDUHM, 2386 ALTIVEC_BUILTIN_VMRGHB, 2387 ALTIVEC_BUILTIN_VMRGHH, 2388 ALTIVEC_BUILTIN_VMRGHW, 2389 ALTIVEC_BUILTIN_VMRGLB, 2390 ALTIVEC_BUILTIN_VMRGLH, 2391 ALTIVEC_BUILTIN_VMRGLW, 2392 ALTIVEC_BUILTIN_VMSUMUBM, 2393 ALTIVEC_BUILTIN_VMSUMMBM, 2394 ALTIVEC_BUILTIN_VMSUMUHM, 2395 ALTIVEC_BUILTIN_VMSUMSHM, 2396 ALTIVEC_BUILTIN_VMSUMUHS, 2397 ALTIVEC_BUILTIN_VMSUMSHS, 2398 ALTIVEC_BUILTIN_VMINUB, 2399 ALTIVEC_BUILTIN_VMINSB, 2400 ALTIVEC_BUILTIN_VMINUH, 2401 ALTIVEC_BUILTIN_VMINSH, 2402 ALTIVEC_BUILTIN_VMINUW, 2403 ALTIVEC_BUILTIN_VMINSW, 2404 ALTIVEC_BUILTIN_VMINFP, 2405 ALTIVEC_BUILTIN_VMULEUB, 2406 ALTIVEC_BUILTIN_VMULESB, 2407 ALTIVEC_BUILTIN_VMULEUH, 2408 ALTIVEC_BUILTIN_VMULESH, 2409 ALTIVEC_BUILTIN_VMULOUB, 2410 ALTIVEC_BUILTIN_VMULOSB, 2411 ALTIVEC_BUILTIN_VMULOUH, 2412 ALTIVEC_BUILTIN_VMULOSH, 2413 ALTIVEC_BUILTIN_VNMSUBFP, 2414 ALTIVEC_BUILTIN_VNOR, 2415 ALTIVEC_BUILTIN_VOR, 2416 ALTIVEC_BUILTIN_VSEL_4SI, 2417 ALTIVEC_BUILTIN_VSEL_4SF, 2418 ALTIVEC_BUILTIN_VSEL_8HI, 2419 ALTIVEC_BUILTIN_VSEL_16QI, 2420 ALTIVEC_BUILTIN_VPERM_4SI, 2421 ALTIVEC_BUILTIN_VPERM_4SF, 2422 ALTIVEC_BUILTIN_VPERM_8HI, 2423 ALTIVEC_BUILTIN_VPERM_16QI, 2424 ALTIVEC_BUILTIN_VPKUHUM, 2425 ALTIVEC_BUILTIN_VPKUWUM, 2426 ALTIVEC_BUILTIN_VPKPX, 2427 ALTIVEC_BUILTIN_VPKUHSS, 2428 ALTIVEC_BUILTIN_VPKSHSS, 2429 ALTIVEC_BUILTIN_VPKUWSS, 2430 ALTIVEC_BUILTIN_VPKSWSS, 2431 ALTIVEC_BUILTIN_VPKUHUS, 2432 ALTIVEC_BUILTIN_VPKSHUS, 2433 ALTIVEC_BUILTIN_VPKUWUS, 2434 ALTIVEC_BUILTIN_VPKSWUS, 2435 ALTIVEC_BUILTIN_VREFP, 2436 ALTIVEC_BUILTIN_VRFIM, 2437 ALTIVEC_BUILTIN_VRFIN, 2438 ALTIVEC_BUILTIN_VRFIP, 2439 ALTIVEC_BUILTIN_VRFIZ, 2440 ALTIVEC_BUILTIN_VRLB, 2441 ALTIVEC_BUILTIN_VRLH, 2442 ALTIVEC_BUILTIN_VRLW, 2443 ALTIVEC_BUILTIN_VRSQRTEFP, 2444 ALTIVEC_BUILTIN_VSLB, 2445 ALTIVEC_BUILTIN_VSLH, 2446 ALTIVEC_BUILTIN_VSLW, 2447 ALTIVEC_BUILTIN_VSL, 2448 ALTIVEC_BUILTIN_VSLO, 2449 ALTIVEC_BUILTIN_VSPLTB, 2450 ALTIVEC_BUILTIN_VSPLTH, 2451 ALTIVEC_BUILTIN_VSPLTW, 2452 ALTIVEC_BUILTIN_VSPLTISB, 2453 ALTIVEC_BUILTIN_VSPLTISH, 2454 ALTIVEC_BUILTIN_VSPLTISW, 2455 ALTIVEC_BUILTIN_VSRB, 2456 ALTIVEC_BUILTIN_VSRH, 2457 ALTIVEC_BUILTIN_VSRW, 2458 ALTIVEC_BUILTIN_VSRAB, 2459 ALTIVEC_BUILTIN_VSRAH, 2460 ALTIVEC_BUILTIN_VSRAW, 2461 ALTIVEC_BUILTIN_VSR, 2462 ALTIVEC_BUILTIN_VSRO, 2463 ALTIVEC_BUILTIN_VSUBUBM, 2464 ALTIVEC_BUILTIN_VSUBUHM, 2465 ALTIVEC_BUILTIN_VSUBUWM, 2466 ALTIVEC_BUILTIN_VSUBFP, 2467 ALTIVEC_BUILTIN_VSUBCUW, 2468 ALTIVEC_BUILTIN_VSUBUBS, 2469 ALTIVEC_BUILTIN_VSUBSBS, 2470 ALTIVEC_BUILTIN_VSUBUHS, 2471 ALTIVEC_BUILTIN_VSUBSHS, 2472 ALTIVEC_BUILTIN_VSUBUWS, 2473 ALTIVEC_BUILTIN_VSUBSWS, 2474 ALTIVEC_BUILTIN_VSUM4UBS, 2475 ALTIVEC_BUILTIN_VSUM4SBS, 2476 ALTIVEC_BUILTIN_VSUM4SHS, 2477 ALTIVEC_BUILTIN_VSUM2SWS, 2478 ALTIVEC_BUILTIN_VSUMSWS, 2479 ALTIVEC_BUILTIN_VXOR, 2480 ALTIVEC_BUILTIN_VSLDOI_16QI, 2481 ALTIVEC_BUILTIN_VSLDOI_8HI, 2482 ALTIVEC_BUILTIN_VSLDOI_4SI, 2483 ALTIVEC_BUILTIN_VSLDOI_4SF, 2484 ALTIVEC_BUILTIN_VUPKHSB, 2485 ALTIVEC_BUILTIN_VUPKHPX, 2486 ALTIVEC_BUILTIN_VUPKHSH, 2487 ALTIVEC_BUILTIN_VUPKLSB, 2488 ALTIVEC_BUILTIN_VUPKLPX, 2489 ALTIVEC_BUILTIN_VUPKLSH, 2490 ALTIVEC_BUILTIN_MTVSCR, 2491 ALTIVEC_BUILTIN_MFVSCR, 2492 ALTIVEC_BUILTIN_DSSALL, 2493 ALTIVEC_BUILTIN_DSS, 2494 ALTIVEC_BUILTIN_LVSL, 2495 ALTIVEC_BUILTIN_LVSR, 2496 ALTIVEC_BUILTIN_DSTT, 2497 ALTIVEC_BUILTIN_DSTST, 2498 ALTIVEC_BUILTIN_DSTSTT, 2499 ALTIVEC_BUILTIN_DST, 2500 ALTIVEC_BUILTIN_LVEBX, 2501 ALTIVEC_BUILTIN_LVEHX, 2502 ALTIVEC_BUILTIN_LVEWX, 2503 ALTIVEC_BUILTIN_LVXL, 2504 ALTIVEC_BUILTIN_LVX, 2505 ALTIVEC_BUILTIN_STVX, 2506 ALTIVEC_BUILTIN_STVEBX, 2507 ALTIVEC_BUILTIN_STVEHX, 2508 ALTIVEC_BUILTIN_STVEWX, 2509 ALTIVEC_BUILTIN_STVXL, 2510 ALTIVEC_BUILTIN_VCMPBFP_P, 2511 ALTIVEC_BUILTIN_VCMPEQFP_P, 2512 ALTIVEC_BUILTIN_VCMPEQUB_P, 2513 ALTIVEC_BUILTIN_VCMPEQUH_P, 2514 ALTIVEC_BUILTIN_VCMPEQUW_P, 2515 ALTIVEC_BUILTIN_VCMPGEFP_P, 2516 ALTIVEC_BUILTIN_VCMPGTFP_P, 2517 ALTIVEC_BUILTIN_VCMPGTSB_P, 2518 ALTIVEC_BUILTIN_VCMPGTSH_P, 2519 ALTIVEC_BUILTIN_VCMPGTSW_P, 2520 ALTIVEC_BUILTIN_VCMPGTUB_P, 2521 ALTIVEC_BUILTIN_VCMPGTUH_P, 2522 ALTIVEC_BUILTIN_VCMPGTUW_P, 2523 ALTIVEC_BUILTIN_ABSS_V4SI, 2524 ALTIVEC_BUILTIN_ABSS_V8HI, 2525 ALTIVEC_BUILTIN_ABSS_V16QI, 2526 ALTIVEC_BUILTIN_ABS_V4SI, 2527 ALTIVEC_BUILTIN_ABS_V4SF, 2528 ALTIVEC_BUILTIN_ABS_V8HI, 2529 ALTIVEC_BUILTIN_ABS_V16QI, 2530 ALTIVEC_BUILTIN_MASK_FOR_LOAD, 2531 ALTIVEC_BUILTIN_MASK_FOR_STORE, 2532 ALTIVEC_BUILTIN_VEC_INIT_V4SI, 2533 ALTIVEC_BUILTIN_VEC_INIT_V8HI, 2534 ALTIVEC_BUILTIN_VEC_INIT_V16QI, 2535 ALTIVEC_BUILTIN_VEC_INIT_V4SF, 2536 ALTIVEC_BUILTIN_VEC_SET_V4SI, 2537 ALTIVEC_BUILTIN_VEC_SET_V8HI, 2538 ALTIVEC_BUILTIN_VEC_SET_V16QI, 2539 ALTIVEC_BUILTIN_VEC_SET_V4SF, 2540 ALTIVEC_BUILTIN_VEC_EXT_V4SI, 2541 ALTIVEC_BUILTIN_VEC_EXT_V8HI, 2542 ALTIVEC_BUILTIN_VEC_EXT_V16QI, 2543 ALTIVEC_BUILTIN_VEC_EXT_V4SF, 2544 2545 /* Altivec overloaded builtins. */ 2546 ALTIVEC_BUILTIN_VCMPEQ_P, 2547 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P, 2548 ALTIVEC_BUILTIN_VCMPGT_P, 2549 ALTIVEC_BUILTIN_VCMPGE_P, 2550 ALTIVEC_BUILTIN_VEC_ABS, 2551 ALTIVEC_BUILTIN_VEC_ABSS, 2552 ALTIVEC_BUILTIN_VEC_ADD, 2553 ALTIVEC_BUILTIN_VEC_ADDC, 2554 ALTIVEC_BUILTIN_VEC_ADDS, 2555 ALTIVEC_BUILTIN_VEC_AND, 2556 ALTIVEC_BUILTIN_VEC_ANDC, 2557 ALTIVEC_BUILTIN_VEC_AVG, 2558 ALTIVEC_BUILTIN_VEC_CEIL, 2559 ALTIVEC_BUILTIN_VEC_CMPB, 2560 ALTIVEC_BUILTIN_VEC_CMPEQ, 2561 ALTIVEC_BUILTIN_VEC_CMPEQUB, 2562 ALTIVEC_BUILTIN_VEC_CMPEQUH, 2563 ALTIVEC_BUILTIN_VEC_CMPEQUW, 2564 ALTIVEC_BUILTIN_VEC_CMPGE, 2565 ALTIVEC_BUILTIN_VEC_CMPGT, 2566 ALTIVEC_BUILTIN_VEC_CMPLE, 2567 ALTIVEC_BUILTIN_VEC_CMPLT, 2568 ALTIVEC_BUILTIN_VEC_CTF, 2569 ALTIVEC_BUILTIN_VEC_CTS, 2570 ALTIVEC_BUILTIN_VEC_CTU, 2571 ALTIVEC_BUILTIN_VEC_DST, 2572 ALTIVEC_BUILTIN_VEC_DSTST, 2573 ALTIVEC_BUILTIN_VEC_DSTSTT, 2574 ALTIVEC_BUILTIN_VEC_DSTT, 2575 ALTIVEC_BUILTIN_VEC_EXPTE, 2576 ALTIVEC_BUILTIN_VEC_FLOOR, 2577 ALTIVEC_BUILTIN_VEC_LD, 2578 ALTIVEC_BUILTIN_VEC_LDE, 2579 ALTIVEC_BUILTIN_VEC_LDL, 2580 ALTIVEC_BUILTIN_VEC_LOGE, 2581 ALTIVEC_BUILTIN_VEC_LVEBX, 2582 ALTIVEC_BUILTIN_VEC_LVEHX, 2583 ALTIVEC_BUILTIN_VEC_LVEWX, 2584 ALTIVEC_BUILTIN_VEC_LVSL, 2585 ALTIVEC_BUILTIN_VEC_LVSR, 2586 ALTIVEC_BUILTIN_VEC_MADD, 2587 ALTIVEC_BUILTIN_VEC_MADDS, 2588 ALTIVEC_BUILTIN_VEC_MAX, 2589 ALTIVEC_BUILTIN_VEC_MERGEH, 2590 ALTIVEC_BUILTIN_VEC_MERGEL, 2591 ALTIVEC_BUILTIN_VEC_MIN, 2592 ALTIVEC_BUILTIN_VEC_MLADD, 2593 ALTIVEC_BUILTIN_VEC_MPERM, 2594 ALTIVEC_BUILTIN_VEC_MRADDS, 2595 ALTIVEC_BUILTIN_VEC_MRGHB, 2596 ALTIVEC_BUILTIN_VEC_MRGHH, 2597 ALTIVEC_BUILTIN_VEC_MRGHW, 2598 ALTIVEC_BUILTIN_VEC_MRGLB, 2599 ALTIVEC_BUILTIN_VEC_MRGLH, 2600 ALTIVEC_BUILTIN_VEC_MRGLW, 2601 ALTIVEC_BUILTIN_VEC_MSUM, 2602 ALTIVEC_BUILTIN_VEC_MSUMS, 2603 ALTIVEC_BUILTIN_VEC_MTVSCR, 2604 ALTIVEC_BUILTIN_VEC_MULE, 2605 ALTIVEC_BUILTIN_VEC_MULO, 2606 ALTIVEC_BUILTIN_VEC_NMSUB, 2607 ALTIVEC_BUILTIN_VEC_NOR, 2608 ALTIVEC_BUILTIN_VEC_OR, 2609 ALTIVEC_BUILTIN_VEC_PACK, 2610 ALTIVEC_BUILTIN_VEC_PACKPX, 2611 ALTIVEC_BUILTIN_VEC_PACKS, 2612 ALTIVEC_BUILTIN_VEC_PACKSU, 2613 ALTIVEC_BUILTIN_VEC_PERM, 2614 ALTIVEC_BUILTIN_VEC_RE, 2615 ALTIVEC_BUILTIN_VEC_RL, 2616 ALTIVEC_BUILTIN_VEC_ROUND, 2617 ALTIVEC_BUILTIN_VEC_RSQRTE, 2618 ALTIVEC_BUILTIN_VEC_SEL, 2619 ALTIVEC_BUILTIN_VEC_SL, 2620 ALTIVEC_BUILTIN_VEC_SLD, 2621 ALTIVEC_BUILTIN_VEC_SLL, 2622 ALTIVEC_BUILTIN_VEC_SLO, 2623 ALTIVEC_BUILTIN_VEC_SPLAT, 2624 ALTIVEC_BUILTIN_VEC_SPLAT_S16, 2625 ALTIVEC_BUILTIN_VEC_SPLAT_S32, 2626 ALTIVEC_BUILTIN_VEC_SPLAT_S8, 2627 ALTIVEC_BUILTIN_VEC_SPLAT_U16, 2628 ALTIVEC_BUILTIN_VEC_SPLAT_U32, 2629 ALTIVEC_BUILTIN_VEC_SPLAT_U8, 2630 ALTIVEC_BUILTIN_VEC_SPLTB, 2631 ALTIVEC_BUILTIN_VEC_SPLTH, 2632 ALTIVEC_BUILTIN_VEC_SPLTW, 2633 ALTIVEC_BUILTIN_VEC_SR, 2634 ALTIVEC_BUILTIN_VEC_SRA, 2635 ALTIVEC_BUILTIN_VEC_SRL, 2636 ALTIVEC_BUILTIN_VEC_SRO, 2637 ALTIVEC_BUILTIN_VEC_ST, 2638 ALTIVEC_BUILTIN_VEC_STE, 2639 ALTIVEC_BUILTIN_VEC_STL, 2640 ALTIVEC_BUILTIN_VEC_STVEBX, 2641 ALTIVEC_BUILTIN_VEC_STVEHX, 2642 ALTIVEC_BUILTIN_VEC_STVEWX, 2643 ALTIVEC_BUILTIN_VEC_SUB, 2644 ALTIVEC_BUILTIN_VEC_SUBC, 2645 ALTIVEC_BUILTIN_VEC_SUBS, 2646 ALTIVEC_BUILTIN_VEC_SUM2S, 2647 ALTIVEC_BUILTIN_VEC_SUM4S, 2648 ALTIVEC_BUILTIN_VEC_SUMS, 2649 ALTIVEC_BUILTIN_VEC_TRUNC, 2650 ALTIVEC_BUILTIN_VEC_UNPACKH, 2651 ALTIVEC_BUILTIN_VEC_UNPACKL, 2652 ALTIVEC_BUILTIN_VEC_VADDFP, 2653 ALTIVEC_BUILTIN_VEC_VADDSBS, 2654 ALTIVEC_BUILTIN_VEC_VADDSHS, 2655 ALTIVEC_BUILTIN_VEC_VADDSWS, 2656 ALTIVEC_BUILTIN_VEC_VADDUBM, 2657 ALTIVEC_BUILTIN_VEC_VADDUBS, 2658 ALTIVEC_BUILTIN_VEC_VADDUHM, 2659 ALTIVEC_BUILTIN_VEC_VADDUHS, 2660 ALTIVEC_BUILTIN_VEC_VADDUWM, 2661 ALTIVEC_BUILTIN_VEC_VADDUWS, 2662 ALTIVEC_BUILTIN_VEC_VAVGSB, 2663 ALTIVEC_BUILTIN_VEC_VAVGSH, 2664 ALTIVEC_BUILTIN_VEC_VAVGSW, 2665 ALTIVEC_BUILTIN_VEC_VAVGUB, 2666 ALTIVEC_BUILTIN_VEC_VAVGUH, 2667 ALTIVEC_BUILTIN_VEC_VAVGUW, 2668 ALTIVEC_BUILTIN_VEC_VCFSX, 2669 ALTIVEC_BUILTIN_VEC_VCFUX, 2670 ALTIVEC_BUILTIN_VEC_VCMPEQFP, 2671 ALTIVEC_BUILTIN_VEC_VCMPEQUB, 2672 ALTIVEC_BUILTIN_VEC_VCMPEQUH, 2673 ALTIVEC_BUILTIN_VEC_VCMPEQUW, 2674 ALTIVEC_BUILTIN_VEC_VCMPGTFP, 2675 ALTIVEC_BUILTIN_VEC_VCMPGTSB, 2676 ALTIVEC_BUILTIN_VEC_VCMPGTSH, 2677 ALTIVEC_BUILTIN_VEC_VCMPGTSW, 2678 ALTIVEC_BUILTIN_VEC_VCMPGTUB, 2679 ALTIVEC_BUILTIN_VEC_VCMPGTUH, 2680 ALTIVEC_BUILTIN_VEC_VCMPGTUW, 2681 ALTIVEC_BUILTIN_VEC_VMAXFP, 2682 ALTIVEC_BUILTIN_VEC_VMAXSB, 2683 ALTIVEC_BUILTIN_VEC_VMAXSH, 2684 ALTIVEC_BUILTIN_VEC_VMAXSW, 2685 ALTIVEC_BUILTIN_VEC_VMAXUB, 2686 ALTIVEC_BUILTIN_VEC_VMAXUH, 2687 ALTIVEC_BUILTIN_VEC_VMAXUW, 2688 ALTIVEC_BUILTIN_VEC_VMINFP, 2689 ALTIVEC_BUILTIN_VEC_VMINSB, 2690 ALTIVEC_BUILTIN_VEC_VMINSH, 2691 ALTIVEC_BUILTIN_VEC_VMINSW, 2692 ALTIVEC_BUILTIN_VEC_VMINUB, 2693 ALTIVEC_BUILTIN_VEC_VMINUH, 2694 ALTIVEC_BUILTIN_VEC_VMINUW, 2695 ALTIVEC_BUILTIN_VEC_VMRGHB, 2696 ALTIVEC_BUILTIN_VEC_VMRGHH, 2697 ALTIVEC_BUILTIN_VEC_VMRGHW, 2698 ALTIVEC_BUILTIN_VEC_VMRGLB, 2699 ALTIVEC_BUILTIN_VEC_VMRGLH, 2700 ALTIVEC_BUILTIN_VEC_VMRGLW, 2701 ALTIVEC_BUILTIN_VEC_VMSUMMBM, 2702 ALTIVEC_BUILTIN_VEC_VMSUMSHM, 2703 ALTIVEC_BUILTIN_VEC_VMSUMSHS, 2704 ALTIVEC_BUILTIN_VEC_VMSUMUBM, 2705 ALTIVEC_BUILTIN_VEC_VMSUMUHM, 2706 ALTIVEC_BUILTIN_VEC_VMSUMUHS, 2707 ALTIVEC_BUILTIN_VEC_VMULESB, 2708 ALTIVEC_BUILTIN_VEC_VMULESH, 2709 ALTIVEC_BUILTIN_VEC_VMULEUB, 2710 ALTIVEC_BUILTIN_VEC_VMULEUH, 2711 ALTIVEC_BUILTIN_VEC_VMULOSB, 2712 ALTIVEC_BUILTIN_VEC_VMULOSH, 2713 ALTIVEC_BUILTIN_VEC_VMULOUB, 2714 ALTIVEC_BUILTIN_VEC_VMULOUH, 2715 ALTIVEC_BUILTIN_VEC_VPKSHSS, 2716 ALTIVEC_BUILTIN_VEC_VPKSHUS, 2717 ALTIVEC_BUILTIN_VEC_VPKSWSS, 2718 ALTIVEC_BUILTIN_VEC_VPKSWUS, 2719 ALTIVEC_BUILTIN_VEC_VPKUHUM, 2720 ALTIVEC_BUILTIN_VEC_VPKUHUS, 2721 ALTIVEC_BUILTIN_VEC_VPKUWUM, 2722 ALTIVEC_BUILTIN_VEC_VPKUWUS, 2723 ALTIVEC_BUILTIN_VEC_VRLB, 2724 ALTIVEC_BUILTIN_VEC_VRLH, 2725 ALTIVEC_BUILTIN_VEC_VRLW, 2726 ALTIVEC_BUILTIN_VEC_VSLB, 2727 ALTIVEC_BUILTIN_VEC_VSLH, 2728 ALTIVEC_BUILTIN_VEC_VSLW, 2729 ALTIVEC_BUILTIN_VEC_VSPLTB, 2730 ALTIVEC_BUILTIN_VEC_VSPLTH, 2731 ALTIVEC_BUILTIN_VEC_VSPLTW, 2732 ALTIVEC_BUILTIN_VEC_VSRAB, 2733 ALTIVEC_BUILTIN_VEC_VSRAH, 2734 ALTIVEC_BUILTIN_VEC_VSRAW, 2735 ALTIVEC_BUILTIN_VEC_VSRB, 2736 ALTIVEC_BUILTIN_VEC_VSRH, 2737 ALTIVEC_BUILTIN_VEC_VSRW, 2738 ALTIVEC_BUILTIN_VEC_VSUBFP, 2739 ALTIVEC_BUILTIN_VEC_VSUBSBS, 2740 ALTIVEC_BUILTIN_VEC_VSUBSHS, 2741 ALTIVEC_BUILTIN_VEC_VSUBSWS, 2742 ALTIVEC_BUILTIN_VEC_VSUBUBM, 2743 ALTIVEC_BUILTIN_VEC_VSUBUBS, 2744 ALTIVEC_BUILTIN_VEC_VSUBUHM, 2745 ALTIVEC_BUILTIN_VEC_VSUBUHS, 2746 ALTIVEC_BUILTIN_VEC_VSUBUWM, 2747 ALTIVEC_BUILTIN_VEC_VSUBUWS, 2748 ALTIVEC_BUILTIN_VEC_VSUM4SBS, 2749 ALTIVEC_BUILTIN_VEC_VSUM4SHS, 2750 ALTIVEC_BUILTIN_VEC_VSUM4UBS, 2751 ALTIVEC_BUILTIN_VEC_VUPKHPX, 2752 ALTIVEC_BUILTIN_VEC_VUPKHSB, 2753 ALTIVEC_BUILTIN_VEC_VUPKHSH, 2754 ALTIVEC_BUILTIN_VEC_VUPKLPX, 2755 ALTIVEC_BUILTIN_VEC_VUPKLSB, 2756 ALTIVEC_BUILTIN_VEC_VUPKLSH, 2757 ALTIVEC_BUILTIN_VEC_XOR, 2758 ALTIVEC_BUILTIN_VEC_STEP, 2759 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP, 2760 2761 /* SPE builtins. */ 2762 SPE_BUILTIN_EVADDW, 2763 SPE_BUILTIN_EVAND, 2764 SPE_BUILTIN_EVANDC, 2765 SPE_BUILTIN_EVDIVWS, 2766 SPE_BUILTIN_EVDIVWU, 2767 SPE_BUILTIN_EVEQV, 2768 SPE_BUILTIN_EVFSADD, 2769 SPE_BUILTIN_EVFSDIV, 2770 SPE_BUILTIN_EVFSMUL, 2771 SPE_BUILTIN_EVFSSUB, 2772 SPE_BUILTIN_EVLDDX, 2773 SPE_BUILTIN_EVLDHX, 2774 SPE_BUILTIN_EVLDWX, 2775 SPE_BUILTIN_EVLHHESPLATX, 2776 SPE_BUILTIN_EVLHHOSSPLATX, 2777 SPE_BUILTIN_EVLHHOUSPLATX, 2778 SPE_BUILTIN_EVLWHEX, 2779 SPE_BUILTIN_EVLWHOSX, 2780 SPE_BUILTIN_EVLWHOUX, 2781 SPE_BUILTIN_EVLWHSPLATX, 2782 SPE_BUILTIN_EVLWWSPLATX, 2783 SPE_BUILTIN_EVMERGEHI, 2784 SPE_BUILTIN_EVMERGEHILO, 2785 SPE_BUILTIN_EVMERGELO, 2786 SPE_BUILTIN_EVMERGELOHI, 2787 SPE_BUILTIN_EVMHEGSMFAA, 2788 SPE_BUILTIN_EVMHEGSMFAN, 2789 SPE_BUILTIN_EVMHEGSMIAA, 2790 SPE_BUILTIN_EVMHEGSMIAN, 2791 SPE_BUILTIN_EVMHEGUMIAA, 2792 SPE_BUILTIN_EVMHEGUMIAN, 2793 SPE_BUILTIN_EVMHESMF, 2794 SPE_BUILTIN_EVMHESMFA, 2795 SPE_BUILTIN_EVMHESMFAAW, 2796 SPE_BUILTIN_EVMHESMFANW, 2797 SPE_BUILTIN_EVMHESMI, 2798 SPE_BUILTIN_EVMHESMIA, 2799 SPE_BUILTIN_EVMHESMIAAW, 2800 SPE_BUILTIN_EVMHESMIANW, 2801 SPE_BUILTIN_EVMHESSF, 2802 SPE_BUILTIN_EVMHESSFA, 2803 SPE_BUILTIN_EVMHESSFAAW, 2804 SPE_BUILTIN_EVMHESSFANW, 2805 SPE_BUILTIN_EVMHESSIAAW, 2806 SPE_BUILTIN_EVMHESSIANW, 2807 SPE_BUILTIN_EVMHEUMI, 2808 SPE_BUILTIN_EVMHEUMIA, 2809 SPE_BUILTIN_EVMHEUMIAAW, 2810 SPE_BUILTIN_EVMHEUMIANW, 2811 SPE_BUILTIN_EVMHEUSIAAW, 2812 SPE_BUILTIN_EVMHEUSIANW, 2813 SPE_BUILTIN_EVMHOGSMFAA, 2814 SPE_BUILTIN_EVMHOGSMFAN, 2815 SPE_BUILTIN_EVMHOGSMIAA, 2816 SPE_BUILTIN_EVMHOGSMIAN, 2817 SPE_BUILTIN_EVMHOGUMIAA, 2818 SPE_BUILTIN_EVMHOGUMIAN, 2819 SPE_BUILTIN_EVMHOSMF, 2820 SPE_BUILTIN_EVMHOSMFA, 2821 SPE_BUILTIN_EVMHOSMFAAW, 2822 SPE_BUILTIN_EVMHOSMFANW, 2823 SPE_BUILTIN_EVMHOSMI, 2824 SPE_BUILTIN_EVMHOSMIA, 2825 SPE_BUILTIN_EVMHOSMIAAW, 2826 SPE_BUILTIN_EVMHOSMIANW, 2827 SPE_BUILTIN_EVMHOSSF, 2828 SPE_BUILTIN_EVMHOSSFA, 2829 SPE_BUILTIN_EVMHOSSFAAW, 2830 SPE_BUILTIN_EVMHOSSFANW, 2831 SPE_BUILTIN_EVMHOSSIAAW, 2832 SPE_BUILTIN_EVMHOSSIANW, 2833 SPE_BUILTIN_EVMHOUMI, 2834 SPE_BUILTIN_EVMHOUMIA, 2835 SPE_BUILTIN_EVMHOUMIAAW, 2836 SPE_BUILTIN_EVMHOUMIANW, 2837 SPE_BUILTIN_EVMHOUSIAAW, 2838 SPE_BUILTIN_EVMHOUSIANW, 2839 SPE_BUILTIN_EVMWHSMF, 2840 SPE_BUILTIN_EVMWHSMFA, 2841 SPE_BUILTIN_EVMWHSMI, 2842 SPE_BUILTIN_EVMWHSMIA, 2843 SPE_BUILTIN_EVMWHSSF, 2844 SPE_BUILTIN_EVMWHSSFA, 2845 SPE_BUILTIN_EVMWHUMI, 2846 SPE_BUILTIN_EVMWHUMIA, 2847 SPE_BUILTIN_EVMWLSMIAAW, 2848 SPE_BUILTIN_EVMWLSMIANW, 2849 SPE_BUILTIN_EVMWLSSIAAW, 2850 SPE_BUILTIN_EVMWLSSIANW, 2851 SPE_BUILTIN_EVMWLUMI, 2852 SPE_BUILTIN_EVMWLUMIA, 2853 SPE_BUILTIN_EVMWLUMIAAW, 2854 SPE_BUILTIN_EVMWLUMIANW, 2855 SPE_BUILTIN_EVMWLUSIAAW, 2856 SPE_BUILTIN_EVMWLUSIANW, 2857 SPE_BUILTIN_EVMWSMF, 2858 SPE_BUILTIN_EVMWSMFA, 2859 SPE_BUILTIN_EVMWSMFAA, 2860 SPE_BUILTIN_EVMWSMFAN, 2861 SPE_BUILTIN_EVMWSMI, 2862 SPE_BUILTIN_EVMWSMIA, 2863 SPE_BUILTIN_EVMWSMIAA, 2864 SPE_BUILTIN_EVMWSMIAN, 2865 SPE_BUILTIN_EVMWHSSFAA, 2866 SPE_BUILTIN_EVMWSSF, 2867 SPE_BUILTIN_EVMWSSFA, 2868 SPE_BUILTIN_EVMWSSFAA, 2869 SPE_BUILTIN_EVMWSSFAN, 2870 SPE_BUILTIN_EVMWUMI, 2871 SPE_BUILTIN_EVMWUMIA, 2872 SPE_BUILTIN_EVMWUMIAA, 2873 SPE_BUILTIN_EVMWUMIAN, 2874 SPE_BUILTIN_EVNAND, 2875 SPE_BUILTIN_EVNOR, 2876 SPE_BUILTIN_EVOR, 2877 SPE_BUILTIN_EVORC, 2878 SPE_BUILTIN_EVRLW, 2879 SPE_BUILTIN_EVSLW, 2880 SPE_BUILTIN_EVSRWS, 2881 SPE_BUILTIN_EVSRWU, 2882 SPE_BUILTIN_EVSTDDX, 2883 SPE_BUILTIN_EVSTDHX, 2884 SPE_BUILTIN_EVSTDWX, 2885 SPE_BUILTIN_EVSTWHEX, 2886 SPE_BUILTIN_EVSTWHOX, 2887 SPE_BUILTIN_EVSTWWEX, 2888 SPE_BUILTIN_EVSTWWOX, 2889 SPE_BUILTIN_EVSUBFW, 2890 SPE_BUILTIN_EVXOR, 2891 SPE_BUILTIN_EVABS, 2892 SPE_BUILTIN_EVADDSMIAAW, 2893 SPE_BUILTIN_EVADDSSIAAW, 2894 SPE_BUILTIN_EVADDUMIAAW, 2895 SPE_BUILTIN_EVADDUSIAAW, 2896 SPE_BUILTIN_EVCNTLSW, 2897 SPE_BUILTIN_EVCNTLZW, 2898 SPE_BUILTIN_EVEXTSB, 2899 SPE_BUILTIN_EVEXTSH, 2900 SPE_BUILTIN_EVFSABS, 2901 SPE_BUILTIN_EVFSCFSF, 2902 SPE_BUILTIN_EVFSCFSI, 2903 SPE_BUILTIN_EVFSCFUF, 2904 SPE_BUILTIN_EVFSCFUI, 2905 SPE_BUILTIN_EVFSCTSF, 2906 SPE_BUILTIN_EVFSCTSI, 2907 SPE_BUILTIN_EVFSCTSIZ, 2908 SPE_BUILTIN_EVFSCTUF, 2909 SPE_BUILTIN_EVFSCTUI, 2910 SPE_BUILTIN_EVFSCTUIZ, 2911 SPE_BUILTIN_EVFSNABS, 2912 SPE_BUILTIN_EVFSNEG, 2913 SPE_BUILTIN_EVMRA, 2914 SPE_BUILTIN_EVNEG, 2915 SPE_BUILTIN_EVRNDW, 2916 SPE_BUILTIN_EVSUBFSMIAAW, 2917 SPE_BUILTIN_EVSUBFSSIAAW, 2918 SPE_BUILTIN_EVSUBFUMIAAW, 2919 SPE_BUILTIN_EVSUBFUSIAAW, 2920 SPE_BUILTIN_EVADDIW, 2921 SPE_BUILTIN_EVLDD, 2922 SPE_BUILTIN_EVLDH, 2923 SPE_BUILTIN_EVLDW, 2924 SPE_BUILTIN_EVLHHESPLAT, 2925 SPE_BUILTIN_EVLHHOSSPLAT, 2926 SPE_BUILTIN_EVLHHOUSPLAT, 2927 SPE_BUILTIN_EVLWHE, 2928 SPE_BUILTIN_EVLWHOS, 2929 SPE_BUILTIN_EVLWHOU, 2930 SPE_BUILTIN_EVLWHSPLAT, 2931 SPE_BUILTIN_EVLWWSPLAT, 2932 SPE_BUILTIN_EVRLWI, 2933 SPE_BUILTIN_EVSLWI, 2934 SPE_BUILTIN_EVSRWIS, 2935 SPE_BUILTIN_EVSRWIU, 2936 SPE_BUILTIN_EVSTDD, 2937 SPE_BUILTIN_EVSTDH, 2938 SPE_BUILTIN_EVSTDW, 2939 SPE_BUILTIN_EVSTWHE, 2940 SPE_BUILTIN_EVSTWHO, 2941 SPE_BUILTIN_EVSTWWE, 2942 SPE_BUILTIN_EVSTWWO, 2943 SPE_BUILTIN_EVSUBIFW, 2944 2945 /* Compares. */ 2946 SPE_BUILTIN_EVCMPEQ, 2947 SPE_BUILTIN_EVCMPGTS, 2948 SPE_BUILTIN_EVCMPGTU, 2949 SPE_BUILTIN_EVCMPLTS, 2950 SPE_BUILTIN_EVCMPLTU, 2951 SPE_BUILTIN_EVFSCMPEQ, 2952 SPE_BUILTIN_EVFSCMPGT, 2953 SPE_BUILTIN_EVFSCMPLT, 2954 SPE_BUILTIN_EVFSTSTEQ, 2955 SPE_BUILTIN_EVFSTSTGT, 2956 SPE_BUILTIN_EVFSTSTLT, 2957 2958 /* EVSEL compares. */ 2959 SPE_BUILTIN_EVSEL_CMPEQ, 2960 SPE_BUILTIN_EVSEL_CMPGTS, 2961 SPE_BUILTIN_EVSEL_CMPGTU, 2962 SPE_BUILTIN_EVSEL_CMPLTS, 2963 SPE_BUILTIN_EVSEL_CMPLTU, 2964 SPE_BUILTIN_EVSEL_FSCMPEQ, 2965 SPE_BUILTIN_EVSEL_FSCMPGT, 2966 SPE_BUILTIN_EVSEL_FSCMPLT, 2967 SPE_BUILTIN_EVSEL_FSTSTEQ, 2968 SPE_BUILTIN_EVSEL_FSTSTGT, 2969 SPE_BUILTIN_EVSEL_FSTSTLT, 2970 2971 SPE_BUILTIN_EVSPLATFI, 2972 SPE_BUILTIN_EVSPLATI, 2973 SPE_BUILTIN_EVMWHSSMAA, 2974 SPE_BUILTIN_EVMWHSMFAA, 2975 SPE_BUILTIN_EVMWHSMIAA, 2976 SPE_BUILTIN_EVMWHUSIAA, 2977 SPE_BUILTIN_EVMWHUMIAA, 2978 SPE_BUILTIN_EVMWHSSFAN, 2979 SPE_BUILTIN_EVMWHSSIAN, 2980 SPE_BUILTIN_EVMWHSMFAN, 2981 SPE_BUILTIN_EVMWHSMIAN, 2982 SPE_BUILTIN_EVMWHUSIAN, 2983 SPE_BUILTIN_EVMWHUMIAN, 2984 SPE_BUILTIN_EVMWHGSSFAA, 2985 SPE_BUILTIN_EVMWHGSMFAA, 2986 SPE_BUILTIN_EVMWHGSMIAA, 2987 SPE_BUILTIN_EVMWHGUMIAA, 2988 SPE_BUILTIN_EVMWHGSSFAN, 2989 SPE_BUILTIN_EVMWHGSMFAN, 2990 SPE_BUILTIN_EVMWHGSMIAN, 2991 SPE_BUILTIN_EVMWHGUMIAN, 2992 SPE_BUILTIN_MTSPEFSCR, 2993 SPE_BUILTIN_MFSPEFSCR, 2994 SPE_BUILTIN_BRINC, 2995 2996 RS6000_BUILTIN_COUNT 2997 }; 2998 2999 enum rs6000_builtin_type_index 3000 { 3001 RS6000_BTI_NOT_OPAQUE, 3002 RS6000_BTI_opaque_V2SI, 3003 RS6000_BTI_opaque_V2SF, 3004 RS6000_BTI_opaque_p_V2SI, 3005 RS6000_BTI_opaque_V4SI, 3006 RS6000_BTI_V16QI, 3007 RS6000_BTI_V2SI, 3008 RS6000_BTI_V2SF, 3009 RS6000_BTI_V4HI, 3010 RS6000_BTI_V4SI, 3011 RS6000_BTI_V4SF, 3012 RS6000_BTI_V8HI, 3013 RS6000_BTI_unsigned_V16QI, 3014 RS6000_BTI_unsigned_V8HI, 3015 RS6000_BTI_unsigned_V4SI, 3016 RS6000_BTI_bool_char, /* __bool char */ 3017 RS6000_BTI_bool_short, /* __bool short */ 3018 RS6000_BTI_bool_int, /* __bool int */ 3019 RS6000_BTI_pixel, /* __pixel */ 3020 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 3021 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 3022 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 3023 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 3024 RS6000_BTI_long, /* long_integer_type_node */ 3025 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 3026 RS6000_BTI_INTQI, /* intQI_type_node */ 3027 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 3028 RS6000_BTI_INTHI, /* intHI_type_node */ 3029 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 3030 RS6000_BTI_INTSI, /* intSI_type_node */ 3031 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 3032 RS6000_BTI_float, /* float_type_node */ 3033 RS6000_BTI_void, /* void_type_node */ 3034 RS6000_BTI_MAX 3035 }; 3036 3037 3038 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 3039 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 3040 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 3041 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 3042 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 3043 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 3044 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 3045 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 3046 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 3047 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 3048 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 3049 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 3050 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 3051 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 3052 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 3053 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 3054 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 3055 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 3056 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 3057 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 3058 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 3059 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 3060 3061 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 3062 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 3063 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 3064 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 3065 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 3066 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 3067 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 3068 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 3069 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 3070 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 3071 3072 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 3073 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 3074 3075