1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
5 */
6
7 #ifndef __KSZ_COMMON_H
8 #define __KSZ_COMMON_H
9
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
15 #include <net/dsa.h>
16 #include <linux/irq.h>
17 #include <linux/platform_data/microchip-ksz.h>
18
19 #include "ksz_ptp.h"
20
21 #define KSZ_MAX_NUM_PORTS 8
22 /* all KSZ switches count ports from 1 */
23 #define KSZ_PORT_1 0
24 #define KSZ_PORT_2 1
25
26 struct ksz_device;
27 struct ksz_port;
28 struct phylink_mac_ops;
29
30 enum ksz_regmap_width {
31 KSZ_REGMAP_8,
32 KSZ_REGMAP_16,
33 KSZ_REGMAP_32,
34 __KSZ_NUM_REGMAPS,
35 };
36
37 struct vlan_table {
38 u32 table[3];
39 };
40
41 struct ksz_port_mib {
42 struct mutex cnt_mutex; /* structure access */
43 u8 cnt_ptr;
44 u64 *counters;
45 struct rtnl_link_stats64 stats64;
46 struct ethtool_pause_stats pause_stats;
47 struct spinlock stats64_lock;
48 };
49
50 struct ksz_mib_names {
51 int index;
52 char string[ETH_GSTRING_LEN];
53 };
54
55 struct ksz_chip_data {
56 u32 chip_id;
57 const char *dev_name;
58 int num_vlans;
59 int num_alus;
60 int num_statics;
61 int cpu_ports;
62 int port_cnt;
63 u8 port_nirqs;
64 u8 num_tx_queues;
65 u8 num_ipms; /* number of Internal Priority Maps */
66 bool tc_cbs_supported;
67 const struct ksz_dev_ops *ops;
68 const struct phylink_mac_ops *phylink_mac_ops;
69 bool ksz87xx_eee_link_erratum;
70 const struct ksz_mib_names *mib_names;
71 int mib_cnt;
72 u8 reg_mib_cnt;
73 const u16 *regs;
74 const u32 *masks;
75 const u8 *shifts;
76 const u8 *xmii_ctrl0;
77 const u8 *xmii_ctrl1;
78 int stp_ctrl_reg;
79 int broadcast_ctrl_reg;
80 int multicast_ctrl_reg;
81 int start_ctrl_reg;
82 bool supports_mii[KSZ_MAX_NUM_PORTS];
83 bool supports_rmii[KSZ_MAX_NUM_PORTS];
84 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
85 bool internal_phy[KSZ_MAX_NUM_PORTS];
86 bool gbit_capable[KSZ_MAX_NUM_PORTS];
87 const struct regmap_access_table *wr_table;
88 const struct regmap_access_table *rd_table;
89 };
90
91 struct ksz_irq {
92 u16 masked;
93 u16 reg_mask;
94 u16 reg_status;
95 struct irq_domain *domain;
96 int nirqs;
97 int irq_num;
98 char name[16];
99 struct ksz_device *dev;
100 };
101
102 struct ksz_ptp_irq {
103 struct ksz_port *port;
104 u16 ts_reg;
105 bool ts_en;
106 char name[16];
107 int num;
108 };
109
110 struct ksz_switch_macaddr {
111 unsigned char addr[ETH_ALEN];
112 refcount_t refcount;
113 };
114
115 struct ksz_port {
116 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
117 bool learning;
118 bool isolated;
119 int stp_state;
120 struct phy_device phydev;
121
122 u32 fiber:1; /* port is fiber */
123 u32 force:1;
124 u32 read:1; /* read MIB counters in background */
125 u32 freeze:1; /* MIB counter freeze is enabled */
126
127 struct ksz_port_mib mib;
128 phy_interface_t interface;
129 u32 rgmii_tx_val;
130 u32 rgmii_rx_val;
131 struct ksz_device *ksz_dev;
132 void *acl_priv;
133 struct ksz_irq pirq;
134 u8 num;
135 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
136 struct hwtstamp_config tstamp_config;
137 bool hwts_tx_en;
138 bool hwts_rx_en;
139 struct ksz_irq ptpirq;
140 struct ksz_ptp_irq ptpmsg_irq[3];
141 ktime_t tstamp_msg;
142 struct completion tstamp_msg_comp;
143 #endif
144 bool manual_flow;
145 };
146
147 struct ksz_device {
148 struct dsa_switch *ds;
149 struct ksz_platform_data *pdata;
150 const struct ksz_chip_data *info;
151
152 struct mutex dev_mutex; /* device access */
153 struct mutex regmap_mutex; /* regmap access */
154 struct mutex alu_mutex; /* ALU access */
155 struct mutex vlan_mutex; /* vlan access */
156 const struct ksz_dev_ops *dev_ops;
157
158 struct device *dev;
159 struct regmap *regmap[__KSZ_NUM_REGMAPS];
160
161 void *priv;
162 int irq;
163
164 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
165
166 /* chip specific data */
167 u32 chip_id;
168 u8 chip_rev;
169 int cpu_port; /* port connected to CPU */
170 int phy_port_cnt;
171 phy_interface_t compat_interface;
172 bool synclko_125;
173 bool synclko_disable;
174 bool wakeup_source;
175
176 struct vlan_table *vlan_cache;
177
178 struct ksz_port *ports;
179 struct delayed_work mib_read;
180 unsigned long mib_read_interval;
181 u16 mirror_rx;
182 u16 mirror_tx;
183 u16 port_mask;
184 struct mutex lock_irq; /* IRQ Access */
185 struct ksz_irq girq;
186 struct ksz_ptp_data ptp_data;
187
188 struct ksz_switch_macaddr *switch_macaddr;
189 struct net_device *hsr_dev; /* HSR */
190 u8 hsr_ports;
191 };
192
193 /* List of supported models */
194 enum ksz_model {
195 KSZ8563,
196 KSZ8567,
197 KSZ8795,
198 KSZ8794,
199 KSZ8765,
200 KSZ8830,
201 KSZ9477,
202 KSZ9896,
203 KSZ9897,
204 KSZ9893,
205 KSZ9563,
206 KSZ9567,
207 LAN9370,
208 LAN9371,
209 LAN9372,
210 LAN9373,
211 LAN9374,
212 };
213
214 enum ksz_regs {
215 REG_SW_MAC_ADDR,
216 REG_IND_CTRL_0,
217 REG_IND_DATA_8,
218 REG_IND_DATA_CHECK,
219 REG_IND_DATA_HI,
220 REG_IND_DATA_LO,
221 REG_IND_MIB_CHECK,
222 REG_IND_BYTE,
223 P_FORCE_CTRL,
224 P_LINK_STATUS,
225 P_LOCAL_CTRL,
226 P_NEG_RESTART_CTRL,
227 P_REMOTE_STATUS,
228 P_SPEED_STATUS,
229 S_TAIL_TAG_CTRL,
230 P_STP_CTRL,
231 S_START_CTRL,
232 S_BROADCAST_CTRL,
233 S_MULTICAST_CTRL,
234 P_XMII_CTRL_0,
235 P_XMII_CTRL_1,
236 };
237
238 enum ksz_masks {
239 PORT_802_1P_REMAPPING,
240 SW_TAIL_TAG_ENABLE,
241 MIB_COUNTER_OVERFLOW,
242 MIB_COUNTER_VALID,
243 VLAN_TABLE_FID,
244 VLAN_TABLE_MEMBERSHIP,
245 VLAN_TABLE_VALID,
246 STATIC_MAC_TABLE_VALID,
247 STATIC_MAC_TABLE_USE_FID,
248 STATIC_MAC_TABLE_FID,
249 STATIC_MAC_TABLE_OVERRIDE,
250 STATIC_MAC_TABLE_FWD_PORTS,
251 DYNAMIC_MAC_TABLE_ENTRIES_H,
252 DYNAMIC_MAC_TABLE_MAC_EMPTY,
253 DYNAMIC_MAC_TABLE_NOT_READY,
254 DYNAMIC_MAC_TABLE_ENTRIES,
255 DYNAMIC_MAC_TABLE_FID,
256 DYNAMIC_MAC_TABLE_SRC_PORT,
257 DYNAMIC_MAC_TABLE_TIMESTAMP,
258 ALU_STAT_WRITE,
259 ALU_STAT_READ,
260 P_MII_TX_FLOW_CTRL,
261 P_MII_RX_FLOW_CTRL,
262 };
263
264 enum ksz_shifts {
265 VLAN_TABLE_MEMBERSHIP_S,
266 VLAN_TABLE,
267 STATIC_MAC_FWD_PORTS,
268 STATIC_MAC_FID,
269 DYNAMIC_MAC_ENTRIES_H,
270 DYNAMIC_MAC_ENTRIES,
271 DYNAMIC_MAC_FID,
272 DYNAMIC_MAC_TIMESTAMP,
273 DYNAMIC_MAC_SRC_PORT,
274 ALU_STAT_INDEX,
275 };
276
277 enum ksz_xmii_ctrl0 {
278 P_MII_100MBIT,
279 P_MII_10MBIT,
280 P_MII_FULL_DUPLEX,
281 P_MII_HALF_DUPLEX,
282 };
283
284 enum ksz_xmii_ctrl1 {
285 P_RGMII_SEL,
286 P_RMII_SEL,
287 P_GMII_SEL,
288 P_MII_SEL,
289 P_GMII_1GBIT,
290 P_GMII_NOT_1GBIT,
291 };
292
293 struct alu_struct {
294 /* entry 1 */
295 u8 is_static:1;
296 u8 is_src_filter:1;
297 u8 is_dst_filter:1;
298 u8 prio_age:3;
299 u32 _reserv_0_1:23;
300 u8 mstp:3;
301 /* entry 2 */
302 u8 is_override:1;
303 u8 is_use_fid:1;
304 u32 _reserv_1_1:23;
305 u8 port_forward:7;
306 /* entry 3 & 4*/
307 u32 _reserv_2_1:9;
308 u8 fid:7;
309 u8 mac[ETH_ALEN];
310 };
311
312 struct ksz_dev_ops {
313 int (*setup)(struct dsa_switch *ds);
314 void (*teardown)(struct dsa_switch *ds);
315 u32 (*get_port_addr)(int port, int offset);
316 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
317 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
318 void (*port_cleanup)(struct ksz_device *dev, int port);
319 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
320 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
321 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
322 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
323 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
324 u64 *cnt);
325 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
326 u64 *dropped, u64 *cnt);
327 void (*r_mib_stat64)(struct ksz_device *dev, int port);
328 int (*vlan_filtering)(struct ksz_device *dev, int port,
329 bool flag, struct netlink_ext_ack *extack);
330 int (*vlan_add)(struct ksz_device *dev, int port,
331 const struct switchdev_obj_port_vlan *vlan,
332 struct netlink_ext_ack *extack);
333 int (*vlan_del)(struct ksz_device *dev, int port,
334 const struct switchdev_obj_port_vlan *vlan);
335 int (*mirror_add)(struct ksz_device *dev, int port,
336 struct dsa_mall_mirror_tc_entry *mirror,
337 bool ingress, struct netlink_ext_ack *extack);
338 void (*mirror_del)(struct ksz_device *dev, int port,
339 struct dsa_mall_mirror_tc_entry *mirror);
340 int (*fdb_add)(struct ksz_device *dev, int port,
341 const unsigned char *addr, u16 vid, struct dsa_db db);
342 int (*fdb_del)(struct ksz_device *dev, int port,
343 const unsigned char *addr, u16 vid, struct dsa_db db);
344 int (*fdb_dump)(struct ksz_device *dev, int port,
345 dsa_fdb_dump_cb_t *cb, void *data);
346 int (*mdb_add)(struct ksz_device *dev, int port,
347 const struct switchdev_obj_port_mdb *mdb,
348 struct dsa_db db);
349 int (*mdb_del)(struct ksz_device *dev, int port,
350 const struct switchdev_obj_port_mdb *mdb,
351 struct dsa_db db);
352 void (*get_caps)(struct ksz_device *dev, int port,
353 struct phylink_config *config);
354 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
355 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
356 void (*port_init_cnt)(struct ksz_device *dev, int port);
357 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
358 unsigned int mode,
359 phy_interface_t interface,
360 struct phy_device *phydev, int speed,
361 int duplex, bool tx_pause, bool rx_pause);
362 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
363 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
364 void (*get_wol)(struct ksz_device *dev, int port,
365 struct ethtool_wolinfo *wol);
366 int (*set_wol)(struct ksz_device *dev, int port,
367 struct ethtool_wolinfo *wol);
368 void (*wol_pre_shutdown)(struct ksz_device *dev, bool *wol_enabled);
369 void (*config_cpu_port)(struct dsa_switch *ds);
370 int (*enable_stp_addr)(struct ksz_device *dev);
371 int (*reset)(struct ksz_device *dev);
372 int (*init)(struct ksz_device *dev);
373 void (*exit)(struct ksz_device *dev);
374 };
375
376 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
377 int ksz_switch_register(struct ksz_device *dev);
378 void ksz_switch_remove(struct ksz_device *dev);
379
380 void ksz_init_mib_timer(struct ksz_device *dev);
381 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port);
382 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
383 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
384 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
385 bool ksz_get_gbit(struct ksz_device *dev, int port);
386 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
387 extern const struct ksz_chip_data ksz_switch_chips[];
388 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
389 struct netlink_ext_ack *extack);
390 void ksz_switch_macaddr_put(struct dsa_switch *ds);
391 void ksz_switch_shutdown(struct ksz_device *dev);
392
393 /* Common register access functions */
ksz_regmap_8(struct ksz_device * dev)394 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
395 {
396 return dev->regmap[KSZ_REGMAP_8];
397 }
398
ksz_regmap_16(struct ksz_device * dev)399 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
400 {
401 return dev->regmap[KSZ_REGMAP_16];
402 }
403
ksz_regmap_32(struct ksz_device * dev)404 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
405 {
406 return dev->regmap[KSZ_REGMAP_32];
407 }
408
ksz_read8(struct ksz_device * dev,u32 reg,u8 * val)409 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
410 {
411 unsigned int value;
412 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
413
414 if (ret)
415 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
416 ERR_PTR(ret));
417
418 *val = value;
419 return ret;
420 }
421
ksz_read16(struct ksz_device * dev,u32 reg,u16 * val)422 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
423 {
424 unsigned int value;
425 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
426
427 if (ret)
428 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
429 ERR_PTR(ret));
430
431 *val = value;
432 return ret;
433 }
434
ksz_read32(struct ksz_device * dev,u32 reg,u32 * val)435 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
436 {
437 unsigned int value;
438 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
439
440 if (ret)
441 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
442 ERR_PTR(ret));
443
444 *val = value;
445 return ret;
446 }
447
ksz_read64(struct ksz_device * dev,u32 reg,u64 * val)448 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
449 {
450 u32 value[2];
451 int ret;
452
453 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
454 if (ret)
455 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
456 ERR_PTR(ret));
457 else
458 *val = (u64)value[0] << 32 | value[1];
459
460 return ret;
461 }
462
ksz_write8(struct ksz_device * dev,u32 reg,u8 value)463 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
464 {
465 int ret;
466
467 ret = regmap_write(ksz_regmap_8(dev), reg, value);
468 if (ret)
469 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
470 ERR_PTR(ret));
471
472 return ret;
473 }
474
ksz_write16(struct ksz_device * dev,u32 reg,u16 value)475 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
476 {
477 int ret;
478
479 ret = regmap_write(ksz_regmap_16(dev), reg, value);
480 if (ret)
481 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
482 ERR_PTR(ret));
483
484 return ret;
485 }
486
ksz_write32(struct ksz_device * dev,u32 reg,u32 value)487 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
488 {
489 int ret;
490
491 ret = regmap_write(ksz_regmap_32(dev), reg, value);
492 if (ret)
493 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
494 ERR_PTR(ret));
495
496 return ret;
497 }
498
ksz_rmw16(struct ksz_device * dev,u32 reg,u16 mask,u16 value)499 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
500 u16 value)
501 {
502 int ret;
503
504 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
505 if (ret)
506 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
507 ERR_PTR(ret));
508
509 return ret;
510 }
511
ksz_rmw32(struct ksz_device * dev,u32 reg,u32 mask,u32 value)512 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
513 u32 value)
514 {
515 int ret;
516
517 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
518 if (ret)
519 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
520 ERR_PTR(ret));
521
522 return ret;
523 }
524
ksz_write64(struct ksz_device * dev,u32 reg,u64 value)525 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
526 {
527 u32 val[2];
528
529 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
530 value = swab64(value);
531 val[0] = swab32(value & 0xffffffffULL);
532 val[1] = swab32(value >> 32ULL);
533
534 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
535 }
536
ksz_rmw8(struct ksz_device * dev,int offset,u8 mask,u8 val)537 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
538 {
539 int ret;
540
541 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
542 if (ret)
543 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
544 ERR_PTR(ret));
545
546 return ret;
547 }
548
ksz_pread8(struct ksz_device * dev,int port,int offset,u8 * data)549 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
550 u8 *data)
551 {
552 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
553 }
554
ksz_pread16(struct ksz_device * dev,int port,int offset,u16 * data)555 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
556 u16 *data)
557 {
558 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
559 }
560
ksz_pread32(struct ksz_device * dev,int port,int offset,u32 * data)561 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
562 u32 *data)
563 {
564 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
565 }
566
ksz_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)567 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
568 u8 data)
569 {
570 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
571 }
572
ksz_pwrite16(struct ksz_device * dev,int port,int offset,u16 data)573 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
574 u16 data)
575 {
576 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
577 data);
578 }
579
ksz_pwrite32(struct ksz_device * dev,int port,int offset,u32 data)580 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
581 u32 data)
582 {
583 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
584 data);
585 }
586
ksz_prmw8(struct ksz_device * dev,int port,int offset,u8 mask,u8 val)587 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
588 u8 mask, u8 val)
589 {
590 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
591 mask, val);
592 }
593
ksz_prmw32(struct ksz_device * dev,int port,int offset,u32 mask,u32 val)594 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
595 u32 mask, u32 val)
596 {
597 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
598 mask, val);
599 }
600
ksz_regmap_lock(void * __mtx)601 static inline void ksz_regmap_lock(void *__mtx)
602 {
603 struct mutex *mtx = __mtx;
604 mutex_lock(mtx);
605 }
606
ksz_regmap_unlock(void * __mtx)607 static inline void ksz_regmap_unlock(void *__mtx)
608 {
609 struct mutex *mtx = __mtx;
610 mutex_unlock(mtx);
611 }
612
ksz_is_ksz87xx(struct ksz_device * dev)613 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
614 {
615 return dev->chip_id == KSZ8795_CHIP_ID ||
616 dev->chip_id == KSZ8794_CHIP_ID ||
617 dev->chip_id == KSZ8765_CHIP_ID;
618 }
619
ksz_is_ksz88x3(struct ksz_device * dev)620 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
621 {
622 return dev->chip_id == KSZ8830_CHIP_ID;
623 }
624
is_ksz8(struct ksz_device * dev)625 static inline bool is_ksz8(struct ksz_device *dev)
626 {
627 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev);
628 }
629
is_lan937x(struct ksz_device * dev)630 static inline int is_lan937x(struct ksz_device *dev)
631 {
632 return dev->chip_id == LAN9370_CHIP_ID ||
633 dev->chip_id == LAN9371_CHIP_ID ||
634 dev->chip_id == LAN9372_CHIP_ID ||
635 dev->chip_id == LAN9373_CHIP_ID ||
636 dev->chip_id == LAN9374_CHIP_ID;
637 }
638
639 /* STP State Defines */
640 #define PORT_TX_ENABLE BIT(2)
641 #define PORT_RX_ENABLE BIT(1)
642 #define PORT_LEARN_DISABLE BIT(0)
643
644 /* Switch ID Defines */
645 #define REG_CHIP_ID0 0x00
646
647 #define SW_FAMILY_ID_M GENMASK(15, 8)
648 #define KSZ87_FAMILY_ID 0x87
649 #define KSZ88_FAMILY_ID 0x88
650
651 #define KSZ8_PORT_STATUS_0 0x08
652 #define KSZ8_PORT_FIBER_MODE BIT(7)
653
654 #define SW_CHIP_ID_M GENMASK(7, 4)
655 #define KSZ87_CHIP_ID_94 0x6
656 #define KSZ87_CHIP_ID_95 0x9
657 #define KSZ88_CHIP_ID_63 0x3
658
659 #define SW_REV_ID_M GENMASK(7, 4)
660
661 /* KSZ9893, KSZ9563, KSZ8563 specific register */
662 #define REG_CHIP_ID4 0x0f
663 #define SKU_ID_KSZ8563 0x3c
664 #define SKU_ID_KSZ9563 0x1c
665
666 /* Driver set switch broadcast storm protection at 10% rate. */
667 #define BROADCAST_STORM_PROT_RATE 10
668
669 /* 148,800 frames * 67 ms / 100 */
670 #define BROADCAST_STORM_VALUE 9969
671
672 #define BROADCAST_STORM_RATE_HI 0x07
673 #define BROADCAST_STORM_RATE_LO 0xFF
674 #define BROADCAST_STORM_RATE 0x07FF
675
676 #define MULTICAST_STORM_DISABLE BIT(6)
677
678 #define SW_START 0x01
679
680 /* xMII configuration */
681 #define P_MII_DUPLEX_M BIT(6)
682 #define P_MII_100MBIT_M BIT(4)
683
684 #define P_GMII_1GBIT_M BIT(6)
685 #define P_RGMII_ID_IG_ENABLE BIT(4)
686 #define P_RGMII_ID_EG_ENABLE BIT(3)
687 #define P_MII_MAC_MODE BIT(2)
688 #define P_MII_SEL_M 0x3
689
690 /* Interrupt */
691 #define REG_SW_PORT_INT_STATUS__1 0x001B
692 #define REG_SW_PORT_INT_MASK__1 0x001F
693
694 #define REG_PORT_INT_STATUS 0x001B
695 #define REG_PORT_INT_MASK 0x001F
696
697 #define PORT_SRC_PHY_INT 1
698 #define PORT_SRC_PTP_INT 2
699
700 #define KSZ8795_HUGE_PACKET_SIZE 2000
701 #define KSZ8863_HUGE_PACKET_SIZE 1916
702 #define KSZ8863_NORMAL_PACKET_SIZE 1536
703 #define KSZ8_LEGAL_PACKET_SIZE 1518
704 #define KSZ9477_MAX_FRAME_SIZE 9000
705
706 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
707 /* Drive Strength of I/O Pad
708 * 0: 8mA, 1: 16mA
709 */
710 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
711
712 #define KSZ8795_REG_SW_CTRL_20 0xa3
713 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d
714 #define SW_DRIVE_STRENGTH_M 0x7
715 #define SW_DRIVE_STRENGTH_2MA 0
716 #define SW_DRIVE_STRENGTH_4MA 1
717 #define SW_DRIVE_STRENGTH_8MA 2
718 #define SW_DRIVE_STRENGTH_12MA 3
719 #define SW_DRIVE_STRENGTH_16MA 4
720 #define SW_DRIVE_STRENGTH_20MA 5
721 #define SW_DRIVE_STRENGTH_24MA 6
722 #define SW_DRIVE_STRENGTH_28MA 7
723 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
724 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
725
726 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
727 #define KSZ9477_OUT_RATE_NO_LIMIT 0
728
729 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
730
731 #define KSZ9477_PORT_TC_MAP_S 4
732
733 /* CBS related registers */
734 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
735
736 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
737
738 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
739 #define MTI_SCHEDULE_STRICT_PRIO 0
740 #define MTI_SCHEDULE_WRR 2
741 #define MTI_SHAPING_M GENMASK(5, 4)
742 #define MTI_SHAPING_OFF 0
743 #define MTI_SHAPING_SRP 1
744 #define MTI_SHAPING_TIME_AWARE 2
745
746 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
747 #define KSZ9477_DEFAULT_WRR_WEIGHT 1
748
749 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
750 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
751
752 /* Regmap tables generation */
753 #define KSZ_SPI_OP_RD 3
754 #define KSZ_SPI_OP_WR 2
755
756 #define swabnot_used(x) 0
757
758 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
759 swab##swp((opcode) << ((regbits) + (regpad)))
760
761 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
762 { \
763 .name = #width, \
764 .val_bits = (width), \
765 .reg_stride = 1, \
766 .reg_bits = (regbits) + (regalign), \
767 .pad_bits = (regpad), \
768 .max_register = BIT(regbits) - 1, \
769 .cache_type = REGCACHE_NONE, \
770 .read_flag_mask = \
771 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
772 regbits, regpad), \
773 .write_flag_mask = \
774 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
775 regbits, regpad), \
776 .lock = ksz_regmap_lock, \
777 .unlock = ksz_regmap_unlock, \
778 .reg_format_endian = REGMAP_ENDIAN_BIG, \
779 .val_format_endian = REGMAP_ENDIAN_BIG \
780 }
781
782 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
783 static const struct regmap_config ksz##_regmap_config[] = { \
784 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
785 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
786 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
787 }
788
789 #endif
790