1 /* $OpenBSD: am7930reg.h,v 1.6 2011/09/03 20:03:29 miod Exp $ */ 2 /* $NetBSD: am7930reg.h,v 1.7 2005/12/11 12:21:25 christos Exp $ */ 3 4 /* 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * @(#)bsd_audioreg.h 8.1 (Berkeley) 6/11/93 42 */ 43 44 /* 45 * Am79C30A direct registers 46 */ 47 48 #define AM7930_DREG_CR 0 /* command register (wo) */ 49 #define AM7930_DREG_IR 0 /* interrupt register (ro) */ 50 #define AM7930_IR_DTTHRSH 0x01 /* D-channel TX empty */ 51 #define AM7930_IR_DRTHRSH 0x02 /* D-channel RX avail */ 52 #define AM7930_IR_DSRI 0x04 /* D-channel packet status */ 53 #define AM7930_IR_DERI 0x08 /* D-channel error */ 54 #define AM7930_IR_BBUFF 0x10 /* Bb or Bc byte avail/empty */ 55 #define AM7930_IR_LSRI 0x20 /* LIU status */ 56 #define AM7930_IR_DSR2I 0x40 /* D-channel buffer status */ 57 #define AM7930_IR_PPMF 0x80 /* Multiframe or PP */ 58 #define AM7930_DREG_DR 1 /* data register (rw) */ 59 #define AM7930_DREG_DSR1 2 /* D-channel status register 1 (ro) */ 60 #define AM7930_DREG_DER 3 /* D-channel error register (ro) */ 61 #define AM7930_DREG_DCTB 4 /* D-channel transmit register (wo) */ 62 #define AM7930_DREG_DCRB 4 /* D-channel receive register (ro) */ 63 #define AM7930_DREG_BBTB 5 /* Bb-channel transmit register (wo) */ 64 #define AM7930_DREG_BBRB 5 /* Bb-channel receive register (ro) */ 65 #define AM7930_DREG_BCTB 6 /* Bc-channel transmit register (wo) */ 66 #define AM7930_DREG_BCRB 6 /* Bc-channel receive register (ro) */ 67 #define AM7930_DREG_DSR2 7 /* D-channel status register 2 (ro) */ 68 69 #define AM7930_DREG_SIZE 8 70 71 /* 72 * Am79C30A indirect registers 73 */ 74 75 /* Initialisation registers */ 76 77 #define AM7930_IREG_INIT 0x21 78 #define AM7930_IREG_INIT2 0x20 79 /* power mode selection */ 80 #define AM7930_INIT_PMS_IDLE 0x00 81 #define AM7930_INIT_PMS_ACTIVE 0x01 82 #define AM7930_INIT_PMS_ACTIVE_DATA 0x02 83 #define AM7930_INIT_PMS_MASK 0x03 84 /* interrupt selection */ 85 #define AM7930_INIT_INT_ENABLE 0x00 86 #define AM7930_INIT_INT_DISABLE 0x04 87 #define AM7930_INIT_INT_MASK 0x04 88 /* clock divider selection */ 89 #define AM7930_INIT_CDS_DIV2 0x00 90 #define AM7930_INIT_CDS_DIV1 0x08 91 #define AM7930_INIT_CDS_DIV4 0x10 92 #define AM7930_INIT_CDS_DIV3 0x20 93 #define AM7930_INIT_CDS_MASK 0x38 94 /* abort selection */ 95 #define AM7930_INIT_AS_RX 0x40 96 #define AM7930_INIT_AS_NRX 0x00 97 #define AM7930_INIT_AS_TX 0x80 98 #define AM7930_INIT_AS_NTX 0x00 99 #define AM7930_INIT_AS_MASK 0xc0 100 101 /* Line Interface Unit registers */ 102 103 #define AM7930_IREG_LIU_LSR 0xa1 /* LIU status (ro) */ 104 #define AM7930_IREG_LIU_LPR 0xa2 /* LIU priority (rw) */ 105 #define AM7930_IREG_LIU_LMR1 0xa3 /* LIU mode register 1 (rw) */ 106 #define AM7930_IREG_LIU_LMR2 0xa4 /* LIU mode register 2 (rw) */ 107 #define AM7930_IREG_LIU_2_4 0xa5 108 #define AM7930_IREG_LIU_MF 0xa6 /* Multiframe (rw) */ 109 #define AM7930_IREG_LIU_MFSB 0xa7 /* Multiframe S-bit/status (ro) */ 110 #define AM7930_IREG_LIU_MFQB 0xa8 /* Multiframe Q-bit buffer (wo) */ 111 112 /* Multiplexer registers */ 113 114 #define AM7930_IREG_MUX_MCR1 0x41 /* MUX command register 1 (rw) */ 115 #define AM7930_IREG_MUX_MCR2 0x42 /* MUX command register 2 (rw) */ 116 #define AM7930_IREG_MUX_MCR3 0x43 /* MUX command register 3 (rw) */ 117 #define AM7930_MCRCHAN_NC 0x00 118 #define AM7930_MCRCHAN_B1 0x01 119 #define AM7930_MCRCHAN_B2 0x02 120 #define AM7930_MCRCHAN_BA 0x03 121 #define AM7930_MCRCHAN_BB 0x04 122 #define AM7930_MCRCHAN_BC 0x05 123 #define AM7930_MCRCHAN_BD 0x06 124 #define AM7930_MCRCHAN_BE 0x07 125 #define AM7930_MCRCHAN_BF 0x08 126 #define AM7930_IREG_MUX_MCR4 0x44 /* MUX command register 4 (rw) */ 127 #define AM7930_MCR4_INT_ENABLE (1 << 3) 128 #define AM7930_MCR4_SWAPBB (1 << 4) 129 #define AM7930_MCR4_SWAPBC (1 << 5) 130 #define AM7930_IREG_MUX_1_4 0x45 131 132 /* Main Audio Processor registers */ 133 134 #define AM7930_IREG_MAP_X 0x61 /* X filter coefficient (rw) */ 135 #define AM7930_IREG_MAP_R 0x62 /* R filter coefficient (rw) */ 136 #define AM7930_IREG_MAP_GX 0x63 /* GX gain coefficient (rw) */ 137 #define AM7930_IREG_MAP_GR 0x64 /* GR gain coefficient (rw) */ 138 #define AM7930_IREG_MAP_GER 0x65 /* GER gain coefficient (rw) */ 139 #define AM7930_IREG_MAP_STG 0x66 /* Sidetone gain coefficient (rw) */ 140 #define AM7930_IREG_MAP_FTGR 0x67 /* Frequency tone generator 1,2 (rw) */ 141 #define AM7930_IREG_MAP_ATGR 0x68 /* Amplitude tone generator 1,2 (rw) */ 142 #define AM7930_IREG_MAP_MMR1 0x69 /* MAP mode register 1 (rw) */ 143 #define AM7930_MMR1_ALAW 0x01 144 #define AM7930_MMR1_GX 0x02 145 #define AM7930_MMR1_GR 0x04 146 #define AM7930_MMR1_GER 0x08 147 #define AM7930_MMR1_X 0x10 148 #define AM7930_MMR1_R 0x20 149 #define AM7930_MMR1_STG 0x40 150 #define AM7930_MMR1_LOOP 0x80 151 #define AM7930_IREG_MAP_MMR2 0x6a /* MAP mode register 2 (rw) */ 152 #define AM7930_MMR2_AINB 0x01 153 #define AM7930_MMR2_LS 0x02 154 #define AM7930_MMR2_DTMF 0x04 155 #define AM7930_MMR2_GEN 0x08 156 #define AM7930_MMR2_RNG 0x10 157 #define AM7930_MMR2_DIS_HPF 0x20 158 #define AM7930_MMR2_DIS_AZ 0x40 159 #define AM7930_IREG_MAP_1_10 0x6b 160 #define AM7930_IREG_MAP_MMR3 0x6c /* MAP mode register 3 (rw) */ 161 #define AM7930_MMR3_BOTH 0x02 162 #define AM7930_MMR3_MBZ 0x01 163 #define AM7930_MMR3_GA 0x70 164 #define AM7930_MMR3_GA0 0x00 165 #define AM7930_MMR3_GA6 0x10 166 #define AM7930_MMR3_GA12 0x20 167 #define AM7930_MMR3_GA18 0x30 168 #define AM7930_MMR3_GA24 0x40 169 #define AM7930_MMR3_MUTE 0x08 170 #define AM7930_MMR3_STR 0x01 171 #define AM7930_IREG_MAP_STRA 0x6d /* Second tone ringer amplitude (rw) */ 172 #define AM7930_IREG_MAP_STRF 0x6e /* Second tone ringer frequency (rw) */ 173 174 /* Data Link Controller registers */ 175 176 #define AM7930_IREG_DLC_FRAR123 0x81 /* First rcvd byte address 123 (rw) */ 177 #define AM7930_IREG_DLC_SRAR123 0x82 /* Second rcvd byte address 123 (rw) */ 178 #define AM7930_IREG_DLC_TAR 0x83 /* Transmit address (rw) */ 179 #define AM7930_IREG_DLC_DRLR 0x84 /* D-channel receive byte limit (rw) */ 180 #define AM7930_IREG_DLC_DTCR 0x85 /* D-channel transmit byte count (rw)*/ 181 #define AM7930_IREG_DLC_DMR1 0x86 /* D-channel mode register 1 (rw) */ 182 #define AM7930_IREG_DLC_DMR2 0x87 /* D-channel mode register 2 (rw) */ 183 #define AM7930_IREG_DLC_1_7 0x88 184 #define AM7930_IREG_DLC_DRCR 0x89 /* D-channel receive byte count (ro) */ 185 #define AM7930_IREG_DLC_RNGR1 0x8a /* Random number generator LSB (rw) */ 186 #define AM7930_IREG_DLC_RNGR2 0x8b /* Random number generator MSB (rw) */ 187 #define AM7930_IREG_DLC_FRAR4 0x8c /* First rcvd byte address 4 (rw) */ 188 #define AM7930_IREG_DLC_SRAR4 0x8d /* Second rcvd byte address 4 (rw) */ 189 #define AM7930_IREG_DLC_DMR3 0x8e /* D-channel mode register 3 (rw) */ 190 #define AM7930_IREG_DLC_DMR4 0x8f /* D-channel mode register 4 (rw) */ 191 #define AM7930_IREG_DLC_12_15 0x90 192 #define AM7930_IREG_DLC_ASR 0x91 /* Address status register (ro) */ 193 #define AM7930_IREG_DLC_EFCR 0x92 /* Extended FIFO control (rw) */ 194 195 /* Peripheral Port registers */ 196 197 #define AM7930_IREG_PP_PPCR1 0xc0 /* Peripheral port control 1 (rw) */ 198 #define AM7930_PPCR1_DISABLE 0x00 199 #define AM7930_PPCR1_SBP 0x01 200 #define AM7930_PPCR1_IOM2SL 0x10 201 #define AM7930_PPCR1_IOM2MA 0x11 202 #define AM7930_IREG_PP_PPSR 0xc1 /* Peripheral port control 2 (ro) */ 203 #define AM7930_IREG_PP_PPIER 0xc2 /* Peripheral port intr enable (rw) */ 204 #define AM7930_IREG_PP_MTDR 0xc3 /* monitor transmit data (wo) */ 205 #define AM7930_IREG_PP_MRDR 0xc3 /* monitor receive data (ro) */ 206 #define AM7930_IREG_PP_CITDR0 0xc4 /* C/I transmit data register 0 (wo) */ 207 #define AM7930_IREG_PP_CIRDR0 0xc4 /* C/I receive data register 0 (ro) */ 208 #define AM7930_IREG_PP_CITDR1 0xc5 /* C/I transmit data register 1 (wo) */ 209 #define AM7930_IREG_PP_CIRDR1 0xc5 /* C/I receive data register 1 (ro) */ 210 #define AM7930_IREG_PP_PPCR2 0xc8 /* Peripheral port control 2 (rw) */ 211