1 /*	$NetBSD: amd_shared.h,v 1.4 2021/12/19 10:59:02 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2015 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 
25 #ifndef __AMD_SHARED_H__
26 #define __AMD_SHARED_H__
27 
28 #include <drm/amd_asic_type.h>
29 
30 
31 #define AMD_MAX_USEC_TIMEOUT		1000000  /* 1000 ms */
32 
33 /*
34  * Chip flags
35  */
36 enum amd_chip_flags {
37 	AMD_ASIC_MASK = 0x0000ffffUL,
38 	AMD_FLAGS_MASK  = 0xffff0000UL,
39 	AMD_IS_MOBILITY = 0x00010000UL,
40 	AMD_IS_APU      = 0x00020000UL,
41 	AMD_IS_PX       = 0x00040000UL,
42 	AMD_EXP_HW_SUPPORT = 0x00080000UL,
43 };
44 
45 enum amd_ip_block_type {
46 	AMD_IP_BLOCK_TYPE_COMMON,
47 	AMD_IP_BLOCK_TYPE_GMC,
48 	AMD_IP_BLOCK_TYPE_IH,
49 	AMD_IP_BLOCK_TYPE_SMC,
50 	AMD_IP_BLOCK_TYPE_PSP,
51 	AMD_IP_BLOCK_TYPE_DCE,
52 	AMD_IP_BLOCK_TYPE_GFX,
53 	AMD_IP_BLOCK_TYPE_SDMA,
54 	AMD_IP_BLOCK_TYPE_UVD,
55 	AMD_IP_BLOCK_TYPE_VCE,
56 	AMD_IP_BLOCK_TYPE_ACP,
57 	AMD_IP_BLOCK_TYPE_VCN,
58 	AMD_IP_BLOCK_TYPE_MES,
59 	AMD_IP_BLOCK_TYPE_JPEG
60 };
61 
62 enum amd_clockgating_state {
63 	AMD_CG_STATE_GATE = 0,
64 	AMD_CG_STATE_UNGATE,
65 };
66 
67 
68 enum amd_powergating_state {
69 	AMD_PG_STATE_GATE = 0,
70 	AMD_PG_STATE_UNGATE,
71 };
72 
73 
74 /* CG flags */
75 #define AMD_CG_SUPPORT_GFX_MGCG			(1 << 0)
76 #define AMD_CG_SUPPORT_GFX_MGLS			(1 << 1)
77 #define AMD_CG_SUPPORT_GFX_CGCG			(1 << 2)
78 #define AMD_CG_SUPPORT_GFX_CGLS			(1 << 3)
79 #define AMD_CG_SUPPORT_GFX_CGTS			(1 << 4)
80 #define AMD_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
81 #define AMD_CG_SUPPORT_GFX_CP_LS		(1 << 6)
82 #define AMD_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
83 #define AMD_CG_SUPPORT_MC_LS			(1 << 8)
84 #define AMD_CG_SUPPORT_MC_MGCG			(1 << 9)
85 #define AMD_CG_SUPPORT_SDMA_LS			(1 << 10)
86 #define AMD_CG_SUPPORT_SDMA_MGCG		(1 << 11)
87 #define AMD_CG_SUPPORT_BIF_LS			(1 << 12)
88 #define AMD_CG_SUPPORT_UVD_MGCG			(1 << 13)
89 #define AMD_CG_SUPPORT_VCE_MGCG			(1 << 14)
90 #define AMD_CG_SUPPORT_HDP_LS			(1 << 15)
91 #define AMD_CG_SUPPORT_HDP_MGCG			(1 << 16)
92 #define AMD_CG_SUPPORT_ROM_MGCG			(1 << 17)
93 #define AMD_CG_SUPPORT_DRM_LS			(1 << 18)
94 #define AMD_CG_SUPPORT_BIF_MGCG			(1 << 19)
95 #define AMD_CG_SUPPORT_GFX_3D_CGCG		(1 << 20)
96 #define AMD_CG_SUPPORT_GFX_3D_CGLS		(1 << 21)
97 #define AMD_CG_SUPPORT_DRM_MGCG			(1 << 22)
98 #define AMD_CG_SUPPORT_DF_MGCG			(1 << 23)
99 #define AMD_CG_SUPPORT_VCN_MGCG			(1 << 24)
100 #define AMD_CG_SUPPORT_HDP_DS			(1 << 25)
101 #define AMD_CG_SUPPORT_HDP_SD			(1 << 26)
102 #define AMD_CG_SUPPORT_IH_CG			(1 << 27)
103 #define AMD_CG_SUPPORT_ATHUB_LS			(1 << 28)
104 #define AMD_CG_SUPPORT_ATHUB_MGCG		(1 << 29)
105 #define AMD_CG_SUPPORT_JPEG_MGCG		(1 << 30)
106 /* PG flags */
107 #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
108 #define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
109 #define AMD_PG_SUPPORT_GFX_DMG			(1 << 2)
110 #define AMD_PG_SUPPORT_UVD			(1 << 3)
111 #define AMD_PG_SUPPORT_VCE			(1 << 4)
112 #define AMD_PG_SUPPORT_CP			(1 << 5)
113 #define AMD_PG_SUPPORT_GDS			(1 << 6)
114 #define AMD_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
115 #define AMD_PG_SUPPORT_SDMA			(1 << 8)
116 #define AMD_PG_SUPPORT_ACP			(1 << 9)
117 #define AMD_PG_SUPPORT_SAMU			(1 << 10)
118 #define AMD_PG_SUPPORT_GFX_QUICK_MG		(1 << 11)
119 #define AMD_PG_SUPPORT_GFX_PIPELINE		(1 << 12)
120 #define AMD_PG_SUPPORT_MMHUB			(1 << 13)
121 #define AMD_PG_SUPPORT_VCN			(1 << 14)
122 #define AMD_PG_SUPPORT_VCN_DPG			(1 << 15)
123 #define AMD_PG_SUPPORT_ATHUB			(1 << 16)
124 #define AMD_PG_SUPPORT_JPEG			(1 << 17)
125 
126 enum PP_FEATURE_MASK {
127 	PP_SCLK_DPM_MASK = 0x1,
128 	PP_MCLK_DPM_MASK = 0x2,
129 	PP_PCIE_DPM_MASK = 0x4,
130 	PP_SCLK_DEEP_SLEEP_MASK = 0x8,
131 	PP_POWER_CONTAINMENT_MASK = 0x10,
132 	PP_UVD_HANDSHAKE_MASK = 0x20,
133 	PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
134 	PP_VBI_TIME_SUPPORT_MASK = 0x80,
135 	PP_ULV_MASK = 0x100,
136 	PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
137 	PP_CLOCK_STRETCH_MASK = 0x400,
138 	PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
139 	PP_SOCCLK_DPM_MASK = 0x1000,
140 	PP_DCEFCLK_DPM_MASK = 0x2000,
141 	PP_OVERDRIVE_MASK = 0x4000,
142 	PP_GFXOFF_MASK = 0x8000,
143 	PP_ACG_MASK = 0x10000,
144 	PP_STUTTER_MODE = 0x20000,
145 	PP_AVFS_MASK = 0x40000,
146 };
147 
148 enum DC_FEATURE_MASK {
149 	DC_FBC_MASK = 0x1,
150 	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
151 	DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
152 	DC_PSR_MASK = 0x8,
153 };
154 
155 enum amd_dpm_forced_level;
156 /**
157  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
158  */
159 struct amd_ip_funcs {
160 	/** @name: Name of IP block */
161 	const char *name;
162 	/**
163 	 * @early_init:
164 	 *
165 	 * sets up early driver state (pre sw_init),
166 	 * does not configure hw - Optional
167 	 */
168 	int (*early_init)(void *handle);
169 	/** @late_init: sets up late driver/hw state (post hw_init) - Optional */
170 	int (*late_init)(void *handle);
171 	/** @sw_init: sets up driver state, does not configure hw */
172 	int (*sw_init)(void *handle);
173 	/** @sw_fini: tears down driver state, does not configure hw */
174 	int (*sw_fini)(void *handle);
175 	/** @hw_init: sets up the hw state */
176 	int (*hw_init)(void *handle);
177 	/** @hw_fini: tears down the hw state */
178 	int (*hw_fini)(void *handle);
179 	/** @late_fini: final cleanup */
180 	void (*late_fini)(void *handle);
181 	/** @suspend: handles IP specific hw/sw changes for suspend */
182 	int (*suspend)(void *handle);
183 	/** @resume: handles IP specific hw/sw changes for resume */
184 	int (*resume)(void *handle);
185 	/** @is_idle: returns current IP block idle status */
186 	bool (*is_idle)(void *handle);
187 	/** @wait_for_idle: poll for idle */
188 	int (*wait_for_idle)(void *handle);
189 	/** @check_soft_reset: check soft reset the IP block */
190 	bool (*check_soft_reset)(void *handle);
191 	/** @pre_soft_reset: pre soft reset the IP block */
192 	int (*pre_soft_reset)(void *handle);
193 	/** @soft_reset: soft reset the IP block */
194 	int (*soft_reset)(void *handle);
195 	/** @post_soft_reset: post soft reset the IP block */
196 	int (*post_soft_reset)(void *handle);
197 	/** @set_clockgating_state: enable/disable cg for the IP block */
198 	int (*set_clockgating_state)(void *handle,
199 				     enum amd_clockgating_state state);
200 	/** @set_powergating_state: enable/disable pg for the IP block */
201 	int (*set_powergating_state)(void *handle,
202 				     enum amd_powergating_state state);
203 	/** @get_clockgating_state: get current clockgating status */
204 	void (*get_clockgating_state)(void *handle, u32 *flags);
205 	/** @enable_umd_pstate: enable UMD powerstate */
206 	int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
207 };
208 
209 
210 #endif /* __AMD_SHARED_H__ */
211