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35 
36 #ifndef __HW_APPS_RCM_H__
37 #define __HW_APPS_RCM_H__
38 
39 //*****************************************************************************
40 //
41 // The following are defines for the APPS_RCM register offsets.
42 //
43 //*****************************************************************************
44 #define APPS_RCM_O_CAMERA_CLK_GEN \
45                                 0x00000000
46 
47 #define APPS_RCM_O_CAMERA_CLK_GATING \
48                                 0x00000004
49 
50 #define APPS_RCM_O_CAMERA_SOFT_RESET \
51                                 0x00000008
52 
53 #define APPS_RCM_O_MCASP_CLK_GATING \
54                                 0x00000014
55 
56 #define APPS_RCM_O_MCASP_SOFT_RESET \
57                                 0x00000018
58 
59 #define APPS_RCM_O_MMCHS_CLK_GEN \
60                                 0x00000020
61 
62 #define APPS_RCM_O_MMCHS_CLK_GATING \
63                                 0x00000024
64 
65 #define APPS_RCM_O_MMCHS_SOFT_RESET \
66                                 0x00000028
67 
68 #define APPS_RCM_O_MCSPI_A1_CLK_GEN \
69                                 0x0000002C
70 
71 #define APPS_RCM_O_MCSPI_A1_CLK_GATING \
72                                 0x00000030
73 
74 #define APPS_RCM_O_MCSPI_A1_SOFT_RESET \
75                                 0x00000034
76 
77 #define APPS_RCM_O_MCSPI_A2_CLK_GEN \
78                                 0x00000038
79 
80 #define APPS_RCM_O_MCSPI_A2_CLK_GATING \
81                                 0x00000040
82 
83 #define APPS_RCM_O_MCSPI_A2_SOFT_RESET \
84                                 0x00000044
85 
86 #define APPS_RCM_O_UDMA_A_CLK_GATING \
87                                 0x00000048
88 
89 #define APPS_RCM_O_UDMA_A_SOFT_RESET \
90                                 0x0000004C
91 
92 #define APPS_RCM_O_GPIO_A_CLK_GATING \
93                                 0x00000050
94 
95 #define APPS_RCM_O_GPIO_A_SOFT_RESET \
96                                 0x00000054
97 
98 #define APPS_RCM_O_GPIO_B_CLK_GATING \
99                                 0x00000058
100 
101 #define APPS_RCM_O_GPIO_B_SOFT_RESET \
102                                 0x0000005C
103 
104 #define APPS_RCM_O_GPIO_C_CLK_GATING \
105                                 0x00000060
106 
107 #define APPS_RCM_O_GPIO_C_SOFT_RESET \
108                                 0x00000064
109 
110 #define APPS_RCM_O_GPIO_D_CLK_GATING \
111                                 0x00000068
112 
113 #define APPS_RCM_O_GPIO_D_SOFT_RESET \
114                                 0x0000006C
115 
116 #define APPS_RCM_O_GPIO_E_CLK_GATING \
117                                 0x00000070
118 
119 #define APPS_RCM_O_GPIO_E_SOFT_RESET \
120                                 0x00000074
121 
122 #define APPS_RCM_O_WDOG_A_CLK_GATING \
123                                 0x00000078
124 
125 #define APPS_RCM_O_WDOG_A_SOFT_RESET \
126                                 0x0000007C
127 
128 #define APPS_RCM_O_UART_A0_CLK_GATING \
129                                 0x00000080
130 
131 #define APPS_RCM_O_UART_A0_SOFT_RESET \
132                                 0x00000084
133 
134 #define APPS_RCM_O_UART_A1_CLK_GATING \
135                                 0x00000088
136 
137 #define APPS_RCM_O_UART_A1_SOFT_RESET \
138                                 0x0000008C
139 
140 #define APPS_RCM_O_GPT_A0_CLK_GATING \
141                                 0x00000090
142 
143 #define APPS_RCM_O_GPT_A0_SOFT_RESET \
144                                 0x00000094
145 
146 #define APPS_RCM_O_GPT_A1_CLK_GATING \
147                                 0x00000098
148 
149 #define APPS_RCM_O_GPT_A1_SOFT_RESET \
150                                 0x0000009C
151 
152 #define APPS_RCM_O_GPT_A2_CLK_GATING \
153                                 0x000000A0
154 
155 #define APPS_RCM_O_GPT_A2_SOFT_RESET \
156                                 0x000000A4
157 
158 #define APPS_RCM_O_GPT_A3_CLK_GATING \
159                                 0x000000A8
160 
161 #define APPS_RCM_O_GPT_A3_SOFT_RESET \
162                                 0x000000AC
163 
164 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \
165                                 0x000000B0
166 
167 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \
168                                 0x000000B4
169 
170 #define APPS_RCM_O_CRYPTO_CLK_GATING \
171                                 0x000000B8
172 
173 #define APPS_RCM_O_CRYPTO_SOFT_RESET \
174                                 0x000000BC
175 
176 #define APPS_RCM_O_MCSPI_S0_CLK_GATING \
177                                 0x000000C8
178 
179 #define APPS_RCM_O_MCSPI_S0_SOFT_RESET \
180                                 0x000000CC
181 
182 #define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \
183                                 0x000000D0
184 
185 #define APPS_RCM_O_I2C_CLK_GATING \
186                                 0x000000D8
187 
188 #define APPS_RCM_O_I2C_SOFT_RESET \
189                                 0x000000DC
190 
191 #define APPS_RCM_O_APPS_LPDS_REQ \
192                                 0x000000E4
193 
194 #define APPS_RCM_O_APPS_TURBO_REQ \
195                                 0x000000EC
196 
197 #define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \
198                                 0x00000108
199 
200 #define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \
201                                 0x0000010C
202 
203 #define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \
204                                 0x00000110
205 
206 #define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \
207                                 0x00000114
208 
209 #define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \
210                                 0x00000118
211 
212 #define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \
213                                 0x00000120
214 
215 #define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \
216                                 0x00000124
217 
218 
219 
220 
221 
222 //******************************************************************************
223 //
224 // The following are defines for the bit fields in the
225 // APPS_RCM_O_CAMERA_CLK_GEN register.
226 //
227 //******************************************************************************
228 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \
229                                 0x00000700  // Configuration of OFF-TIME for
230                                             // dividing PLL clk (240 MHz) in
231                                             // generation of Camera func-clk :
232                                             // "000" - 1 "001" - 2 "010" - 3
233                                             // "011" - 4 "100" - 5 "101" - 6
234                                             // "110" - 7 "111" - 8
235 
236 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8
237 #define APPS_RCM_CAMERA_CLK_GEN_NU1_M \
238                                 0x000000F8
239 
240 #define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3
241 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \
242                                 0x00000007  // Configuration of ON-TIME for
243                                             // dividing PLL clk (240 MHz) in
244                                             // generation of Camera func-clk :
245                                             // "000" - 1 "001" - 2 "010" - 3
246                                             // "011" - 4 "100" - 5 "101" - 6
247                                             // "110" - 7 "111" - 8
248 
249 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0
250 //******************************************************************************
251 //
252 // The following are defines for the bit fields in the
253 // APPS_RCM_O_CAMERA_CLK_GATING register.
254 //
255 //******************************************************************************
256 #define APPS_RCM_CAMERA_CLK_GATING_NU1_M \
257                                 0x00FE0000
258 
259 #define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17
260 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \
261                                 0x00010000  // 0 - Disable camera clk during
262                                             // deep-sleep mode
263 
264 #define APPS_RCM_CAMERA_CLK_GATING_NU2_M \
265                                 0x0000FE00
266 
267 #define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9
268 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \
269                                 0x00000100  // 1- Enable camera clk during
270                                             // sleep mode ; 0- Disable camera
271                                             // clk during sleep mode
272 
273 #define APPS_RCM_CAMERA_CLK_GATING_NU3_M \
274                                 0x000000FE
275 
276 #define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1
277 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \
278                                 0x00000001  // 1- Enable camera clk during run
279                                             // mode ; 0- Disable camera clk
280                                             // during run mode
281 
282 //******************************************************************************
283 //
284 // The following are defines for the bit fields in the
285 // APPS_RCM_O_CAMERA_SOFT_RESET register.
286 //
287 //******************************************************************************
288 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \
289                                 0x00000002  // 1 - Camera clocks/resets are
290                                             // enabled ; 0 - Camera
291                                             // clocks/resets are disabled
292 
293 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \
294                                 0x00000001  // 1 - Assert reset for Camera-core
295                                             // ; 0 - De-assert reset for
296                                             // Camera-core
297 
298 //******************************************************************************
299 //
300 // The following are defines for the bit fields in the
301 // APPS_RCM_O_MCASP_CLK_GATING register.
302 //
303 //******************************************************************************
304 #define APPS_RCM_MCASP_CLK_GATING_NU1_M \
305                                 0x00FE0000
306 
307 #define APPS_RCM_MCASP_CLK_GATING_NU1_S 17
308 #define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \
309                                 0x00010000  // 0 - Disable MCASP clk during
310                                             // deep-sleep mode
311 
312 #define APPS_RCM_MCASP_CLK_GATING_NU2_M \
313                                 0x0000FE00
314 
315 #define APPS_RCM_MCASP_CLK_GATING_NU2_S 9
316 #define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \
317                                 0x00000100  // 1- Enable MCASP clk during sleep
318                                             // mode ; 0- Disable MCASP clk
319                                             // during sleep mode
320 
321 #define APPS_RCM_MCASP_CLK_GATING_NU3_M \
322                                 0x000000FE
323 
324 #define APPS_RCM_MCASP_CLK_GATING_NU3_S 1
325 #define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \
326                                 0x00000001  // 1- Enable MCASP clk during run
327                                             // mode ; 0- Disable MCASP clk
328                                             // during run mode
329 
330 //******************************************************************************
331 //
332 // The following are defines for the bit fields in the
333 // APPS_RCM_O_MCASP_SOFT_RESET register.
334 //
335 //******************************************************************************
336 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \
337                                 0x00000002  // 1 - MCASP Clocks/resets are
338                                             // enabled ; 0 - MCASP Clocks/resets
339                                             // are disabled
340 
341 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \
342                                 0x00000001  // 1 - Assert reset for MCASP-core
343                                             // ; 0 - De-assert reset for
344                                             // MCASP-core
345 
346 //******************************************************************************
347 //
348 // The following are defines for the bit fields in the
349 // APPS_RCM_O_MMCHS_CLK_GEN register.
350 //
351 //******************************************************************************
352 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \
353                                 0x00000700  // Configuration of OFF-TIME for
354                                             // dividing PLL clk (240 MHz) in
355                                             // generation of MMCHS func-clk :
356                                             // "000" - 1 "001" - 2 "010" - 3
357                                             // "011" - 4 "100" - 5 "101" - 6
358                                             // "110" - 7 "111" - 8
359 
360 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8
361 #define APPS_RCM_MMCHS_CLK_GEN_NU1_M \
362                                 0x000000F8
363 
364 #define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3
365 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \
366                                 0x00000007  // Configuration of ON-TIME for
367                                             // dividing PLL clk (240 MHz) in
368                                             // generation of MMCHS func-clk :
369                                             // "000" - 1 "001" - 2 "010" - 3
370                                             // "011" - 4 "100" - 5 "101" - 6
371                                             // "110" - 7 "111" - 8
372 
373 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0
374 //******************************************************************************
375 //
376 // The following are defines for the bit fields in the
377 // APPS_RCM_O_MMCHS_CLK_GATING register.
378 //
379 //******************************************************************************
380 #define APPS_RCM_MMCHS_CLK_GATING_NU1_M \
381                                 0x00FE0000
382 
383 #define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17
384 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \
385                                 0x00010000  // 0 - Disable MMCHS clk during
386                                             // deep-sleep mode
387 
388 #define APPS_RCM_MMCHS_CLK_GATING_NU2_M \
389                                 0x0000FE00
390 
391 #define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9
392 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \
393                                 0x00000100  // 1- Enable MMCHS clk during sleep
394                                             // mode ; 0- Disable MMCHS clk
395                                             // during sleep mode
396 
397 #define APPS_RCM_MMCHS_CLK_GATING_NU3_M \
398                                 0x000000FE
399 
400 #define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1
401 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \
402                                 0x00000001  // 1- Enable MMCHS clk during run
403                                             // mode ; 0- Disable MMCHS clk
404                                             // during run mode
405 
406 //******************************************************************************
407 //
408 // The following are defines for the bit fields in the
409 // APPS_RCM_O_MMCHS_SOFT_RESET register.
410 //
411 //******************************************************************************
412 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \
413                                 0x00000002  // 1 - MMCHS Clocks/resets are
414                                             // enabled ; 0 - MMCHS Clocks/resets
415                                             // are disabled
416 
417 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \
418                                 0x00000001  // 1 - Assert reset for MMCHS-core
419                                             // ; 0 - De-assert reset for
420                                             // MMCHS-core
421 
422 //******************************************************************************
423 //
424 // The following are defines for the bit fields in the
425 // APPS_RCM_O_MCSPI_A1_CLK_GEN register.
426 //
427 //******************************************************************************
428 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \
429                                 0x00010000  // 0 - XTAL clk is used as baud clk
430                                             // for MCSPI_A1 ; 1 - PLL divclk is
431                                             // used as baud clk for MCSPI_A1.
432 
433 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \
434                                 0x0000F800
435 
436 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11
437 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \
438                                 0x00000700  // Configuration of OFF-TIME for
439                                             // dividing PLL clk (240 MHz) in
440                                             // generation of MCSPI_A1 func-clk :
441                                             // "000" - 1 "001" - 2 "010" - 3
442                                             // "011" - 4 "100" - 5 "101" - 6
443                                             // "110" - 7 "111" - 8
444 
445 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8
446 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \
447                                 0x000000F8
448 
449 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3
450 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \
451                                 0x00000007  // Configuration of ON-TIME for
452                                             // dividing PLL clk (240 MHz) in
453                                             // generation of MCSPI_A1 func-clk :
454                                             // "000" - 1 "001" - 2 "010" - 3
455                                             // "011" - 4 "100" - 5 "101" - 6
456                                             // "110" - 7 "111" - 8
457 
458 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0
459 //******************************************************************************
460 //
461 // The following are defines for the bit fields in the
462 // APPS_RCM_O_MCSPI_A1_CLK_GATING register.
463 //
464 //******************************************************************************
465 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \
466                                 0x00FE0000
467 
468 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17
469 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \
470                                 0x00010000  // 0 - Disable MCSPI_A1 clk during
471                                             // deep-sleep mode
472 
473 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \
474                                 0x0000FE00
475 
476 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9
477 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \
478                                 0x00000100  // 1- Enable MCSPI_A1 clk during
479                                             // sleep mode ; 0- Disable MCSPI_A1
480                                             // clk during sleep mode
481 
482 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \
483                                 0x000000FE
484 
485 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1
486 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \
487                                 0x00000001  // 1- Enable MCSPI_A1 clk during
488                                             // run mode ; 0- Disable MCSPI_A1
489                                             // clk during run mode
490 
491 //******************************************************************************
492 //
493 // The following are defines for the bit fields in the
494 // APPS_RCM_O_MCSPI_A1_SOFT_RESET register.
495 //
496 //******************************************************************************
497 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \
498                                 0x00000002  // 1 - MCSPI_A1 Clocks/Resets are
499                                             // enabled ; 0 - MCSPI_A1
500                                             // Clocks/Resets are disabled
501 
502 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \
503                                 0x00000001  // 1 - Assert reset for
504                                             // MCSPI_A1-core ; 0 - De-assert
505                                             // reset for MCSPI_A1-core
506 
507 //******************************************************************************
508 //
509 // The following are defines for the bit fields in the
510 // APPS_RCM_O_MCSPI_A2_CLK_GEN register.
511 //
512 //******************************************************************************
513 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \
514                                 0x00010000  // 0 - XTAL clk is used as baud-clk
515                                             // for MCSPI_A2 ; 1 - PLL divclk is
516                                             // used as baud-clk for MCSPI_A2
517 
518 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \
519                                 0x0000F800
520 
521 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11
522 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \
523                                 0x00000700  // Configuration of OFF-TIME for
524                                             // dividing PLL clk (240 MHz) in
525                                             // generation of MCSPI_A2 func-clk :
526                                             // "000" - 1 "001" - 2 "010" - 3
527                                             // "011" - 4 "100" - 5 "101" - 6
528                                             // "110" - 7 "111" - 8
529 
530 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8
531 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \
532                                 0x000000F8
533 
534 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3
535 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \
536                                 0x00000007  // Configuration of OFF-TIME for
537                                             // dividing PLL clk (240 MHz) in
538                                             // generation of MCSPI_A2 func-clk :
539                                             // "000" - 1 "001" - 2 "010" - 3
540                                             // "011" - 4 "100" - 5 "101" - 6
541                                             // "110" - 7 "111" - 8
542 
543 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0
544 //******************************************************************************
545 //
546 // The following are defines for the bit fields in the
547 // APPS_RCM_O_MCSPI_A2_CLK_GATING register.
548 //
549 //******************************************************************************
550 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \
551                                 0x00FE0000
552 
553 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17
554 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \
555                                 0x00010000  // 0 - Disable MCSPI_A2 clk during
556                                             // deep-sleep mode
557 
558 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \
559                                 0x0000FE00
560 
561 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9
562 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \
563                                 0x00000100  // 1- Enable MCSPI_A2 clk during
564                                             // sleep mode ; 0- Disable MCSPI_A2
565                                             // clk during sleep mode
566 
567 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \
568                                 0x000000FE
569 
570 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1
571 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \
572                                 0x00000001  // 1- Enable MCSPI_A2 clk during
573                                             // run mode ; 0- Disable MCSPI_A2
574                                             // clk during run mode
575 
576 //******************************************************************************
577 //
578 // The following are defines for the bit fields in the
579 // APPS_RCM_O_MCSPI_A2_SOFT_RESET register.
580 //
581 //******************************************************************************
582 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \
583                                 0x00000002  // 1 - MCSPI_A2 Clocks/Resets are
584                                             // enabled ; 0 - MCSPI_A2
585                                             // Clocks/Resets are disabled
586 
587 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \
588                                 0x00000001  // 1 - Assert reset for
589                                             // MCSPI_A2-core ; 0 - De-assert
590                                             // reset for MCSPI_A2-core
591 
592 //******************************************************************************
593 //
594 // The following are defines for the bit fields in the
595 // APPS_RCM_O_UDMA_A_CLK_GATING register.
596 //
597 //******************************************************************************
598 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \
599                                 0x00010000  // 1 - Enable UDMA_A clk during
600                                             // deep-sleep mode 0 - Disable
601                                             // UDMA_A clk during deep-sleep mode
602                                             // ;
603 
604 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \
605                                 0x0000FE00
606 
607 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9
608 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \
609                                 0x00000100  // 1 - Enable UDMA_A clk during
610                                             // sleep mode 0 - Disable UDMA_A clk
611                                             // during sleep mode ;
612 
613 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \
614                                 0x000000FE
615 
616 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1
617 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \
618                                 0x00000001  // 1 - Enable UDMA_A clk during run
619                                             // mode 0 - Disable UDMA_A clk
620                                             // during run mode ;
621 
622 //******************************************************************************
623 //
624 // The following are defines for the bit fields in the
625 // APPS_RCM_O_UDMA_A_SOFT_RESET register.
626 //
627 //******************************************************************************
628 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \
629                                 0x00000002  // 1 - UDMA_A Clocks/Resets are
630                                             // enabled ; 0 - UDMA_A
631                                             // Clocks/Resets are disabled
632 
633 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \
634                                 0x00000001  // 1 - Assert reset for DMA_A ; 0 -
635                                             // De-assert reset for DMA_A
636 
637 //******************************************************************************
638 //
639 // The following are defines for the bit fields in the
640 // APPS_RCM_O_GPIO_A_CLK_GATING register.
641 //
642 //******************************************************************************
643 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \
644                                 0x00010000  // 1 - Enable GPIO_A clk during
645                                             // deep-sleep mode 0 - Disable
646                                             // GPIO_A clk during deep-sleep mode
647                                             // ;
648 
649 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \
650                                 0x0000FE00
651 
652 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9
653 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \
654                                 0x00000100  // 1 - Enable GPIO_A clk during
655                                             // sleep mode 0 - Disable GPIO_A clk
656                                             // during sleep mode ;
657 
658 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \
659                                 0x000000FE
660 
661 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1
662 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \
663                                 0x00000001  // 1 - Enable GPIO_A clk during run
664                                             // mode 0 - Disable GPIO_A clk
665                                             // during run mode ;
666 
667 //******************************************************************************
668 //
669 // The following are defines for the bit fields in the
670 // APPS_RCM_O_GPIO_A_SOFT_RESET register.
671 //
672 //******************************************************************************
673 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \
674                                 0x00000002  // 1 - GPIO_A Clocks/Resets are
675                                             // enabled ; 0 - GPIO_A
676                                             // Clocks/Resets are disabled
677 
678 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \
679                                 0x00000001  // 1 - Assert reset for GPIO_A ; 0
680                                             // - De-assert reset for GPIO_A
681 
682 //******************************************************************************
683 //
684 // The following are defines for the bit fields in the
685 // APPS_RCM_O_GPIO_B_CLK_GATING register.
686 //
687 //******************************************************************************
688 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \
689                                 0x00010000  // 1 - Enable GPIO_B clk during
690                                             // deep-sleep mode 0 - Disable
691                                             // GPIO_B clk during deep-sleep mode
692                                             // ;
693 
694 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \
695                                 0x0000FE00
696 
697 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9
698 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \
699                                 0x00000100  // 1 - Enable GPIO_B clk during
700                                             // sleep mode 0 - Disable GPIO_B clk
701                                             // during sleep mode ;
702 
703 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \
704                                 0x000000FE
705 
706 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1
707 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \
708                                 0x00000001  // 1 - Enable GPIO_B clk during run
709                                             // mode 0 - Disable GPIO_B clk
710                                             // during run mode ;
711 
712 //******************************************************************************
713 //
714 // The following are defines for the bit fields in the
715 // APPS_RCM_O_GPIO_B_SOFT_RESET register.
716 //
717 //******************************************************************************
718 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \
719                                 0x00000002  // 1 - GPIO_B Clocks/Resets are
720                                             // enabled ; 0 - GPIO_B
721                                             // Clocks/Resets are disabled
722 
723 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \
724                                 0x00000001  // 1 - Assert reset for GPIO_B ; 0
725                                             // - De-assert reset for GPIO_B
726 
727 //******************************************************************************
728 //
729 // The following are defines for the bit fields in the
730 // APPS_RCM_O_GPIO_C_CLK_GATING register.
731 //
732 //******************************************************************************
733 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \
734                                 0x00010000  // 1 - Enable GPIO_C clk during
735                                             // deep-sleep mode 0 - Disable
736                                             // GPIO_C clk during deep-sleep mode
737                                             // ;
738 
739 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \
740                                 0x0000FE00
741 
742 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9
743 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \
744                                 0x00000100  // 1 - Enable GPIO_C clk during
745                                             // sleep mode 0 - Disable GPIO_C clk
746                                             // during sleep mode ;
747 
748 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \
749                                 0x000000FE
750 
751 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1
752 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \
753                                 0x00000001  // 1 - Enable GPIO_C clk during run
754                                             // mode 0 - Disable GPIO_C clk
755                                             // during run mode ;
756 
757 //******************************************************************************
758 //
759 // The following are defines for the bit fields in the
760 // APPS_RCM_O_GPIO_C_SOFT_RESET register.
761 //
762 //******************************************************************************
763 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \
764                                 0x00000002  // 1 - GPIO_C Clocks/Resets are
765                                             // enabled ; 0 - GPIO_C
766                                             // Clocks/Resets are disabled
767 
768 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \
769                                 0x00000001  // 1 - Assert reset for GPIO_C ; 0
770                                             // - De-assert reset for GPIO_C
771 
772 //******************************************************************************
773 //
774 // The following are defines for the bit fields in the
775 // APPS_RCM_O_GPIO_D_CLK_GATING register.
776 //
777 //******************************************************************************
778 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \
779                                 0x00010000  // 1 - Enable GPIO_D clk during
780                                             // deep-sleep mode 0 - Disable
781                                             // GPIO_D clk during deep-sleep mode
782                                             // ;
783 
784 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \
785                                 0x0000FE00
786 
787 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9
788 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \
789                                 0x00000100  // 1 - Enable GPIO_D clk during
790                                             // sleep mode 0 - Disable GPIO_D clk
791                                             // during sleep mode ;
792 
793 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \
794                                 0x000000FE
795 
796 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1
797 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \
798                                 0x00000001  // 1 - Enable GPIO_D clk during run
799                                             // mode 0 - Disable GPIO_D clk
800                                             // during run mode ;
801 
802 //******************************************************************************
803 //
804 // The following are defines for the bit fields in the
805 // APPS_RCM_O_GPIO_D_SOFT_RESET register.
806 //
807 //******************************************************************************
808 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \
809                                 0x00000002  // 1 - GPIO_D Clocks/Resets are
810                                             // enabled ; 0 - GPIO_D
811                                             // Clocks/Resets are disabled
812 
813 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \
814                                 0x00000001  // 1 - Assert reset for GPIO_D ; 0
815                                             // - De-assert reset for GPIO_D
816 
817 //******************************************************************************
818 //
819 // The following are defines for the bit fields in the
820 // APPS_RCM_O_GPIO_E_CLK_GATING register.
821 //
822 //******************************************************************************
823 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \
824                                 0x00010000  // 1 - Enable GPIO_E clk during
825                                             // deep-sleep mode 0 - Disable
826                                             // GPIO_E clk during deep-sleep mode
827                                             // ;
828 
829 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \
830                                 0x0000FE00
831 
832 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9
833 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \
834                                 0x00000100  // 1 - Enable GPIO_E clk during
835                                             // sleep mode 0 - Disable GPIO_E clk
836                                             // during sleep mode ;
837 
838 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \
839                                 0x000000FE
840 
841 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1
842 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \
843                                 0x00000001  // 1 - Enable GPIO_E clk during run
844                                             // mode 0 - Disable GPIO_E clk
845                                             // during run mode ;
846 
847 //******************************************************************************
848 //
849 // The following are defines for the bit fields in the
850 // APPS_RCM_O_GPIO_E_SOFT_RESET register.
851 //
852 //******************************************************************************
853 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \
854                                 0x00000002  // 1 - GPIO_E Clocks/Resets are
855                                             // enabled ; 0 - GPIO_E
856                                             // Clocks/Resets are disabled
857 
858 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \
859                                 0x00000001  // 1 - Assert reset for GPIO_E ; 0
860                                             // - De-assert reset for GPIO_E
861 
862 //******************************************************************************
863 //
864 // The following are defines for the bit fields in the
865 // APPS_RCM_O_WDOG_A_CLK_GATING register.
866 //
867 //******************************************************************************
868 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \
869                                 0x03000000  // "00" - Sysclk ; "01" - REF_CLK
870                                             // (38.4 MHz) ; "10/11" - Slow_clk
871 
872 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24
873 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \
874                                 0x00010000  // 1 - Enable WDOG_A clk during
875                                             // deep-sleep mode 0 - Disable
876                                             // WDOG_A clk during deep-sleep mode
877                                             // ;
878 
879 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \
880                                 0x0000FE00
881 
882 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9
883 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \
884                                 0x00000100  // 1 - Enable WDOG_A clk during
885                                             // sleep mode 0 - Disable WDOG_A clk
886                                             // during sleep mode ;
887 
888 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \
889                                 0x000000FE
890 
891 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1
892 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \
893                                 0x00000001  // 1 - Enable WDOG_A clk during run
894                                             // mode 0 - Disable WDOG_A clk
895                                             // during run mode ;
896 
897 //******************************************************************************
898 //
899 // The following are defines for the bit fields in the
900 // APPS_RCM_O_WDOG_A_SOFT_RESET register.
901 //
902 //******************************************************************************
903 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \
904                                 0x00000002  // 1 - WDOG_A Clocks/Resets are
905                                             // enabled ; 0 - WDOG_A
906                                             // Clocks/Resets are disabled
907 
908 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \
909                                 0x00000001  // 1 - Assert reset for WDOG_A ; 0
910                                             // - De-assert reset for WDOG_A
911 
912 //******************************************************************************
913 //
914 // The following are defines for the bit fields in the
915 // APPS_RCM_O_UART_A0_CLK_GATING register.
916 //
917 //******************************************************************************
918 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \
919                                 0x00010000  // 1 - Enable UART_A0 clk during
920                                             // deep-sleep mode 0 - Disable
921                                             // UART_A0 clk during deep-sleep
922                                             // mode ;
923 
924 #define APPS_RCM_UART_A0_CLK_GATING_NU1_M \
925                                 0x0000FE00
926 
927 #define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9
928 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \
929                                 0x00000100  // 1 - Enable UART_A0 clk during
930                                             // sleep mode 0 - Disable UART_A0
931                                             // clk during sleep mode ;
932 
933 #define APPS_RCM_UART_A0_CLK_GATING_NU2_M \
934                                 0x000000FE
935 
936 #define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1
937 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \
938                                 0x00000001  // 1 - Enable UART_A0 clk during
939                                             // run mode 0 - Disable UART_A0 clk
940                                             // during run mode ;
941 
942 //******************************************************************************
943 //
944 // The following are defines for the bit fields in the
945 // APPS_RCM_O_UART_A0_SOFT_RESET register.
946 //
947 //******************************************************************************
948 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \
949                                 0x00000002  // 1 - UART_A0 Clocks/Resets are
950                                             // enabled ; 0 - UART_A0
951                                             // Clocks/Resets are disabled
952 
953 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \
954                                 0x00000001  // 1 - Assert reset for UART_A0 ; 0
955                                             // - De-assert reset for UART_A0
956 
957 //******************************************************************************
958 //
959 // The following are defines for the bit fields in the
960 // APPS_RCM_O_UART_A1_CLK_GATING register.
961 //
962 //******************************************************************************
963 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \
964                                 0x00010000  // 1 - Enable UART_A1 clk during
965                                             // deep-sleep mode 0 - Disable
966                                             // UART_A1 clk during deep-sleep
967                                             // mode ;
968 
969 #define APPS_RCM_UART_A1_CLK_GATING_NU1_M \
970                                 0x0000FE00
971 
972 #define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9
973 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \
974                                 0x00000100  // 1 - Enable UART_A1 clk during
975                                             // sleep mode 0 - Disable UART_A1
976                                             // clk during sleep mode ;
977 
978 #define APPS_RCM_UART_A1_CLK_GATING_NU2_M \
979                                 0x000000FE
980 
981 #define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1
982 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \
983                                 0x00000001  // 1 - Enable UART_A1 clk during
984                                             // run mode 0 - Disable UART_A1 clk
985                                             // during run mode ;
986 
987 //******************************************************************************
988 //
989 // The following are defines for the bit fields in the
990 // APPS_RCM_O_UART_A1_SOFT_RESET register.
991 //
992 //******************************************************************************
993 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \
994                                 0x00000002  // 1 - UART_A1 Clocks/Resets are
995                                             // enabled ; 0 - UART_A1
996                                             // Clocks/Resets are disabled
997 
998 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \
999                                 0x00000001  // 1 - Assert the soft reset for
1000                                             // UART_A1 ; 0 - De-assert the soft
1001                                             // reset for UART_A1
1002 
1003 //******************************************************************************
1004 //
1005 // The following are defines for the bit fields in the
1006 // APPS_RCM_O_GPT_A0_CLK_GATING register.
1007 //
1008 //******************************************************************************
1009 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \
1010                                 0x00010000  // 1 - Enable the GPT_A0 clock
1011                                             // during deep-sleep ; 0 - Disable
1012                                             // the GPT_A0 clock during
1013                                             // deep-sleep
1014 
1015 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \
1016                                 0x0000FE00
1017 
1018 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9
1019 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \
1020                                 0x00000100  // 1 - Enable the GPT_A0 clock
1021                                             // during sleep ; 0 - Disable the
1022                                             // GPT_A0 clock during sleep
1023 
1024 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \
1025                                 0x000000FE
1026 
1027 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1
1028 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \
1029                                 0x00000001  // 1 - Enable the GPT_A0 clock
1030                                             // during run ; 0 - Disable the
1031                                             // GPT_A0 clock during run
1032 
1033 //******************************************************************************
1034 //
1035 // The following are defines for the bit fields in the
1036 // APPS_RCM_O_GPT_A0_SOFT_RESET register.
1037 //
1038 //******************************************************************************
1039 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \
1040                                 0x00000002  // 1 - GPT_A0 clocks/resets are
1041                                             // enabled ; 0 - GPT_A0
1042                                             // clocks/resets are disabled
1043 
1044 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \
1045                                 0x00000001  // 1 - Assert the soft reset for
1046                                             // GPT_A0 ; 0 - De-assert the soft
1047                                             // reset for GPT_A0
1048 
1049 //******************************************************************************
1050 //
1051 // The following are defines for the bit fields in the
1052 // APPS_RCM_O_GPT_A1_CLK_GATING register.
1053 //
1054 //******************************************************************************
1055 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \
1056                                 0x00010000  // 1 - Enable the GPT_A1 clock
1057                                             // during deep-sleep ; 0 - Disable
1058                                             // the GPT_A1 clock during
1059                                             // deep-sleep
1060 
1061 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \
1062                                 0x0000FE00
1063 
1064 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9
1065 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \
1066                                 0x00000100  // 1 - Enable the GPT_A1 clock
1067                                             // during sleep ; 0 - Disable the
1068                                             // GPT_A1 clock during sleep
1069 
1070 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \
1071                                 0x000000FE
1072 
1073 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1
1074 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \
1075                                 0x00000001  // 1 - Enable the GPT_A1 clock
1076                                             // during run ; 0 - Disable the
1077                                             // GPT_A1 clock during run
1078 
1079 //******************************************************************************
1080 //
1081 // The following are defines for the bit fields in the
1082 // APPS_RCM_O_GPT_A1_SOFT_RESET register.
1083 //
1084 //******************************************************************************
1085 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \
1086                                 0x00000002  // 1 - GPT_A1 clocks/resets are
1087                                             // enabled ; 0 - GPT_A1
1088                                             // clocks/resets are disabled
1089 
1090 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \
1091                                 0x00000001  // 1 - Assert the soft reset for
1092                                             // GPT_A1 ; 0 - De-assert the soft
1093                                             // reset for GPT_A1
1094 
1095 //******************************************************************************
1096 //
1097 // The following are defines for the bit fields in the
1098 // APPS_RCM_O_GPT_A2_CLK_GATING register.
1099 //
1100 //******************************************************************************
1101 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \
1102                                 0x00010000  // 1 - Enable the GPT_A2 clock
1103                                             // during deep-sleep ; 0 - Disable
1104                                             // the GPT_A2 clock during
1105                                             // deep-sleep
1106 
1107 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \
1108                                 0x0000FE00
1109 
1110 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9
1111 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \
1112                                 0x00000100  // 1 - Enable the GPT_A2 clock
1113                                             // during sleep ; 0 - Disable the
1114                                             // GPT_A2 clock during sleep
1115 
1116 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \
1117                                 0x000000FE
1118 
1119 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1
1120 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \
1121                                 0x00000001  // 1 - Enable the GPT_A2 clock
1122                                             // during run ; 0 - Disable the
1123                                             // GPT_A2 clock during run
1124 
1125 //******************************************************************************
1126 //
1127 // The following are defines for the bit fields in the
1128 // APPS_RCM_O_GPT_A2_SOFT_RESET register.
1129 //
1130 //******************************************************************************
1131 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \
1132                                 0x00000002  // 1 - GPT_A2 clocks/resets are
1133                                             // enabled ; 0 - GPT_A2
1134                                             // clocks/resets are disabled
1135 
1136 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \
1137                                 0x00000001  // 1 - Assert the soft reset for
1138                                             // GPT_A2 ; 0 - De-assert the soft
1139                                             // reset for GPT_A2
1140 
1141 //******************************************************************************
1142 //
1143 // The following are defines for the bit fields in the
1144 // APPS_RCM_O_GPT_A3_CLK_GATING register.
1145 //
1146 //******************************************************************************
1147 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \
1148                                 0x00010000  // 1 - Enable the GPT_A3 clock
1149                                             // during deep-sleep ; 0 - Disable
1150                                             // the GPT_A3 clock during
1151                                             // deep-sleep
1152 
1153 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \
1154                                 0x0000FE00
1155 
1156 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9
1157 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \
1158                                 0x00000100  // 1 - Enable the GPT_A3 clock
1159                                             // during sleep ; 0 - Disable the
1160                                             // GPT_A3 clock during sleep
1161 
1162 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \
1163                                 0x000000FE
1164 
1165 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1
1166 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \
1167                                 0x00000001  // 1 - Enable the GPT_A3 clock
1168                                             // during run ; 0 - Disable the
1169                                             // GPT_A3 clock during run
1170 
1171 //******************************************************************************
1172 //
1173 // The following are defines for the bit fields in the
1174 // APPS_RCM_O_GPT_A3_SOFT_RESET register.
1175 //
1176 //******************************************************************************
1177 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \
1178                                 0x00000002  // 1 - GPT_A3 Clocks/resets are
1179                                             // enabled ; 0 - GPT_A3
1180                                             // Clocks/resets are disabled
1181 
1182 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \
1183                                 0x00000001  // 1 - Assert the soft reset for
1184                                             // GPT_A3 ; 0 - De-assert the soft
1185                                             // reset for GPT_A3
1186 
1187 //******************************************************************************
1188 //
1189 // The following are defines for the bit fields in the
1190 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register.
1191 //
1192 //******************************************************************************
1193 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \
1194                                 0x03FF0000
1195 
1196 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16
1197 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \
1198                                 0x0000FFFF
1199 
1200 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0
1201 //******************************************************************************
1202 //
1203 // The following are defines for the bit fields in the
1204 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register.
1205 //
1206 //******************************************************************************
1207 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \
1208                                 0x00010000  // 1 - Assert the reset for MCASP
1209                                             // Frac-clk div; 0 - Donot assert
1210                                             // the reset for MCASP frac clk-div
1211 
1212 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \
1213                                 0x000003FF
1214 
1215 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0
1216 //******************************************************************************
1217 //
1218 // The following are defines for the bit fields in the
1219 // APPS_RCM_O_CRYPTO_CLK_GATING register.
1220 //
1221 //******************************************************************************
1222 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \
1223                                 0x00010000  // 0 - Disable the Crypto clock
1224                                             // during deep-sleep
1225 
1226 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \
1227                                 0x0000FE00
1228 
1229 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9
1230 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \
1231                                 0x00000100  // 1 - Enable the Crypto clock
1232                                             // during sleep ; 0 - Disable the
1233                                             // Crypto clock during sleep
1234 
1235 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \
1236                                 0x000000FE
1237 
1238 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1
1239 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \
1240                                 0x00000001  // 1 - Enable the Crypto clock
1241                                             // during run ; 0 - Disable the
1242                                             // Crypto clock during run
1243 
1244 //******************************************************************************
1245 //
1246 // The following are defines for the bit fields in the
1247 // APPS_RCM_O_CRYPTO_SOFT_RESET register.
1248 //
1249 //******************************************************************************
1250 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \
1251                                 0x00000002  // 1 - Crypto clocks/resets are
1252                                             // enabled ; 0 - Crypto
1253                                             // clocks/resets are disabled
1254 
1255 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \
1256                                 0x00000001  // 1 - Assert the soft reset for
1257                                             // Crypto ; 0 - De-assert the soft
1258                                             // reset for Crypto
1259 
1260 //******************************************************************************
1261 //
1262 // The following are defines for the bit fields in the
1263 // APPS_RCM_O_MCSPI_S0_CLK_GATING register.
1264 //
1265 //******************************************************************************
1266 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \
1267                                 0x00010000  // 0 - Disable the MCSPI_S0 clock
1268                                             // during deep-sleep
1269 
1270 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \
1271                                 0x0000FE00
1272 
1273 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9
1274 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \
1275                                 0x00000100  // 1 - Enable the MCSPI_S0 clock
1276                                             // during sleep ; 0 - Disable the
1277                                             // MCSPI_S0 clock during sleep
1278 
1279 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \
1280                                 0x000000FE
1281 
1282 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1
1283 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \
1284                                 0x00000001  // 1 - Enable the MCSPI_S0 clock
1285                                             // during run ; 0 - Disable the
1286                                             // MCSPI_S0 clock during run
1287 
1288 //******************************************************************************
1289 //
1290 // The following are defines for the bit fields in the
1291 // APPS_RCM_O_MCSPI_S0_SOFT_RESET register.
1292 //
1293 //******************************************************************************
1294 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \
1295                                 0x00000002  // 1 - MCSPI_S0 Clocks/Resets are
1296                                             // enabled ; 0 - MCSPI_S0
1297                                             // Clocks/resets are disabled
1298 
1299 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \
1300                                 0x00000001  // 1 - Assert the soft reset for
1301                                             // MCSPI_S0 ; 0 - De-assert the soft
1302                                             // reset for MCSPI_S0
1303 
1304 //******************************************************************************
1305 //
1306 // The following are defines for the bit fields in the
1307 // APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register.
1308 //
1309 //******************************************************************************
1310 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \
1311                                 0x00010000  // 0 - XTAL clk is used as baud-clk
1312                                             // for MCSPI_S0 ; 1 - PLL divclk is
1313                                             // used as buad-clk for MCSPI_S0
1314 
1315 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \
1316                                 0x0000F800
1317 
1318 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11
1319 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \
1320                                 0x00000700  // Configuration of OFF-TIME for
1321                                             // dividing PLL clk (240 MHz) in
1322                                             // generation of MCSPI_S0 func-clk :
1323                                             // "000" - 1 "001" - 2 "010" - 3
1324                                             // "011" - 4 "100" - 5 "101" - 6
1325                                             // "110" - 7 "111" - 8
1326 
1327 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8
1328 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \
1329                                 0x000000F8
1330 
1331 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3
1332 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \
1333                                 0x00000007  // Configuration of ON-TIME for
1334                                             // dividing PLL clk (240 MHz) in
1335                                             // generation of MCSPI_S0 func-clk :
1336                                             // "000" - 1 "001" - 2 "010" - 3
1337                                             // "011" - 4 "100" - 5 "101" - 6
1338                                             // "110" - 7 "111" - 8
1339 
1340 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0
1341 //******************************************************************************
1342 //
1343 // The following are defines for the bit fields in the
1344 // APPS_RCM_O_I2C_CLK_GATING register.
1345 //
1346 //******************************************************************************
1347 #define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \
1348                                 0x00010000  // 1 - Enable the I2C Clock during
1349                                             // deep-sleep 0 - Disable the I2C
1350                                             // clock during deep-sleep
1351 
1352 #define APPS_RCM_I2C_CLK_GATING_NU1_M \
1353                                 0x0000FE00
1354 
1355 #define APPS_RCM_I2C_CLK_GATING_NU1_S 9
1356 #define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \
1357                                 0x00000100  // 1 - Enable the I2C clock during
1358                                             // sleep ; 0 - Disable the I2C clock
1359                                             // during sleep
1360 
1361 #define APPS_RCM_I2C_CLK_GATING_NU2_M \
1362                                 0x000000FE
1363 
1364 #define APPS_RCM_I2C_CLK_GATING_NU2_S 1
1365 #define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \
1366                                 0x00000001  // 1 - Enable the I2C clock during
1367                                             // run ; 0 - Disable the I2C clock
1368                                             // during run
1369 
1370 //******************************************************************************
1371 //
1372 // The following are defines for the bit fields in the
1373 // APPS_RCM_O_I2C_SOFT_RESET register.
1374 //
1375 //******************************************************************************
1376 #define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \
1377                                 0x00000002  // 1 - I2C Clocks/Resets are
1378                                             // enabled ; 0 - I2C clocks/resets
1379                                             // are disabled
1380 
1381 #define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \
1382                                 0x00000001  // 1 - Assert the soft reset for
1383                                             // Shared-I2C ; 0 - De-assert the
1384                                             // soft reset for Shared-I2C
1385 
1386 //******************************************************************************
1387 //
1388 // The following are defines for the bit fields in the
1389 // APPS_RCM_O_APPS_LPDS_REQ register.
1390 //
1391 //******************************************************************************
1392 #define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \
1393                                 0x00000001  // 1 - Request for LPDS
1394 
1395 //******************************************************************************
1396 //
1397 // The following are defines for the bit fields in the
1398 // APPS_RCM_O_APPS_TURBO_REQ register.
1399 //
1400 //******************************************************************************
1401 #define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \
1402                                 0x00000001  // 1 - Request for TURBO
1403 
1404 //******************************************************************************
1405 //
1406 // The following are defines for the bit fields in the
1407 // APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register.
1408 //
1409 //******************************************************************************
1410 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \
1411                                 0x00000002  // 1 - Enable the NWP to wake APPS
1412                                             // from deep-sleep ; 0 - Disable NWP
1413                                             // to wake APPS from deep-sleep
1414 
1415 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \
1416                                 0x00000001  // 1 - Enable deep-sleep wake timer
1417                                             // in APPS RCM for deep-sleep; 0 -
1418                                             // Disable deep-sleep wake timer in
1419                                             // APPS RCM
1420 
1421 //******************************************************************************
1422 //
1423 // The following are defines for the bit fields in the
1424 // APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register.
1425 //
1426 //******************************************************************************
1427 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \
1428                                 0xFFFF0000  // Configuration (in slow_clks)
1429                                             // which says when to request for
1430                                             // OPP during deep-sleep exit
1431 
1432 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16
1433 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \
1434                                 0x0000FFFF  // Configuration (in slow_clks)
1435                                             // which says when to request for
1436                                             // WAKE during deep-sleep exit
1437 
1438 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0
1439 //******************************************************************************
1440 //
1441 // The following are defines for the bit fields in the
1442 // APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register.
1443 //
1444 //******************************************************************************
1445 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \
1446                                 0x00000002  // 1- Enable the sleep wakeup due
1447                                             // to NWP request. 0- Disable the
1448                                             // sleep wakeup due to NWP request
1449 
1450 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \
1451                                 0x00000001  // 1- Enable the sleep wakeup due
1452                                             // to sleep-timer; 0-Disable the
1453                                             // sleep wakeup due to sleep-timer
1454 
1455 //******************************************************************************
1456 //
1457 // The following are defines for the bit fields in the
1458 // APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register.
1459 //
1460 //******************************************************************************
1461 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \
1462                                 0xFFFFFFFF  // Configuration (number of
1463                                             // sysclks-80MHz) for the Sleep
1464                                             // wakeup timer
1465 
1466 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0
1467 //******************************************************************************
1468 //
1469 // The following are defines for the bit fields in the
1470 // APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register.
1471 //
1472 //******************************************************************************
1473 #define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \
1474                                 0x00000001  // When 1 => APPS generated a wake
1475                                             // request to NWP (When NWP is in
1476                                             // any of its low-power modes :
1477                                             // SLP/DSLP/LPDS)
1478 
1479 //******************************************************************************
1480 //
1481 // The following are defines for the bit fields in the
1482 // APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register.
1483 //
1484 //******************************************************************************
1485 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \
1486                                 0x00000008  // 1 - Indicates that deep-sleep
1487                                             // timer expiry had caused the
1488                                             // wakeup from deep-sleep
1489 
1490 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \
1491                                 0x00000004  // 1 - Indicates that sleep timer
1492                                             // expiry had caused the wakeup from
1493                                             // sleep
1494 
1495 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \
1496                                 0x00000002  // 1 - Indicates that NWP had
1497                                             // caused the wakeup from deep-sleep
1498 
1499 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \
1500                                 0x00000001  // 1 - Indicates that NWP had
1501                                             // caused the wakeup from Sleep
1502 
1503 
1504 
1505 
1506 #endif // __HW_APPS_RCM_H__
1507