1 /*
2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14  * PERFORMANCE OF THIS SOFTWARE.
15  */
16 #include "opt_ah.h"
17 
18 //#ifdef AH_SUPPORT_AR9300
19 
20 #include "ah.h"
21 #include "ah_desc.h"
22 #include "ah_internal.h"
23 
24 #include "ar9300_freebsd_inc.h"
25 
26 #include "ar9300/ar9300phy.h"
27 #include "ar9300/ar9300.h"
28 #include "ar9300/ar9300reg.h"
29 #include "ar9300/ar9300desc.h"
30 
31 #if ATH_SUPPORT_SPECTRAL
32 
33 /*
34  * Default 9300 spectral scan parameters
35  */
36 #define AR9300_SPECTRAL_SCAN_ENA                0
37 #define AR9300_SPECTRAL_SCAN_ACTIVE             0
38 #define AR9300_SPECTRAL_SCAN_FFT_PERIOD         8
39 #define AR9300_SPECTRAL_SCAN_PERIOD             1
40 #define AR9300_SPECTRAL_SCAN_COUNT              16 /* used to be 128 */
41 #define AR9300_SPECTRAL_SCAN_SHORT_REPEAT       1
42 
43 /* constants */
44 #define MAX_RADAR_DC_PWR_THRESH 127
45 #define MAX_RADAR_RSSI_THRESH 0x3f
46 #define MAX_RADAR_HEIGHT 0x3f
47 #define MAX_CCA_THRESH 127
48 #define ENABLE_ALL_PHYERR 0xffffffff
49 
50 void ar9300_disable_cck(struct ath_hal *ah);
51 void ar9300_disable_radar(struct ath_hal *ah);
52 void ar9300_disable_restart(struct ath_hal *ah);
53 void ar9300_set_radar_dc_thresh(struct ath_hal *ah);
54 void ar9300_disable_weak_signal(struct ath_hal *ah);
55 void ar9300_disable_strong_signal(struct ath_hal *ah);
56 void ar9300_prep_spectral_scan(struct ath_hal *ah);
57 void ar9300_disable_dc_offset(struct ath_hal *ah);
58 void ar9300_enable_cck_detect(struct ath_hal *ah);
59 
60 void
ar9300_disable_cck(struct ath_hal * ah)61 ar9300_disable_cck(struct ath_hal *ah)
62 {
63     u_int32_t val;
64 
65     val = OS_REG_READ(ah, AR_PHY_MODE);
66     val &= ~(AR_PHY_MODE_DYN_CCK_DISABLE);
67 
68     OS_REG_WRITE(ah, AR_PHY_MODE, val);
69 }
70 
71 void
ar9300_disable_radar(struct ath_hal * ah)72 ar9300_disable_radar(struct ath_hal *ah)
73 {
74     u_int32_t val;
75 
76     /* Enable radar FFT */
77     val = OS_REG_READ(ah, AR_PHY_RADAR_0);
78     val |= AR_PHY_RADAR_0_FFT_ENA;
79 
80     /* set radar detect thresholds to max to effectively disable radar */
81     val &= ~AR_PHY_RADAR_0_RRSSI;
82     val |= SM(MAX_RADAR_RSSI_THRESH, AR_PHY_RADAR_0_RRSSI);
83 
84     val &= ~AR_PHY_RADAR_0_HEIGHT;
85     val |= SM(MAX_RADAR_HEIGHT, AR_PHY_RADAR_0_HEIGHT);
86 
87     val &= ~(AR_PHY_RADAR_0_ENA);
88     OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
89 
90     /* disable extension radar detect */
91     val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
92     OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
93 
94     val = OS_REG_READ(ah, AR_RX_FILTER);
95     val |= (1 << 13);
96     OS_REG_WRITE(ah, AR_RX_FILTER, val);
97 }
98 
ar9300_disable_restart(struct ath_hal * ah)99 void ar9300_disable_restart(struct ath_hal *ah)
100 {
101     u_int32_t val;
102     val = OS_REG_READ(ah, AR_PHY_RESTART);
103     val &= ~AR_PHY_RESTART_ENA;
104     OS_REG_WRITE(ah, AR_PHY_RESTART, val);
105 
106     val = OS_REG_READ(ah, AR_PHY_RESTART);
107 }
108 
ar9300_set_radar_dc_thresh(struct ath_hal * ah)109 void ar9300_set_radar_dc_thresh(struct ath_hal *ah)
110 {
111     u_int32_t val;
112     val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
113     val &= ~AR_PHY_RADAR_DC_PWR_THRESH;
114     val |= SM(MAX_RADAR_DC_PWR_THRESH, AR_PHY_RADAR_DC_PWR_THRESH);
115     OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val);
116 
117     val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
118 }
119 
120 void
ar9300_disable_weak_signal(struct ath_hal * ah)121 ar9300_disable_weak_signal(struct ath_hal *ah)
122 {
123     /* set firpwr to max (signed) */
124     OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, 0x7f);
125     OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT);
126 
127     /* set firstep to max */
128     OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, 0x3f);
129 
130     /* set relpwr to max (signed) */
131     OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR, 0x1f);
132     OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELPWR_SIGN_BIT);
133 
134     /* set relstep to max (signed) */
135     OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP, 0x1f);
136     OS_REG_CLR_BIT(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT);
137 
138     /* set firpwr_low to max (signed) */
139     OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR, 0x7f);
140     OS_REG_CLR_BIT(
141         ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT);
142 
143     /* set firstep_low to max */
144     OS_REG_RMW_FIELD(
145         ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, 0x3f);
146 
147     /* set relstep_low to max (signed) */
148     OS_REG_RMW_FIELD(
149         ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP, 0x1f);
150     OS_REG_CLR_BIT(
151         ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT);
152 }
153 
154 void
ar9300_disable_strong_signal(struct ath_hal * ah)155 ar9300_disable_strong_signal(struct ath_hal *ah)
156 {
157     u_int32_t val;
158 
159     val = OS_REG_READ(ah, AR_PHY_TIMING5);
160     val |= AR_PHY_TIMING5_RSSI_THR1A_ENA;
161     OS_REG_WRITE(ah, AR_PHY_TIMING5, val);
162 
163     OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_RSSI_THR1A, 0x7f);
164 
165 }
166 void
ar9300_set_cca_threshold(struct ath_hal * ah,u_int8_t thresh62)167 ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62)
168 {
169     OS_REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, thresh62);
170     OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, thresh62);
171     /*
172     OS_REG_RMW_FIELD(ah,
173         AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, thresh62);
174      */
175     OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, thresh62);
176 }
177 
ar9300_classify_strong_bins(struct ath_hal * ah)178 static void ar9300_classify_strong_bins(struct ath_hal *ah)
179 {
180     OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH, 0x1);
181 }
182 
ar9300_disable_dc_offset(struct ath_hal * ah)183 void ar9300_disable_dc_offset(struct ath_hal *ah)
184 {
185     OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET, 0);
186 }
187 
ar9300_enable_cck_detect(struct ath_hal * ah)188 void ar9300_enable_cck_detect(struct ath_hal *ah)
189 {
190     OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK, 0);
191     OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, 1);
192 }
193 
ar9300_prep_spectral_scan(struct ath_hal * ah)194 void ar9300_prep_spectral_scan(struct ath_hal *ah)
195 {
196     ar9300_disable_radar(ah);
197     ar9300_classify_strong_bins(ah);
198     ar9300_disable_dc_offset(ah);
199     if (AH_PRIVATE(ah)->ah_curchan &&
200         IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan))
201     { /* fast clock */
202         ar9300_enable_cck_detect(ah);
203     }
204 #ifdef DEMO_MODE
205     ar9300_disable_strong_signal(ah);
206     ar9300_disable_weak_signal(ah);
207     ar9300_set_radar_dc_thresh(ah);
208     ar9300_set_cca_threshold(ah, MAX_CCA_THRESH);
209     /*ar9300_disable_restart(ah);*/
210 #endif
211     OS_REG_WRITE(ah, AR_PHY_ERR, HAL_PHYERR_SPECTRAL);
212 }
213 
214 
215 //#define TEST_NOISE_PWR_WITHOUT_EEPROM 1
216 #ifdef TEST_NOISE_PWR_WITHOUT_EEPROM
217 struct nf_cal {
218     int cal;
219     int pwr;
220 };
221 struct nf_cal_table_t {
222     int freq;
223     struct nf_cal chain[AH_MAX_CHAINS];
224 };
225 
226 static const struct nf_cal_table_t nf_cal_table[] =
227 {
228 /* ch 1  */ {2412, { {N2DBM(-101, 00),  N2DBM( -94, 25)},
229                      {N2DBM(-107, 75),  N2DBM( -99, 75)},
230                    } },
231 /* ch 6  */ {2437, { {N2DBM(-102, 25),  N2DBM( -94, 25)},
232                      {N2DBM(-106, 00),  N2DBM( -97, 25)},
233                    } },
234 /* ch 11 */ {2462, { {N2DBM(-101, 50),  N2DBM( -95, 00)},
235                      {N2DBM(-105, 50),  N2DBM( -98, 00)},
236                    } },
237 /* ch 36 */ {5180, { {N2DBM(-114, 25),  N2DBM( -95, 00)},
238                      {N2DBM(-114, 75),  N2DBM( -94, 00)},
239                    } },
240 /* ch 44 */ {5220, { {N2DBM(-113, 00),  N2DBM( -95, 00)},
241                      {N2DBM(-115, 00),  N2DBM( -94, 50)},
242                    } },
243 /* ch 64 */ {5320, { {N2DBM(-113, 00),  N2DBM( -95, 00)}, // not cal'ed
244                      {N2DBM(-115, 00),  N2DBM( -94, 50)},
245                    } },
246 /* ch 100*/ {5500, { {N2DBM(-111, 50),  N2DBM( -93, 75)},
247                      {N2DBM(-112, 00),  N2DBM( -95, 25)},
248                    } },
249 /* ch 120*/ {5600, { {N2DBM(-111, 50),  N2DBM( -93, 75)},
250                      {N2DBM(-112, 00),  N2DBM( -95, 25)},
251                    } },
252 /* ch 140*/ {5700, { {N2DBM(-111, 75),  N2DBM( -95, 00)},
253                      {N2DBM(-111, 75),  N2DBM( -96, 00)},
254                    } },
255 /* ch 157*/ {5785, { {N2DBM(-112, 50),  N2DBM( -94, 75)},
256                      {N2DBM(-111, 75),  N2DBM( -95, 50)},
257                    } },
258 /* ch 165*/ {5825, { {N2DBM(-111, 50),  N2DBM( -95, 00)},
259                      {N2DBM(-112, 00),  N2DBM( -95, 00)},
260                    } },
261                    {0}
262 };
263 
264 static int
ar9300_noise_floor_get(struct ath_hal * ah,int freq_mhz,int ch)265 ar9300_noise_floor_get(struct ath_hal *ah, int freq_mhz, int ch)
266 {
267     int i;
268     for (i = 0; nf_cal_table[i].freq != 0; i++) {
269         if (nf_cal_table[i + 0].freq == freq_mhz ||
270             nf_cal_table[i + 1].freq > freq_mhz ||
271             nf_cal_table[i + 1].freq == 0) {
272             return nf_cal_table[i].chain[ch].cal;
273         }
274     }
275 
276     ath_hal_printf(ah,
277         "%s: **Warning: device %d.%d: "
278         "no nf cal offset found for freq %d chain %d\n",
279         __func__, (AH_PRIVATE(ah))->ah_macVersion,
280         (AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch);
281     return 0;
282 }
283 
284 static int
ar9300_noise_floor_power_get(struct ath_hal * ah,int freq_mhz,int ch)285 ar9300_noise_floor_power_get(struct ath_hal *ah, int freq_mhz, int ch)
286 {
287     int i;
288     for (i = 0; nf_cal_table[i].freq != 0; i++) {
289         if (nf_cal_table[i + 0].freq == freq_mhz ||
290             nf_cal_table[i + 1].freq > freq_mhz ||
291             nf_cal_table[i + 1].freq == 0) {
292             return nf_cal_table[i].chain[ch].pwr;
293         }
294     }
295 
296     ath_hal_printf(ah,
297         "%s: **Warning: device %d.%d: "
298         "no nf pwr offset found for freq %d chain %d\n",
299         __func__, (AH_PRIVATE(ah))->ah_macVersion,
300         (AH_PRIVATE(ah))->ah_macRev, freq_mhz, ch);
301     return 0;
302 }
303 #else
304 #define ar9300_noise_floor_get(_ah,_f,_ich)          ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 1/*use_cal*/)
305 #define ar9300_noise_floor_power_get(_ah,_f,_ich)    ar9300_noise_floor_cal_or_power_get((_ah), (_f), (_ich), 0/*use_cal*/)
306 #endif
307 
308 
309 void
ar9300_configure_spectral_scan(struct ath_hal * ah,HAL_SPECTRAL_PARAM * ss)310 ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
311 {
312     u_int32_t val, i;
313     struct ath_hal_9300 *ahp = AH9300(ah);
314     HAL_BOOL asleep = ahp->ah_chip_full_sleep;
315     int16_t nf_buf[HAL_NUM_NF_READINGS];
316 
317     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
318         ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
319     }
320 
321     ar9300_prep_spectral_scan(ah);
322 
323     if (ss->ss_spectral_pri) {
324         for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
325             nf_buf[i] = NOISE_PWR_DBM_2_INT(ss->ss_nf_cal[i]);
326         }
327         ar9300_load_nf(ah, nf_buf);
328 #ifdef DEMO_MODE
329         ar9300_disable_strong_signal(ah);
330         ar9300_disable_weak_signal(ah);
331         ar9300_set_radar_dc_thresh(ah);
332         ar9300_set_cca_threshold(ah, MAX_CCA_THRESH);
333         /*ar9300_disable_restart(ah);*/
334 #endif
335     }
336 
337     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
338 
339     if (ss->ss_fft_period != HAL_SPECTRAL_PARAM_NOVAL) {
340         val &= ~AR_PHY_SPECTRAL_SCAN_FFT_PERIOD;
341         val |= SM(ss->ss_fft_period, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
342     }
343 
344     if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
345         val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
346         val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
347     }
348 
349     if (ss->ss_count != HAL_SPECTRAL_PARAM_NOVAL) {
350         val &= ~AR_PHY_SPECTRAL_SCAN_COUNT;
351         /* Remnants of a Merlin bug, 128 translates to 0 for
352          * continuous scanning. Instead we do piecemeal captures
353          * of 64 samples for Osprey.
354          */
355         if (ss->ss_count == 128) {
356             val |= SM(0, AR_PHY_SPECTRAL_SCAN_COUNT);
357         } else {
358             val |= SM(ss->ss_count, AR_PHY_SPECTRAL_SCAN_COUNT);
359         }
360     }
361 
362     if (ss->ss_period != HAL_SPECTRAL_PARAM_NOVAL) {
363         val &= ~AR_PHY_SPECTRAL_SCAN_PERIOD;
364         val |= SM(ss->ss_period, AR_PHY_SPECTRAL_SCAN_PERIOD);
365     }
366 
367     if (ss->ss_short_report == AH_TRUE) {
368         val |= AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
369     } else {
370         val &= ~AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT;
371     }
372 
373     /* if noise power cal, force high priority */
374     if (ss->ss_spectral_pri) {
375         val |= AR_PHY_SPECTRAL_SCAN_PRIORITY_HI;
376     } else {
377         val &= ~AR_PHY_SPECTRAL_SCAN_PRIORITY_HI;
378     }
379 
380     /* enable spectral scan */
381     OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val | AR_PHY_SPECTRAL_SCAN_ENABLE);
382 
383     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
384         ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
385     }
386 }
387 
388 /*
389  * Get the spectral parameter values and return them in the pe
390  * structure
391  */
392 
393 void
ar9300_get_spectral_params(struct ath_hal * ah,HAL_SPECTRAL_PARAM * ss)394 ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss)
395 {
396     u_int32_t val;
397     HAL_CHANNEL_INTERNAL *chan = NULL;
398     const struct ieee80211_channel *c;
399     int i, ichain, rx_chain_status;
400     struct ath_hal_9300 *ahp = AH9300(ah);
401     HAL_BOOL asleep = ahp->ah_chip_full_sleep;
402 
403     c = AH_PRIVATE(ah)->ah_curchan;
404     if (c != NULL)
405         chan = ath_hal_checkchannel(ah, c);
406 
407     // XXX TODO: just always wake up all chips?
408     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
409         ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
410     }
411 
412     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
413 
414     ss->ss_fft_period = MS(val, AR_PHY_SPECTRAL_SCAN_FFT_PERIOD);
415     ss->ss_period = MS(val, AR_PHY_SPECTRAL_SCAN_PERIOD);
416     ss->ss_count = MS(val, AR_PHY_SPECTRAL_SCAN_COUNT);
417     ss->ss_short_report = (val & AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT) ? 1:0;
418     ss->ss_spectral_pri = ( val & AR_PHY_SPECTRAL_SCAN_PRIORITY_HI) ? 1:0;
419     OS_MEMZERO(ss->ss_nf_cal, sizeof(ss->ss_nf_cal));
420     OS_MEMZERO(ss->ss_nf_pwr, sizeof(ss->ss_nf_cal));
421     ss->ss_nf_temp_data = 0;
422 
423     if (chan != NULL) {
424         rx_chain_status = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK) & 0x7;
425         for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
426             ichain = i % 3;
427             if (rx_chain_status & (1 << ichain)) {
428                 ss->ss_nf_cal[i] =
429                     ar9300_noise_floor_get(ah, chan->channel, ichain);
430                 ss->ss_nf_pwr[i] =
431                     ar9300_noise_floor_power_get(ah, chan->channel, ichain);
432             }
433         }
434         ss->ss_nf_temp_data = OS_REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);
435     } else {
436         HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
437             "%s: chan is NULL - no ss nf values\n", __func__);
438     }
439 
440     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
441         ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
442     }
443 }
444 
445 HAL_BOOL
ar9300_is_spectral_active(struct ath_hal * ah)446 ar9300_is_spectral_active(struct ath_hal *ah)
447 {
448     u_int32_t val;
449 
450     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
451     return MS(val, AR_PHY_SPECTRAL_SCAN_ACTIVE);
452 }
453 
454 HAL_BOOL
ar9300_is_spectral_enabled(struct ath_hal * ah)455 ar9300_is_spectral_enabled(struct ath_hal *ah)
456 {
457     u_int32_t val;
458 
459     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
460     return MS(val, AR_PHY_SPECTRAL_SCAN_ENABLE);
461 }
462 
ar9300_start_spectral_scan(struct ath_hal * ah)463 void ar9300_start_spectral_scan(struct ath_hal *ah)
464 {
465     u_int32_t val;
466     struct ath_hal_9300 *ahp = AH9300(ah);
467     HAL_BOOL asleep = ahp->ah_chip_full_sleep;
468 
469     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
470         ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
471     }
472 
473     ar9300_prep_spectral_scan(ah);
474 
475     /* activate spectral scan */
476     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
477     /* This is a hardware bug fix, the enable and active bits should
478      * not be set/reset in the same write operation to the register
479      */
480     if (!(val & AR_PHY_SPECTRAL_SCAN_ENABLE)) {
481         val |= AR_PHY_SPECTRAL_SCAN_ENABLE;
482         OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
483         val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
484     }
485     val |= AR_PHY_SPECTRAL_SCAN_ACTIVE;
486     OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
487 
488     /* Reset the PHY_ERR_MASK */
489     val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG);
490     OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val | AR_PHY_ERR_RADAR);
491 
492     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
493         ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
494     }
495 }
496 
ar9300_stop_spectral_scan(struct ath_hal * ah)497 void ar9300_stop_spectral_scan(struct ath_hal *ah)
498 {
499     u_int32_t val;
500     struct ath_hal_9300 *ahp = AH9300(ah);
501     HAL_BOOL asleep = ahp->ah_chip_full_sleep;
502 
503     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
504         ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
505     }
506     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
507 
508     /* deactivate spectral scan */
509     /* HW Bug fix -- Do not disable the spectral scan
510      * only turn off the active bit
511      */
512     //val &= ~AR_PHY_SPECTRAL_SCAN_ENABLE;
513     val &= ~AR_PHY_SPECTRAL_SCAN_ACTIVE;
514     OS_REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
515     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
516 
517     OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_CF_BIN_THRESH,
518                      ahp->ah_radar1);
519     OS_REG_RMW_FIELD(ah, AR_PHY_TIMING2, AR_PHY_TIMING2_DC_OFFSET,
520                      ahp->ah_dc_offset);
521     OS_REG_WRITE(ah, AR_PHY_ERR, 0);
522 
523     if (AH_PRIVATE(ah)->ah_curchan &&
524         IS_5GHZ_FAST_CLOCK_EN(ah, AH_PRIVATE(ah)->ah_curchan))
525     { /* fast clock */
526         OS_REG_RMW_FIELD(ah, AR_PHY_MODE, AR_PHY_MODE_DISABLE_CCK,
527                          ahp->ah_disable_cck);
528     }
529 
530     val = OS_REG_READ(ah, AR_PHY_ERR);
531 
532     val = OS_REG_READ(ah, AR_PHY_ERR_MASK_REG) & (~AR_PHY_ERR_RADAR);
533     OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, val);
534 
535     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
536         ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
537     }
538 }
539 
ar9300_get_spectral_config(struct ath_hal * ah)540 u_int32_t ar9300_get_spectral_config(struct ath_hal *ah)
541 {
542     u_int32_t val;
543     struct ath_hal_9300 *ahp = AH9300(ah);
544     HAL_BOOL asleep = ahp->ah_chip_full_sleep;
545 
546     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
547         ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE);
548     }
549 
550     val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
551 
552     if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && asleep) {
553         ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
554     }
555     return val;
556 }
557 
ar9300_get_ctl_chan_nf(struct ath_hal * ah)558 int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah)
559 {
560     int16_t nf;
561 #if 0
562     struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
563 #endif
564 
565     if ( (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
566         /* Noise floor calibration value is ready */
567         nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
568     } else {
569         /* NF calibration is not done, return nominal value */
570         nf = AH9300(ah)->nfp->nominal;
571     }
572     if (nf & 0x100) {
573         nf = (0 - ((nf ^ 0x1ff) + 1));
574     }
575     return nf;
576 }
577 
ar9300_get_ext_chan_nf(struct ath_hal * ah)578 int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah)
579 {
580     int16_t nf;
581 #if 0
582     struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
583 #endif
584 
585     if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
586         /* Noise floor calibration value is ready */
587         nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
588     } else {
589         /* NF calibration is not done, return nominal value */
590         nf = AH9300(ah)->nfp->nominal;
591     }
592     if (nf & 0x100) {
593         nf = (0 - ((nf ^ 0x1ff) + 1));
594     }
595     return nf;
596 }
597 
598 #endif /* ATH_SUPPORT_SPECTRAL */
599 //#endif
600 
601