1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
4
5 #include <linux/cpumask.h>
6 #include <linux/static_call.h>
7
8 #include <asm/alternative.h>
9 #include <asm/cpufeature.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
14 #include <asm/msr.h>
15 #include <asm/hardirq.h>
16 #include <asm/io.h>
17 #include <asm/posted_intr.h>
18
19 #define ARCH_APICTIMER_STOPS_ON_C3 1
20
21 /*
22 * Debugging macros
23 */
24 #define APIC_QUIET 0
25 #define APIC_VERBOSE 1
26 #define APIC_DEBUG 2
27
28 /* Macros for apic_extnmi which controls external NMI masking */
29 #define APIC_EXTNMI_BSP 0 /* Default */
30 #define APIC_EXTNMI_ALL 1
31 #define APIC_EXTNMI_NONE 2
32
33 /*
34 * Define the default level of output to be very little
35 * This can be turned up by using apic=verbose for more
36 * information and apic=debug for _lots_ of information.
37 * apic_verbosity is defined in apic.c
38 */
39 #define apic_printk(v, s, a...) do { \
40 if ((v) <= apic_verbosity) \
41 printk(s, ##a); \
42 } while (0)
43
44
45 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
46 extern void x86_32_probe_apic(void);
47 #else
x86_32_probe_apic(void)48 static inline void x86_32_probe_apic(void) { }
49 #endif
50
51 extern u32 cpuid_to_apicid[];
52
53 #define CPU_ACPIID_INVALID U32_MAX
54
55 #ifdef CONFIG_X86_LOCAL_APIC
56
57 extern int apic_verbosity;
58 extern int local_apic_timer_c2_ok;
59
60 extern bool apic_is_disabled;
61 extern unsigned int lapic_timer_period;
62
63 extern enum apic_intr_mode_id apic_intr_mode;
64 enum apic_intr_mode_id {
65 APIC_PIC,
66 APIC_VIRTUAL_WIRE,
67 APIC_VIRTUAL_WIRE_NO_CONFIG,
68 APIC_SYMMETRIC_IO,
69 APIC_SYMMETRIC_IO_NO_ROUTING
70 };
71
72 /*
73 * With 82489DX we can't rely on apic feature bit
74 * retrieved via cpuid but still have to deal with
75 * such an apic chip so we assume that SMP configuration
76 * is found from MP table (64bit case uses ACPI mostly
77 * which set smp presence flag as well so we are safe
78 * to use this helper too).
79 */
apic_from_smp_config(void)80 static inline bool apic_from_smp_config(void)
81 {
82 return smp_found_config && !apic_is_disabled;
83 }
84
85 /*
86 * Basic functions accessing APICs.
87 */
88 #ifdef CONFIG_PARAVIRT
89 #include <asm/paravirt.h>
90 #endif
91
native_apic_mem_write(u32 reg,u32 v)92 static inline void native_apic_mem_write(u32 reg, u32 v)
93 {
94 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
95
96 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
97 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
98 ASM_OUTPUT2("0" (v), "m" (*addr)));
99 }
100
native_apic_mem_read(u32 reg)101 static inline u32 native_apic_mem_read(u32 reg)
102 {
103 return readl((void __iomem *)(APIC_BASE + reg));
104 }
105
native_apic_mem_eoi(void)106 static inline void native_apic_mem_eoi(void)
107 {
108 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
109 }
110
111 extern void native_apic_icr_write(u32 low, u32 id);
112 extern u64 native_apic_icr_read(void);
113
apic_is_x2apic_enabled(void)114 static inline bool apic_is_x2apic_enabled(void)
115 {
116 u64 msr;
117
118 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
119 return false;
120 return msr & X2APIC_ENABLE;
121 }
122
123 extern void enable_IR_x2apic(void);
124
125 extern int get_physical_broadcast(void);
126
127 extern int lapic_get_maxlvt(void);
128 extern void clear_local_APIC(void);
129 extern void disconnect_bsp_APIC(int virt_wire_setup);
130 extern void disable_local_APIC(void);
131 extern void apic_soft_disable(void);
132 extern void lapic_shutdown(void);
133 extern void sync_Arb_IDs(void);
134 extern void init_bsp_APIC(void);
135 extern void apic_intr_mode_select(void);
136 extern void apic_intr_mode_init(void);
137 extern void init_apic_mappings(void);
138 void register_lapic_address(unsigned long address);
139 extern void setup_boot_APIC_clock(void);
140 extern void setup_secondary_APIC_clock(void);
141 extern void lapic_update_tsc_freq(void);
142
143 #ifdef CONFIG_X86_64
apic_force_enable(unsigned long addr)144 static inline bool apic_force_enable(unsigned long addr)
145 {
146 return false;
147 }
148 #else
149 extern bool apic_force_enable(unsigned long addr);
150 #endif
151
152 extern void apic_ap_setup(void);
153
154 /*
155 * On 32bit this is mach-xxx local
156 */
157 #ifdef CONFIG_X86_64
158 extern int apic_is_clustered_box(void);
159 #else
apic_is_clustered_box(void)160 static inline int apic_is_clustered_box(void)
161 {
162 return 0;
163 }
164 #endif
165
166 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
167 extern void lapic_assign_system_vectors(void);
168 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
169 extern void lapic_update_legacy_vectors(void);
170 extern void lapic_online(void);
171 extern void lapic_offline(void);
172 extern bool apic_needs_pit(void);
173
174 extern void apic_send_IPI_allbutself(unsigned int vector);
175
176 extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present);
177 extern void topology_register_boot_apic(u32 apic_id);
178 extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id);
179 extern void topology_hotunplug_apic(unsigned int cpu);
180 extern void topology_apply_cmdline_limits_early(void);
181 extern void topology_init_possible_cpus(void);
182 extern void topology_reset_possible_cpus_up(void);
183
184 #else /* !CONFIG_X86_LOCAL_APIC */
lapic_shutdown(void)185 static inline void lapic_shutdown(void) { }
186 #define local_apic_timer_c2_ok 1
init_apic_mappings(void)187 static inline void init_apic_mappings(void) { }
disable_local_APIC(void)188 static inline void disable_local_APIC(void) { }
189 # define setup_boot_APIC_clock x86_init_noop
190 # define setup_secondary_APIC_clock x86_init_noop
lapic_update_tsc_freq(void)191 static inline void lapic_update_tsc_freq(void) { }
init_bsp_APIC(void)192 static inline void init_bsp_APIC(void) { }
apic_intr_mode_select(void)193 static inline void apic_intr_mode_select(void) { }
apic_intr_mode_init(void)194 static inline void apic_intr_mode_init(void) { }
lapic_assign_system_vectors(void)195 static inline void lapic_assign_system_vectors(void) { }
lapic_assign_legacy_vector(unsigned int i,bool r)196 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
apic_needs_pit(void)197 static inline bool apic_needs_pit(void) { return true; }
topology_apply_cmdline_limits_early(void)198 static inline void topology_apply_cmdline_limits_early(void) { }
topology_init_possible_cpus(void)199 static inline void topology_init_possible_cpus(void) { }
200 #endif /* !CONFIG_X86_LOCAL_APIC */
201
202 #ifdef CONFIG_X86_X2APIC
native_apic_msr_write(u32 reg,u32 v)203 static inline void native_apic_msr_write(u32 reg, u32 v)
204 {
205 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
206 reg == APIC_LVR)
207 return;
208
209 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
210 }
211
native_apic_msr_eoi(void)212 static inline void native_apic_msr_eoi(void)
213 {
214 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
215 }
216
native_apic_msr_read(u32 reg)217 static inline u32 native_apic_msr_read(u32 reg)
218 {
219 u64 msr;
220
221 if (reg == APIC_DFR)
222 return -1;
223
224 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
225 return (u32)msr;
226 }
227
native_x2apic_icr_write(u32 low,u32 id)228 static inline void native_x2apic_icr_write(u32 low, u32 id)
229 {
230 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
231 }
232
native_x2apic_icr_read(void)233 static inline u64 native_x2apic_icr_read(void)
234 {
235 unsigned long val;
236
237 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
238 return val;
239 }
240
241 extern int x2apic_mode;
242 extern int x2apic_phys;
243 extern void __init x2apic_set_max_apicid(u32 apicid);
244 extern void x2apic_setup(void);
x2apic_enabled(void)245 static inline int x2apic_enabled(void)
246 {
247 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
248 }
249
250 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
251 #else /* !CONFIG_X86_X2APIC */
x2apic_setup(void)252 static inline void x2apic_setup(void) { }
x2apic_enabled(void)253 static inline int x2apic_enabled(void) { return 0; }
native_apic_msr_read(u32 reg)254 static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
255 #define x2apic_mode (0)
256 #define x2apic_supported() (0)
257 #endif /* !CONFIG_X86_X2APIC */
258 extern void __init check_x2apic(void);
259
260 struct irq_data;
261
262 /*
263 * Copyright 2004 James Cleverdon, IBM.
264 *
265 * Generic APIC sub-arch data struct.
266 *
267 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
268 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
269 * James Cleverdon.
270 */
271 struct apic {
272 /* Hotpath functions first */
273 void (*eoi)(void);
274 void (*native_eoi)(void);
275 void (*write)(u32 reg, u32 v);
276 u32 (*read)(u32 reg);
277
278 /* IPI related functions */
279 void (*wait_icr_idle)(void);
280 u32 (*safe_wait_icr_idle)(void);
281
282 void (*send_IPI)(int cpu, int vector);
283 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
284 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
285 void (*send_IPI_allbutself)(int vector);
286 void (*send_IPI_all)(int vector);
287 void (*send_IPI_self)(int vector);
288
289 u32 disable_esr : 1,
290 dest_mode_logical : 1,
291 x2apic_set_max_apicid : 1,
292 nmi_to_offline_cpu : 1;
293
294 u32 (*calc_dest_apicid)(unsigned int cpu);
295
296 /* ICR related functions */
297 u64 (*icr_read)(void);
298 void (*icr_write)(u32 low, u32 high);
299
300 /* The limit of the APIC ID space. */
301 u32 max_apic_id;
302
303 /* Probe, setup and smpboot functions */
304 int (*probe)(void);
305 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
306
307 void (*init_apic_ldr)(void);
308 u32 (*cpu_present_to_apicid)(int mps_cpu);
309
310 u32 (*get_apic_id)(u32 id);
311
312 /* wakeup_secondary_cpu */
313 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
314 /* wakeup secondary CPU using 64-bit wakeup point */
315 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
316
317 char *name;
318 };
319
320 struct apic_override {
321 void (*eoi)(void);
322 void (*native_eoi)(void);
323 void (*write)(u32 reg, u32 v);
324 u32 (*read)(u32 reg);
325 void (*send_IPI)(int cpu, int vector);
326 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
327 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
328 void (*send_IPI_allbutself)(int vector);
329 void (*send_IPI_all)(int vector);
330 void (*send_IPI_self)(int vector);
331 u64 (*icr_read)(void);
332 void (*icr_write)(u32 low, u32 high);
333 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
334 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
335 };
336
337 /*
338 * Pointer to the local APIC driver in use on this system (there's
339 * always just one such driver in use - the kernel decides via an
340 * early probing process which one it picks - and then sticks to it):
341 */
342 extern struct apic *apic;
343
344 /*
345 * APIC drivers are probed based on how they are listed in the .apicdrivers
346 * section. So the order is important and enforced by the ordering
347 * of different apic driver files in the Makefile.
348 *
349 * For the files having two apic drivers, we use apic_drivers()
350 * to enforce the order with in them.
351 */
352 #define apic_driver(sym) \
353 static const struct apic *__apicdrivers_##sym __used \
354 __aligned(sizeof(struct apic *)) \
355 __section(".apicdrivers") = { &sym }
356
357 #define apic_drivers(sym1, sym2) \
358 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
359 __aligned(sizeof(struct apic *)) \
360 __section(".apicdrivers") = { &sym1, &sym2 }
361
362 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
363
364 /*
365 * APIC functionality to boot other CPUs - only used on SMP:
366 */
367 #ifdef CONFIG_SMP
368 extern int lapic_can_unplug_cpu(void);
369 #endif
370
371 #ifdef CONFIG_X86_LOCAL_APIC
372 extern struct apic_override __x86_apic_override;
373
374 void __init apic_setup_apic_calls(void);
375 void __init apic_install_driver(struct apic *driver);
376
377 #define apic_update_callback(_callback, _fn) { \
378 __x86_apic_override._callback = _fn; \
379 apic->_callback = _fn; \
380 static_call_update(apic_call_##_callback, _fn); \
381 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
382 }
383
384 #define DECLARE_APIC_CALL(__cb) \
385 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
386
387 DECLARE_APIC_CALL(eoi);
388 DECLARE_APIC_CALL(native_eoi);
389 DECLARE_APIC_CALL(icr_read);
390 DECLARE_APIC_CALL(icr_write);
391 DECLARE_APIC_CALL(read);
392 DECLARE_APIC_CALL(send_IPI);
393 DECLARE_APIC_CALL(send_IPI_mask);
394 DECLARE_APIC_CALL(send_IPI_mask_allbutself);
395 DECLARE_APIC_CALL(send_IPI_allbutself);
396 DECLARE_APIC_CALL(send_IPI_all);
397 DECLARE_APIC_CALL(send_IPI_self);
398 DECLARE_APIC_CALL(wait_icr_idle);
399 DECLARE_APIC_CALL(wakeup_secondary_cpu);
400 DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
401 DECLARE_APIC_CALL(write);
402
apic_read(u32 reg)403 static __always_inline u32 apic_read(u32 reg)
404 {
405 return static_call(apic_call_read)(reg);
406 }
407
apic_write(u32 reg,u32 val)408 static __always_inline void apic_write(u32 reg, u32 val)
409 {
410 static_call(apic_call_write)(reg, val);
411 }
412
apic_eoi(void)413 static __always_inline void apic_eoi(void)
414 {
415 static_call(apic_call_eoi)();
416 }
417
apic_native_eoi(void)418 static __always_inline void apic_native_eoi(void)
419 {
420 static_call(apic_call_native_eoi)();
421 }
422
apic_icr_read(void)423 static __always_inline u64 apic_icr_read(void)
424 {
425 return static_call(apic_call_icr_read)();
426 }
427
apic_icr_write(u32 low,u32 high)428 static __always_inline void apic_icr_write(u32 low, u32 high)
429 {
430 static_call(apic_call_icr_write)(low, high);
431 }
432
__apic_send_IPI(int cpu,int vector)433 static __always_inline void __apic_send_IPI(int cpu, int vector)
434 {
435 static_call(apic_call_send_IPI)(cpu, vector);
436 }
437
__apic_send_IPI_mask(const struct cpumask * mask,int vector)438 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
439 {
440 static_call_mod(apic_call_send_IPI_mask)(mask, vector);
441 }
442
__apic_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)443 static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
444 {
445 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
446 }
447
__apic_send_IPI_allbutself(int vector)448 static __always_inline void __apic_send_IPI_allbutself(int vector)
449 {
450 static_call(apic_call_send_IPI_allbutself)(vector);
451 }
452
__apic_send_IPI_all(int vector)453 static __always_inline void __apic_send_IPI_all(int vector)
454 {
455 static_call(apic_call_send_IPI_all)(vector);
456 }
457
__apic_send_IPI_self(int vector)458 static __always_inline void __apic_send_IPI_self(int vector)
459 {
460 static_call_mod(apic_call_send_IPI_self)(vector);
461 }
462
apic_wait_icr_idle(void)463 static __always_inline void apic_wait_icr_idle(void)
464 {
465 static_call_cond(apic_call_wait_icr_idle)();
466 }
467
safe_apic_wait_icr_idle(void)468 static __always_inline u32 safe_apic_wait_icr_idle(void)
469 {
470 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
471 }
472
apic_id_valid(u32 apic_id)473 static __always_inline bool apic_id_valid(u32 apic_id)
474 {
475 return apic_id <= apic->max_apic_id;
476 }
477
478 #else /* CONFIG_X86_LOCAL_APIC */
479
apic_read(u32 reg)480 static inline u32 apic_read(u32 reg) { return 0; }
apic_write(u32 reg,u32 val)481 static inline void apic_write(u32 reg, u32 val) { }
apic_eoi(void)482 static inline void apic_eoi(void) { }
apic_icr_read(void)483 static inline u64 apic_icr_read(void) { return 0; }
apic_icr_write(u32 low,u32 high)484 static inline void apic_icr_write(u32 low, u32 high) { }
apic_wait_icr_idle(void)485 static inline void apic_wait_icr_idle(void) { }
safe_apic_wait_icr_idle(void)486 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
apic_set_eoi_cb(void (* eoi)(void))487 static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
apic_native_eoi(void)488 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
apic_setup_apic_calls(void)489 static inline void apic_setup_apic_calls(void) { }
490
491 #define apic_update_callback(_callback, _fn) do { } while (0)
492
493 #endif /* CONFIG_X86_LOCAL_APIC */
494
495 extern void apic_ack_irq(struct irq_data *data);
496
lapic_vector_set_in_irr(unsigned int vector)497 static inline bool lapic_vector_set_in_irr(unsigned int vector)
498 {
499 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
500
501 return !!(irr & (1U << (vector % 32)));
502 }
503
is_vector_pending(unsigned int vector)504 static inline bool is_vector_pending(unsigned int vector)
505 {
506 return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector);
507 }
508
509 /*
510 * Warm reset vector position:
511 */
512 #define TRAMPOLINE_PHYS_LOW 0x467
513 #define TRAMPOLINE_PHYS_HIGH 0x469
514
515 extern void generic_bigsmp_probe(void);
516
517 #ifdef CONFIG_X86_LOCAL_APIC
518
519 #include <asm/smp.h>
520
521 extern struct apic apic_noop;
522
read_apic_id(void)523 static inline u32 read_apic_id(void)
524 {
525 u32 reg = apic_read(APIC_ID);
526
527 return apic->get_apic_id(reg);
528 }
529
530 #ifdef CONFIG_X86_64
531 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
532 extern int default_acpi_madt_oem_check(char *, char *);
533 extern void x86_64_probe_apic(void);
534 #else
default_acpi_madt_oem_check(char * a,char * b)535 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
x86_64_probe_apic(void)536 static inline void x86_64_probe_apic(void) { }
537 #endif
538
539 extern int default_apic_id_valid(u32 apicid);
540
541 extern u32 apic_default_calc_apicid(unsigned int cpu);
542 extern u32 apic_flat_calc_apicid(unsigned int cpu);
543
544 extern u32 default_cpu_present_to_apicid(int mps_cpu);
545
546 void apic_send_nmi_to_offline_cpu(unsigned int cpu);
547
548 #else /* CONFIG_X86_LOCAL_APIC */
549
read_apic_id(void)550 static inline u32 read_apic_id(void) { return 0; }
551
552 #endif /* !CONFIG_X86_LOCAL_APIC */
553
554 #ifdef CONFIG_SMP
555 void apic_smt_update(void);
556 #else
apic_smt_update(void)557 static inline void apic_smt_update(void) { }
558 #endif
559
560 struct msi_msg;
561 struct irq_cfg;
562
563 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
564 bool dmar);
565
566 extern void ioapic_zap_locks(void);
567
568 #endif /* _ASM_X86_APIC_H */
569