1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_PROCESSOR_H
9 #define __ASM_PROCESSOR_H
10
11 /*
12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
13 * no point in shifting all network buffers by 2 bytes just to make some IP
14 * header fields appear aligned in memory, potentially sacrificing some DMA
15 * performance on some platforms.
16 */
17 #define NET_IP_ALIGN 0
18
19 #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20 #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21
22 #define MTE_CTRL_TCF_SYNC (1UL << 16)
23 #define MTE_CTRL_TCF_ASYNC (1UL << 17)
24 #define MTE_CTRL_TCF_ASYMM (1UL << 18)
25
26 #ifndef __ASSEMBLY__
27
28 #include <linux/build_bug.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/stddef.h>
32 #include <linux/string.h>
33 #include <linux/thread_info.h>
34
35 #include <vdso/processor.h>
36
37 #include <asm/alternative.h>
38 #include <asm/cpufeature.h>
39 #include <asm/hw_breakpoint.h>
40 #include <asm/kasan.h>
41 #include <asm/lse.h>
42 #include <asm/pgtable-hwdef.h>
43 #include <asm/pointer_auth.h>
44 #include <asm/ptrace.h>
45 #include <asm/spectre.h>
46 #include <asm/types.h>
47
48 /*
49 * TASK_SIZE - the maximum size of a user space task.
50 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
51 */
52
53 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
54 #define TASK_SIZE_64 (UL(1) << vabits_actual)
55 #define TASK_SIZE_MAX (UL(1) << VA_BITS)
56
57 #ifdef CONFIG_COMPAT
58 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
59 /*
60 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
61 * by the compat vectors page.
62 */
63 #define TASK_SIZE_32 UL(0x100000000)
64 #else
65 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
66 #endif /* CONFIG_ARM64_64K_PAGES */
67 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
68 TASK_SIZE_32 : TASK_SIZE_64)
69 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
70 TASK_SIZE_32 : TASK_SIZE_64)
71 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
72 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
73 #else
74 #define TASK_SIZE TASK_SIZE_64
75 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
76 #endif /* CONFIG_COMPAT */
77
78 #ifdef CONFIG_ARM64_FORCE_52BIT
79 #define STACK_TOP_MAX TASK_SIZE_64
80 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
81 #else
82 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
83 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
84 #endif /* CONFIG_ARM64_FORCE_52BIT */
85
86 #ifdef CONFIG_COMPAT
87 #define AARCH32_VECTORS_BASE 0xffff0000
88 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
89 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
90 #else
91 #define STACK_TOP STACK_TOP_MAX
92 #endif /* CONFIG_COMPAT */
93
94 #ifndef CONFIG_ARM64_FORCE_52BIT
95 #define arch_get_mmap_end(addr, len, flags) \
96 (((addr) > DEFAULT_MAP_WINDOW) ? TASK_SIZE : DEFAULT_MAP_WINDOW)
97
98 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
99 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
100 base)
101 #endif /* CONFIG_ARM64_FORCE_52BIT */
102
103 extern phys_addr_t arm64_dma_phys_limit;
104 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
105
106 struct debug_info {
107 #ifdef CONFIG_HAVE_HW_BREAKPOINT
108 /* Have we suspended stepping by a debugger? */
109 int suspended_step;
110 /* Allow breakpoints and watchpoints to be disabled for this thread. */
111 int bps_disabled;
112 int wps_disabled;
113 /* Hardware breakpoints pinned to this task. */
114 struct perf_event *hbp_break[ARM_MAX_BRP];
115 struct perf_event *hbp_watch[ARM_MAX_WRP];
116 #endif
117 };
118
119 enum vec_type {
120 ARM64_VEC_SVE = 0,
121 ARM64_VEC_SME,
122 ARM64_VEC_MAX,
123 };
124
125 enum fp_type {
126 FP_STATE_CURRENT, /* Save based on current task state. */
127 FP_STATE_FPSIMD,
128 FP_STATE_SVE,
129 };
130
131 struct cpu_context {
132 unsigned long x19;
133 unsigned long x20;
134 unsigned long x21;
135 unsigned long x22;
136 unsigned long x23;
137 unsigned long x24;
138 unsigned long x25;
139 unsigned long x26;
140 unsigned long x27;
141 unsigned long x28;
142 unsigned long fp;
143 unsigned long sp;
144 unsigned long pc;
145 };
146
147 struct thread_struct {
148 struct cpu_context cpu_context; /* cpu context */
149
150 /*
151 * Whitelisted fields for hardened usercopy:
152 * Maintainers must ensure manually that this contains no
153 * implicit padding.
154 */
155 struct {
156 unsigned long tp_value; /* TLS register */
157 unsigned long tp2_value;
158 u64 fpmr;
159 unsigned long pad;
160 struct user_fpsimd_state fpsimd_state;
161 } uw;
162
163 enum fp_type fp_type; /* registers FPSIMD or SVE? */
164 unsigned int fpsimd_cpu;
165 void *sve_state; /* SVE registers, if any */
166 void *sme_state; /* ZA and ZT state, if any */
167 unsigned int vl[ARM64_VEC_MAX]; /* vector length */
168 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */
169 unsigned long fault_address; /* fault info */
170 unsigned long fault_code; /* ESR_EL1 value */
171 struct debug_info debug; /* debugging */
172
173 struct user_fpsimd_state kernel_fpsimd_state;
174 unsigned int kernel_fpsimd_cpu;
175 #ifdef CONFIG_ARM64_PTR_AUTH
176 struct ptrauth_keys_user keys_user;
177 #ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
178 struct ptrauth_keys_kernel keys_kernel;
179 #endif
180 #endif
181 #ifdef CONFIG_ARM64_MTE
182 u64 mte_ctrl;
183 #endif
184 u64 sctlr_user;
185 u64 svcr;
186 u64 tpidr2_el0;
187 u64 por_el0;
188 };
189
thread_get_vl(struct thread_struct * thread,enum vec_type type)190 static inline unsigned int thread_get_vl(struct thread_struct *thread,
191 enum vec_type type)
192 {
193 return thread->vl[type];
194 }
195
thread_get_sve_vl(struct thread_struct * thread)196 static inline unsigned int thread_get_sve_vl(struct thread_struct *thread)
197 {
198 return thread_get_vl(thread, ARM64_VEC_SVE);
199 }
200
thread_get_sme_vl(struct thread_struct * thread)201 static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
202 {
203 return thread_get_vl(thread, ARM64_VEC_SME);
204 }
205
thread_get_cur_vl(struct thread_struct * thread)206 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
207 {
208 if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
209 return thread_get_sme_vl(thread);
210 else
211 return thread_get_sve_vl(thread);
212 }
213
214 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type);
215 void task_set_vl(struct task_struct *task, enum vec_type type,
216 unsigned long vl);
217 void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
218 unsigned long vl);
219 unsigned int task_get_vl_onexec(const struct task_struct *task,
220 enum vec_type type);
221
task_get_sve_vl(const struct task_struct * task)222 static inline unsigned int task_get_sve_vl(const struct task_struct *task)
223 {
224 return task_get_vl(task, ARM64_VEC_SVE);
225 }
226
task_get_sme_vl(const struct task_struct * task)227 static inline unsigned int task_get_sme_vl(const struct task_struct *task)
228 {
229 return task_get_vl(task, ARM64_VEC_SME);
230 }
231
task_set_sve_vl(struct task_struct * task,unsigned long vl)232 static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl)
233 {
234 task_set_vl(task, ARM64_VEC_SVE, vl);
235 }
236
task_get_sve_vl_onexec(const struct task_struct * task)237 static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task)
238 {
239 return task_get_vl_onexec(task, ARM64_VEC_SVE);
240 }
241
task_set_sve_vl_onexec(struct task_struct * task,unsigned long vl)242 static inline void task_set_sve_vl_onexec(struct task_struct *task,
243 unsigned long vl)
244 {
245 task_set_vl_onexec(task, ARM64_VEC_SVE, vl);
246 }
247
248 #define SCTLR_USER_MASK \
249 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
250 SCTLR_EL1_TCF0_MASK)
251
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)252 static inline void arch_thread_struct_whitelist(unsigned long *offset,
253 unsigned long *size)
254 {
255 /* Verify that there is no padding among the whitelisted fields: */
256 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
257 sizeof_field(struct thread_struct, uw.tp_value) +
258 sizeof_field(struct thread_struct, uw.tp2_value) +
259 sizeof_field(struct thread_struct, uw.fpmr) +
260 sizeof_field(struct thread_struct, uw.pad) +
261 sizeof_field(struct thread_struct, uw.fpsimd_state));
262
263 *offset = offsetof(struct thread_struct, uw);
264 *size = sizeof_field(struct thread_struct, uw);
265 }
266
267 #ifdef CONFIG_COMPAT
268 #define task_user_tls(t) \
269 ({ \
270 unsigned long *__tls; \
271 if (is_compat_thread(task_thread_info(t))) \
272 __tls = &(t)->thread.uw.tp2_value; \
273 else \
274 __tls = &(t)->thread.uw.tp_value; \
275 __tls; \
276 })
277 #else
278 #define task_user_tls(t) (&(t)->thread.uw.tp_value)
279 #endif
280
281 /* Sync TPIDR_EL0 back to thread_struct for current */
282 void tls_preserve_current_state(void);
283
284 #define INIT_THREAD { \
285 .fpsimd_cpu = NR_CPUS, \
286 }
287
start_thread_common(struct pt_regs * regs,unsigned long pc)288 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
289 {
290 s32 previous_syscall = regs->syscallno;
291 memset(regs, 0, sizeof(*regs));
292 regs->syscallno = previous_syscall;
293 regs->pc = pc;
294
295 if (system_uses_irq_prio_masking())
296 regs->pmr_save = GIC_PRIO_IRQON;
297 }
298
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)299 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
300 unsigned long sp)
301 {
302 start_thread_common(regs, pc);
303 regs->pstate = PSR_MODE_EL0t;
304 spectre_v4_enable_task_mitigation(current);
305 regs->sp = sp;
306 }
307
308 #ifdef CONFIG_COMPAT
compat_start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)309 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
310 unsigned long sp)
311 {
312 start_thread_common(regs, pc);
313 regs->pstate = PSR_AA32_MODE_USR;
314 if (pc & 1)
315 regs->pstate |= PSR_AA32_T_BIT;
316
317 #ifdef __AARCH64EB__
318 regs->pstate |= PSR_AA32_E_BIT;
319 #endif
320
321 spectre_v4_enable_task_mitigation(current);
322 regs->compat_sp = sp;
323 }
324 #endif
325
is_ttbr0_addr(unsigned long addr)326 static __always_inline bool is_ttbr0_addr(unsigned long addr)
327 {
328 /* entry assembly clears tags for TTBR0 addrs */
329 return addr < TASK_SIZE;
330 }
331
is_ttbr1_addr(unsigned long addr)332 static __always_inline bool is_ttbr1_addr(unsigned long addr)
333 {
334 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
335 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
336 }
337
338 /* Forward declaration, a strange C thing */
339 struct task_struct;
340
341 unsigned long __get_wchan(struct task_struct *p);
342
343 void update_sctlr_el1(u64 sctlr);
344
345 /* Thread switching */
346 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
347 struct task_struct *next);
348
349 #define task_pt_regs(p) \
350 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
351
352 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
353 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
354
355 /*
356 * Prefetching support
357 */
358 #define ARCH_HAS_PREFETCH
prefetch(const void * ptr)359 static inline void prefetch(const void *ptr)
360 {
361 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
362 }
363
364 #define ARCH_HAS_PREFETCHW
prefetchw(const void * ptr)365 static inline void prefetchw(const void *ptr)
366 {
367 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
368 }
369
370 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
371 extern void __init minsigstksz_setup(void);
372
373 /*
374 * Not at the top of the file due to a direct #include cycle between
375 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
376 * ensures that contents of processor.h are visible to fpsimd.h even if
377 * processor.h is included first.
378 *
379 * These prctl helpers are the only things in this file that require
380 * fpsimd.h. The core code expects them to be in this header.
381 */
382 #include <asm/fpsimd.h>
383
384 /* Userspace interface for PR_S[MV]E_{SET,GET}_VL prctl()s: */
385 #define SVE_SET_VL(arg) sve_set_current_vl(arg)
386 #define SVE_GET_VL() sve_get_current_vl()
387 #define SME_SET_VL(arg) sme_set_current_vl(arg)
388 #define SME_GET_VL() sme_get_current_vl()
389
390 /* PR_PAC_RESET_KEYS prctl */
391 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
392
393 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
394 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
395 ptrauth_set_enabled_keys(tsk, keys, enabled)
396 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
397
398 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
399 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
400 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
401 long get_tagged_addr_ctrl(struct task_struct *task);
402 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
403 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
404 #endif
405
406 int get_tsc_mode(unsigned long adr);
407 int set_tsc_mode(unsigned int val);
408 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
409 #define SET_TSC_CTL(val) set_tsc_mode((val))
410
411 #endif /* __ASSEMBLY__ */
412 #endif /* __ASM_PROCESSOR_H */
413