1 /* 2 * Copyright (C) 2015 by pierrr kuo 3 * vichy.kuo@gmail.com 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 #ifndef OPENOCD_TARGET_ARMV8_OPCODES_H 16 #define OPENOCD_TARGET_ARMV8_OPCODES_H 17 18 #include "arm_opcodes.h" 19 20 #define SYSTEM_CUREL_MASK 0xC0 21 #define SYSTEM_CUREL_SHIFT 6 22 #define SYSTEM_CUREL_EL0 0x0 23 #define SYSTEM_CUREL_EL1 0x1 24 #define SYSTEM_CUREL_EL2 0x2 25 #define SYSTEM_CUREL_EL3 0x3 26 #define SYSTEM_CUREL_NONCH 0xF 27 #define SYSTEM_AARCH64 0x1 28 29 #define SYSTEM_AAR64_MODE_EL0t 0x0 30 #define SYSTEM_AAR64_MODE_EL1t 0x4 31 #define SYSTEM_AAR64_MODE_EL1h 0x5 32 #define SYSTEM_AAR64_MODE_EL2t 0x8 33 #define SYSTEM_AAR64_MODE_EL2h 0x9 34 #define SYSTEM_AAR64_MODE_EL3t 0xC 35 #define SYSTEM_AAR64_MODE_EL3h 0xd 36 37 #define SYSTEM_DAIF 0b1101101000010001 38 #define SYSTEM_DAIF_MASK 0x3C0 39 #define SYSTEM_DAIF_SHIFT 6 40 41 #define SYSTEM_ELR_EL1 0b1100001000000001 42 #define SYSTEM_ELR_EL2 0b1110001000000001 43 #define SYSTEM_ELR_EL3 0b1111001000000001 44 45 #define SYSTEM_SCTLR_EL1 0b1100000010000000 46 #define SYSTEM_SCTLR_EL2 0b1110000010000000 47 #define SYSTEM_SCTLR_EL3 0b1111000010000000 48 49 #define SYSTEM_FPCR 0b1101101000100000 50 #define SYSTEM_FPSR 0b1101101000100001 51 #define SYSTEM_DAIF 0b1101101000010001 52 #define SYSTEM_NZCV 0b1101101000010000 53 #define SYSTEM_SP_EL0 0b1100001000001000 54 #define SYSTEM_SP_EL1 0b1110001000001000 55 #define SYSTEM_SP_EL2 0b1111001000001000 56 #define SYSTEM_SP_SEL 0b1100001000010000 57 #define SYSTEM_SPSR_ABT 0b1110001000011001 58 #define SYSTEM_SPSR_FIQ 0b1110001000011011 59 #define SYSTEM_SPSR_IRQ 0b1110001000011000 60 #define SYSTEM_SPSR_UND 0b1110001000011010 61 62 #define SYSTEM_SPSR_EL1 0b1100001000000000 63 #define SYSTEM_SPSR_EL2 0b1110001000000000 64 #define SYSTEM_SPSR_EL3 0b1111001000000000 65 66 #define SYSTEM_ISR_EL1 0b1100011000001000 67 68 #define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000 69 #define SYSTEM_DBG_DLR_EL0 0b1101101000101001 70 #define SYSTEM_DBG_DTRRX_EL0 0b1001100000101000 71 #define SYSTEM_DBG_DTRTX_EL0 0b1001100000101000 72 #define SYSTEM_DBG_DBGDTR_EL0 0b1001100000100000 73 74 #define SYSTEM_CCSIDR 0b1100100000000000 75 #define SYSTEM_CLIDR 0b1100100000000001 76 #define SYSTEM_CSSELR 0b1101000000000000 77 #define SYSTEM_CTYPE 0b1101100000000001 78 #define SYSTEM_CTR 0b1101100000000001 79 80 #define SYSTEM_DCCISW 0b0100001111110010 81 #define SYSTEM_DCCSW 0b0100001111010010 82 #define SYSTEM_ICIVAU 0b0101101110101001 83 #define SYSTEM_DCCVAU 0b0101101111011001 84 #define SYSTEM_DCCIVAC 0b0101101111110001 85 86 #define SYSTEM_MPIDR 0b1100000000000101 87 88 #define SYSTEM_TCR_EL1 0b1100000100000010 89 #define SYSTEM_TCR_EL2 0b1110000100000010 90 #define SYSTEM_TCR_EL3 0b1111000100000010 91 92 #define SYSTEM_TTBR0_EL1 0b1100000100000000 93 #define SYSTEM_TTBR0_EL2 0b1110000100000000 94 #define SYSTEM_TTBR0_EL3 0b1111000100000000 95 #define SYSTEM_TTBR1_EL1 0b1100000100000001 96 97 /* ARMv8 address translation */ 98 #define SYSTEM_PAR_EL1 0b1100001110100000 99 #define SYSTEM_ATS12E0R 0b0110001111000110 100 #define SYSTEM_ATS12E1R 0b0110001111000100 101 #define SYSTEM_ATS1E2R 0b0110001111000000 102 #define SYSTEM_ATS1E3R 0b0111001111000000 103 104 /* fault status and fault address */ 105 #define SYSTEM_FAR_EL1 0b1100001100000000 106 #define SYSTEM_FAR_EL2 0b1110001100000000 107 #define SYSTEM_FAR_EL3 0b1111001100000000 108 #define SYSTEM_ESR_EL1 0b1100001010010000 109 #define SYSTEM_ESR_EL2 0b1110001010010000 110 #define SYSTEM_ESR_EL3 0b1111001010010000 111 112 #define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt)) 113 #define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt)) 114 #define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt)) 115 #define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt)) 116 117 /* T32 instruction to access coprocessor registers */ 118 #define ARMV8_MCR_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MCR(cp, opc1, Rt, CRn, CRm, opc2) 119 #define ARMV8_MRC_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MRC(cp, opc1, Rt, CRn, CRm, opc2) 120 121 /* T32 instructions to access DSPSR and DLR */ 122 #define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt) 123 #define ARMV8_MCR_DSPSR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, Rt) 124 #define ARMV8_MRC_DLR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt) 125 #define ARMV8_MCR_DLR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt) 126 127 #define ARMV8_DCPS1(IM) (0xd4a00001 | (((IM) & 0xFFFF) << 5)) 128 #define ARMV8_DCPS2(IM) (0xd4a00002 | (((IM) & 0xFFFF) << 5)) 129 #define ARMV8_DCPS3(IM) (0xd4a00003 | (((IM) & 0xFFFF) << 5)) 130 #define ARMV8_DCPS(EL, IM) (0xd4a00000 | (((IM) & 0xFFFF) << 5) | EL) 131 #define ARMV8_DCPS_T1(EL) (0xf78f8000 | EL) 132 #define ARMV8_DRPS 0xd6bf03e0 133 #define ARMV8_ERET_T1 0xf3de8f00 134 135 #define ARMV8_DSB_SY 0xd5033F9F 136 #define ARMV8_DSB_SY_T1 0xf3bf8f4f 137 #define ARMV8_ISB 0xd5033fdf 138 #define ARMV8_ISB_SY_T1 0xf3bf8f6f 139 140 #define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt)) 141 /* ARM V8 Move to system register. */ 142 #define ARMV8_MSR_GP(System, Rt) \ 143 (0xd5100000 | ((System) << 5) | (Rt)) 144 /* ARM V8 Move immediate to process state field. */ 145 #define ARMV8_MSR_IM(Op1, CRm, Op2) \ 146 (0xd500401f | ((Op1) << 16) | ((CRm) << 8) | ((Op2) << 5)) 147 148 #define ARMV8_MRS_T1(R, M1, Rd, M) (0xF3E08020 | (R << 20) | (M1 << 16) | (Rd << 8) | (M << 4)) 149 #define ARMV8_MRS_xPSR_T1(R, Rd) (0xF3EF8000 | (R << 20) | (Rd << 8)) 150 #define ARMV8_MSR_GP_T1(R, M1, Rd, M) (0xF3808020 | (R << 20) | (M1 << 8) | (Rd << 16) | (M << 4)) 151 #define ARMV8_MSR_GP_xPSR_T1(R, Rn, mask) (0xF3808000 | (R << 20) | (Rn << 16) | (mask << 8)) 152 153 #define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5)) 154 #define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5)) 155 #define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF)) 156 #define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f)) 157 158 #define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt)) 159 #define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F)) 160 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt)) 161 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F)) 162 163 #define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd) 164 #define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd) 165 #define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd) 166 167 #define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12)) 168 #define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12)) 169 #define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12)) 170 171 #define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd) 172 #define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd) 173 #define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd) 174 175 #define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12)) 176 #define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12)) 177 #define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12)) 178 179 #define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd) 180 #define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd) 181 182 #define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt)) 183 #define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt)) 184 #define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt)) 185 #define ARMV8_MSR_FPSR(Rt) (0xd51b4420 | (Rt)) 186 187 #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt) 188 189 enum armv8_opcode { 190 READ_REG_CTR, 191 READ_REG_CLIDR, 192 READ_REG_CSSELR, 193 READ_REG_CCSIDR, 194 WRITE_REG_CSSELR, 195 READ_REG_MPIDR, 196 READ_REG_DTRRX, 197 WRITE_REG_DTRTX, 198 WRITE_REG_DSPSR, 199 READ_REG_DSPSR, 200 ARMV8_OPC_DSB_SY, 201 ARMV8_OPC_DCPS, 202 ARMV8_OPC_DRPS, 203 ARMV8_OPC_ISB_SY, 204 ARMV8_OPC_DCCISW, 205 ARMV8_OPC_DCCIVAC, 206 ARMV8_OPC_ICIVAU, 207 ARMV8_OPC_HLT, 208 ARMV8_OPC_STRB_IP, 209 ARMV8_OPC_STRH_IP, 210 ARMV8_OPC_STRW_IP, 211 ARMV8_OPC_LDRB_IP, 212 ARMV8_OPC_LDRH_IP, 213 ARMV8_OPC_LDRW_IP, 214 ARMV8_OPC_NUM, 215 }; 216 217 extern uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode); 218 extern void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64); 219 220 #endif /* OPENOCD_TARGET_ARMV8_OPCODES_H */ 221