1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 #else
30 # define TARGET_LONG_BITS 32
31 #endif
32
33 /* ARM processors have a weak memory model */
34 #define TCG_GUEST_DEFAULT_MO (0)
35
36 #define CPUArchState struct CPUARMState
37
38 #include "qemu-common.h"
39 #include "cpu-qom.h"
40 #include "exec/cpu-defs.h"
41
42 #define EXCP_UDEF 1 /* undefined instruction */
43 #define EXCP_SWI 2 /* software interrupt */
44 #define EXCP_PREFETCH_ABORT 3
45 #define EXCP_DATA_ABORT 4
46 #define EXCP_IRQ 5
47 #define EXCP_FIQ 6
48 #define EXCP_BKPT 7
49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
51 #define EXCP_HVC 11 /* HyperVisor Call */
52 #define EXCP_HYP_TRAP 12
53 #define EXCP_SMC 13 /* Secure Monitor Call */
54 #define EXCP_VIRQ 14
55 #define EXCP_VFIQ 15
56 #define EXCP_SEMIHOST 16 /* semihosting call */
57 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
58 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
59 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
61
62 #define ARMV7M_EXCP_RESET 1
63 #define ARMV7M_EXCP_NMI 2
64 #define ARMV7M_EXCP_HARD 3
65 #define ARMV7M_EXCP_MEM 4
66 #define ARMV7M_EXCP_BUS 5
67 #define ARMV7M_EXCP_USAGE 6
68 #define ARMV7M_EXCP_SECURE 7
69 #define ARMV7M_EXCP_SVC 11
70 #define ARMV7M_EXCP_DEBUG 12
71 #define ARMV7M_EXCP_PENDSV 14
72 #define ARMV7M_EXCP_SYSTICK 15
73
74 /* For M profile, some registers are banked secure vs non-secure;
75 * these are represented as a 2-element array where the first element
76 * is the non-secure copy and the second is the secure copy.
77 * When the CPU does not have implement the security extension then
78 * only the first element is used.
79 * This means that the copy for the current security state can be
80 * accessed via env->registerfield[env->v7m.secure] (whether the security
81 * extension is implemented or not).
82 */
83 enum {
84 M_REG_NS = 0,
85 M_REG_S = 1,
86 M_REG_NUM_BANKS = 2,
87 };
88
89 /* ARM-specific interrupt pending bits. */
90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
93
94 /* The usual mapping for an AArch64 system register to its AArch32
95 * counterpart is for the 32 bit world to have access to the lower
96 * half only (with writes leaving the upper half untouched). It's
97 * therefore useful to be able to pass TCG the offset of the least
98 * significant half of a uint64_t struct member.
99 */
100 #ifdef HOST_WORDS_BIGENDIAN
101 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
102 #define offsetofhigh32(S, M) offsetof(S, M)
103 #else
104 #define offsetoflow32(S, M) offsetof(S, M)
105 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
106 #endif
107
108 /* Meanings of the ARMCPU object's four inbound GPIO lines */
109 #define ARM_CPU_IRQ 0
110 #define ARM_CPU_FIQ 1
111 #define ARM_CPU_VIRQ 2
112 #define ARM_CPU_VFIQ 3
113
114 #define NB_MMU_MODES 8
115 /* ARM-specific extra insn start words:
116 * 1: Conditional execution bits
117 * 2: Partial exception syndrome for data aborts
118 */
119 #define TARGET_INSN_START_EXTRA_WORDS 2
120
121 /* The 2nd extra word holding syndrome info for data aborts does not use
122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
123 * help the sleb128 encoder do a better job.
124 * When restoring the CPU state, we shift it back up.
125 */
126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
127 #define ARM_INSN_START_WORD2_SHIFT 14
128
129 /* We currently assume float and double are IEEE single and double
130 precision respectively.
131 Doing runtime conversions is tricky because VFP registers may contain
132 integer values (eg. as the result of a FTOSI instruction).
133 s<2n> maps to the least significant half of d<n>
134 s<2n+1> maps to the most significant half of d<n>
135 */
136
137 /**
138 * DynamicGDBXMLInfo:
139 * @desc: Contains the XML descriptions.
140 * @num_cpregs: Number of the Coprocessor registers seen by GDB.
141 * @cpregs_keys: Array that contains the corresponding Key of
142 * a given cpreg with the same order of the cpreg in the XML description.
143 */
144 typedef struct DynamicGDBXMLInfo {
145 char *desc;
146 int num_cpregs;
147 uint32_t *cpregs_keys;
148 } DynamicGDBXMLInfo;
149
150 /* CPU state for each instance of a generic timer (in cp15 c14) */
151 typedef struct ARMGenericTimer {
152 uint64_t cval; /* Timer CompareValue register */
153 uint64_t ctl; /* Timer Control register */
154 } ARMGenericTimer;
155
156 #define GTIMER_PHYS 0
157 #define GTIMER_VIRT 1
158 #define GTIMER_HYP 2
159 #define GTIMER_SEC 3
160 #define NUM_GTIMERS 4
161
162 typedef struct {
163 uint64_t raw_tcr;
164 uint32_t mask;
165 uint32_t base_mask;
166 } TCR;
167
168 /* Define a maximum sized vector register.
169 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
170 * For 64-bit, this is a 2048-bit SVE register.
171 *
172 * Note that the mapping between S, D, and Q views of the register bank
173 * differs between AArch64 and AArch32.
174 * In AArch32:
175 * Qn = regs[n].d[1]:regs[n].d[0]
176 * Dn = regs[n / 2].d[n & 1]
177 * Sn = regs[n / 4].d[n % 4 / 2],
178 * bits 31..0 for even n, and bits 63..32 for odd n
179 * (and regs[16] to regs[31] are inaccessible)
180 * In AArch64:
181 * Zn = regs[n].d[*]
182 * Qn = regs[n].d[1]:regs[n].d[0]
183 * Dn = regs[n].d[0]
184 * Sn = regs[n].d[0] bits 31..0
185 * Hn = regs[n].d[0] bits 15..0
186 *
187 * This corresponds to the architecturally defined mapping between
188 * the two execution states, and means we do not need to explicitly
189 * map these registers when changing states.
190 *
191 * Align the data for use with TCG host vector operations.
192 */
193
194 #ifdef TARGET_AARCH64
195 # define ARM_MAX_VQ 16
196 #else
197 # define ARM_MAX_VQ 1
198 #endif
199
200 typedef struct ARMVectorReg {
201 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
202 } ARMVectorReg;
203
204 /* In AArch32 mode, predicate registers do not exist at all. */
205 #ifdef TARGET_AARCH64
206 typedef struct ARMPredicateReg {
207 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
208 } ARMPredicateReg;
209 #endif
210
211
212 typedef struct CPUARMState {
213 /* Regs for current mode. */
214 uint32_t regs[16];
215
216 /* 32/64 switch only happens when taking and returning from
217 * exceptions so the overlap semantics are taken care of then
218 * instead of having a complicated union.
219 */
220 /* Regs for A64 mode. */
221 uint64_t xregs[32];
222 uint64_t pc;
223 /* PSTATE isn't an architectural register for ARMv8. However, it is
224 * convenient for us to assemble the underlying state into a 32 bit format
225 * identical to the architectural format used for the SPSR. (This is also
226 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
227 * 'pstate' register are.) Of the PSTATE bits:
228 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
229 * semantics as for AArch32, as described in the comments on each field)
230 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
231 * DAIF (exception masks) are kept in env->daif
232 * all other bits are stored in their correct places in env->pstate
233 */
234 uint32_t pstate;
235 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
236
237 /* Frequently accessed CPSR bits are stored separately for efficiency.
238 This contains all the other bits. Use cpsr_{read,write} to access
239 the whole CPSR. */
240 uint32_t uncached_cpsr;
241 uint32_t spsr;
242
243 /* Banked registers. */
244 uint64_t banked_spsr[8];
245 uint32_t banked_r13[8];
246 uint32_t banked_r14[8];
247
248 /* These hold r8-r12. */
249 uint32_t usr_regs[5];
250 uint32_t fiq_regs[5];
251
252 /* cpsr flag cache for faster execution */
253 uint32_t CF; /* 0 or 1 */
254 uint32_t VF; /* V is the bit 31. All other bits are undefined */
255 uint32_t NF; /* N is bit 31. All other bits are undefined. */
256 uint32_t ZF; /* Z set if zero. */
257 uint32_t QF; /* 0 or 1 */
258 uint32_t GE; /* cpsr[19:16] */
259 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
260 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
261 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
262
263 uint64_t elr_el[4]; /* AArch64 exception link regs */
264 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
265
266 /* System control coprocessor (cp15) */
267 struct {
268 uint32_t c0_cpuid;
269 union { /* Cache size selection */
270 struct {
271 uint64_t _unused_csselr0;
272 uint64_t csselr_ns;
273 uint64_t _unused_csselr1;
274 uint64_t csselr_s;
275 };
276 uint64_t csselr_el[4];
277 };
278 union { /* System control register. */
279 struct {
280 uint64_t _unused_sctlr;
281 uint64_t sctlr_ns;
282 uint64_t hsctlr;
283 uint64_t sctlr_s;
284 };
285 uint64_t sctlr_el[4];
286 };
287 uint64_t cpacr_el1; /* Architectural feature access control register */
288 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
289 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
290 uint64_t sder; /* Secure debug enable register. */
291 uint32_t nsacr; /* Non-secure access control register. */
292 union { /* MMU translation table base 0. */
293 struct {
294 uint64_t _unused_ttbr0_0;
295 uint64_t ttbr0_ns;
296 uint64_t _unused_ttbr0_1;
297 uint64_t ttbr0_s;
298 };
299 uint64_t ttbr0_el[4];
300 };
301 union { /* MMU translation table base 1. */
302 struct {
303 uint64_t _unused_ttbr1_0;
304 uint64_t ttbr1_ns;
305 uint64_t _unused_ttbr1_1;
306 uint64_t ttbr1_s;
307 };
308 uint64_t ttbr1_el[4];
309 };
310 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
311 /* MMU translation table base control. */
312 TCR tcr_el[4];
313 TCR vtcr_el2; /* Virtualization Translation Control. */
314 uint32_t c2_data; /* MPU data cacheable bits. */
315 uint32_t c2_insn; /* MPU instruction cacheable bits. */
316 union { /* MMU domain access control register
317 * MPU write buffer control.
318 */
319 struct {
320 uint64_t dacr_ns;
321 uint64_t dacr_s;
322 };
323 struct {
324 uint64_t dacr32_el2;
325 };
326 };
327 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
328 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
329 uint64_t hcr_el2; /* Hypervisor configuration register */
330 uint64_t scr_el3; /* Secure configuration register. */
331 union { /* Fault status registers. */
332 struct {
333 uint64_t ifsr_ns;
334 uint64_t ifsr_s;
335 };
336 struct {
337 uint64_t ifsr32_el2;
338 };
339 };
340 union {
341 struct {
342 uint64_t _unused_dfsr;
343 uint64_t dfsr_ns;
344 uint64_t hsr;
345 uint64_t dfsr_s;
346 };
347 uint64_t esr_el[4];
348 };
349 uint32_t c6_region[8]; /* MPU base/size registers. */
350 union { /* Fault address registers. */
351 struct {
352 uint64_t _unused_far0;
353 #ifdef HOST_WORDS_BIGENDIAN
354 uint32_t ifar_ns;
355 uint32_t dfar_ns;
356 uint32_t ifar_s;
357 uint32_t dfar_s;
358 #else
359 uint32_t dfar_ns;
360 uint32_t ifar_ns;
361 uint32_t dfar_s;
362 uint32_t ifar_s;
363 #endif
364 uint64_t _unused_far3;
365 };
366 uint64_t far_el[4];
367 };
368 uint64_t hpfar_el2;
369 uint64_t hstr_el2;
370 union { /* Translation result. */
371 struct {
372 uint64_t _unused_par_0;
373 uint64_t par_ns;
374 uint64_t _unused_par_1;
375 uint64_t par_s;
376 };
377 uint64_t par_el[4];
378 };
379
380 uint32_t c9_insn; /* Cache lockdown registers. */
381 uint32_t c9_data;
382 uint64_t c9_pmcr; /* performance monitor control register */
383 uint64_t c9_pmcnten; /* perf monitor counter enables */
384 uint64_t c9_pmovsr; /* perf monitor overflow status */
385 uint64_t c9_pmuserenr; /* perf monitor user enable */
386 uint64_t c9_pmselr; /* perf monitor counter selection register */
387 uint64_t c9_pminten; /* perf monitor interrupt enables */
388 union { /* Memory attribute redirection */
389 struct {
390 #ifdef HOST_WORDS_BIGENDIAN
391 uint64_t _unused_mair_0;
392 uint32_t mair1_ns;
393 uint32_t mair0_ns;
394 uint64_t _unused_mair_1;
395 uint32_t mair1_s;
396 uint32_t mair0_s;
397 #else
398 uint64_t _unused_mair_0;
399 uint32_t mair0_ns;
400 uint32_t mair1_ns;
401 uint64_t _unused_mair_1;
402 uint32_t mair0_s;
403 uint32_t mair1_s;
404 #endif
405 };
406 uint64_t mair_el[4];
407 };
408 union { /* vector base address register */
409 struct {
410 uint64_t _unused_vbar;
411 uint64_t vbar_ns;
412 uint64_t hvbar;
413 uint64_t vbar_s;
414 };
415 uint64_t vbar_el[4];
416 };
417 uint32_t mvbar; /* (monitor) vector base address register */
418 struct { /* FCSE PID. */
419 uint32_t fcseidr_ns;
420 uint32_t fcseidr_s;
421 };
422 union { /* Context ID. */
423 struct {
424 uint64_t _unused_contextidr_0;
425 uint64_t contextidr_ns;
426 uint64_t _unused_contextidr_1;
427 uint64_t contextidr_s;
428 };
429 uint64_t contextidr_el[4];
430 };
431 union { /* User RW Thread register. */
432 struct {
433 uint64_t tpidrurw_ns;
434 uint64_t tpidrprw_ns;
435 uint64_t htpidr;
436 uint64_t _tpidr_el3;
437 };
438 uint64_t tpidr_el[4];
439 };
440 /* The secure banks of these registers don't map anywhere */
441 uint64_t tpidrurw_s;
442 uint64_t tpidrprw_s;
443 uint64_t tpidruro_s;
444
445 union { /* User RO Thread register. */
446 uint64_t tpidruro_ns;
447 uint64_t tpidrro_el[1];
448 };
449 uint64_t c14_cntfrq; /* Counter Frequency register */
450 uint64_t c14_cntkctl; /* Timer Control register */
451 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
452 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
453 ARMGenericTimer c14_timer[NUM_GTIMERS];
454 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
455 uint32_t c15_ticonfig; /* TI925T configuration byte. */
456 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
457 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
458 uint32_t c15_threadid; /* TI debugger thread-ID. */
459 uint32_t c15_config_base_address; /* SCU base address. */
460 uint32_t c15_diagnostic; /* diagnostic register */
461 uint32_t c15_power_diagnostic;
462 uint32_t c15_power_control; /* power control */
463 uint64_t dbgbvr[16]; /* breakpoint value registers */
464 uint64_t dbgbcr[16]; /* breakpoint control registers */
465 uint64_t dbgwvr[16]; /* watchpoint value registers */
466 uint64_t dbgwcr[16]; /* watchpoint control registers */
467 uint64_t mdscr_el1;
468 uint64_t oslsr_el1; /* OS Lock Status */
469 uint64_t mdcr_el2;
470 uint64_t mdcr_el3;
471 /* If the counter is enabled, this stores the last time the counter
472 * was reset. Otherwise it stores the counter value
473 */
474 uint64_t c15_ccnt;
475 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
476 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
477 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
478 } cp15;
479
480 struct {
481 /* M profile has up to 4 stack pointers:
482 * a Main Stack Pointer and a Process Stack Pointer for each
483 * of the Secure and Non-Secure states. (If the CPU doesn't support
484 * the security extension then it has only two SPs.)
485 * In QEMU we always store the currently active SP in regs[13],
486 * and the non-active SP for the current security state in
487 * v7m.other_sp. The stack pointers for the inactive security state
488 * are stored in other_ss_msp and other_ss_psp.
489 * switch_v7m_security_state() is responsible for rearranging them
490 * when we change security state.
491 */
492 uint32_t other_sp;
493 uint32_t other_ss_msp;
494 uint32_t other_ss_psp;
495 uint32_t vecbase[M_REG_NUM_BANKS];
496 uint32_t basepri[M_REG_NUM_BANKS];
497 uint32_t control[M_REG_NUM_BANKS];
498 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
499 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
500 uint32_t hfsr; /* HardFault Status */
501 uint32_t dfsr; /* Debug Fault Status Register */
502 uint32_t sfsr; /* Secure Fault Status Register */
503 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
504 uint32_t bfar; /* BusFault Address */
505 uint32_t sfar; /* Secure Fault Address Register */
506 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
507 int exception;
508 uint32_t primask[M_REG_NUM_BANKS];
509 uint32_t faultmask[M_REG_NUM_BANKS];
510 uint32_t aircr; /* only holds r/w state if security extn implemented */
511 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
512 uint32_t csselr[M_REG_NUM_BANKS];
513 uint32_t scr[M_REG_NUM_BANKS];
514 uint32_t msplim[M_REG_NUM_BANKS];
515 uint32_t psplim[M_REG_NUM_BANKS];
516 } v7m;
517
518 /* Information associated with an exception about to be taken:
519 * code which raises an exception must set cs->exception_index and
520 * the relevant parts of this structure; the cpu_do_interrupt function
521 * will then set the guest-visible registers as part of the exception
522 * entry process.
523 */
524 struct {
525 uint32_t syndrome; /* AArch64 format syndrome register */
526 uint32_t fsr; /* AArch32 format fault status register info */
527 uint64_t vaddress; /* virtual addr associated with exception, if any */
528 uint32_t target_el; /* EL the exception should be targeted for */
529 /* If we implement EL2 we will also need to store information
530 * about the intermediate physical address for stage 2 faults.
531 */
532 } exception;
533
534 /* Thumb-2 EE state. */
535 uint32_t teecr;
536 uint32_t teehbr;
537
538 /* VFP coprocessor state. */
539 struct {
540 ARMVectorReg zregs[32];
541
542 #ifdef TARGET_AARCH64
543 /* Store FFR as pregs[16] to make it easier to treat as any other. */
544 #define FFR_PRED_NUM 16
545 ARMPredicateReg pregs[17];
546 /* Scratch space for aa64 sve predicate temporary. */
547 ARMPredicateReg preg_tmp;
548 #endif
549
550 uint32_t xregs[16];
551 /* We store these fpcsr fields separately for convenience. */
552 int vec_len;
553 int vec_stride;
554
555 /* Scratch space for aa32 neon expansion. */
556 uint32_t scratch[8];
557
558 /* There are a number of distinct float control structures:
559 *
560 * fp_status: is the "normal" fp status.
561 * fp_status_fp16: used for half-precision calculations
562 * standard_fp_status : the ARM "Standard FPSCR Value"
563 *
564 * Half-precision operations are governed by a separate
565 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
566 * status structure to control this.
567 *
568 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
569 * round-to-nearest and is used by any operations (generally
570 * Neon) which the architecture defines as controlled by the
571 * standard FPSCR value rather than the FPSCR.
572 *
573 * To avoid having to transfer exception bits around, we simply
574 * say that the FPSCR cumulative exception flags are the logical
575 * OR of the flags in the three fp statuses. This relies on the
576 * only thing which needs to read the exception flags being
577 * an explicit FPSCR read.
578 */
579 float_status fp_status;
580 float_status fp_status_f16;
581 float_status standard_fp_status;
582
583 /* ZCR_EL[1-3] */
584 uint64_t zcr_el[4];
585 } vfp;
586 uint64_t exclusive_addr;
587 uint64_t exclusive_val;
588 uint64_t exclusive_high;
589
590 /* iwMMXt coprocessor state. */
591 struct {
592 uint64_t regs[16];
593 uint64_t val;
594
595 uint32_t cregs[16];
596 } iwmmxt;
597
598 #if defined(CONFIG_USER_ONLY)
599 /* For usermode syscall translation. */
600 int eabi;
601 #endif
602
603 struct CPUBreakpoint *cpu_breakpoint[16];
604 struct CPUWatchpoint *cpu_watchpoint[16];
605
606 /* Fields up to this point are cleared by a CPU reset */
607 struct {} end_reset_fields;
608
609 CPU_COMMON
610
611 /* Fields after CPU_COMMON are preserved across CPU reset. */
612
613 /* Internal CPU feature flags. */
614 uint64_t features;
615
616 /* PMSAv7 MPU */
617 struct {
618 uint32_t *drbar;
619 uint32_t *drsr;
620 uint32_t *dracr;
621 uint32_t rnr[M_REG_NUM_BANKS];
622 } pmsav7;
623
624 /* PMSAv8 MPU */
625 struct {
626 /* The PMSAv8 implementation also shares some PMSAv7 config
627 * and state:
628 * pmsav7.rnr (region number register)
629 * pmsav7_dregion (number of configured regions)
630 */
631 uint32_t *rbar[M_REG_NUM_BANKS];
632 uint32_t *rlar[M_REG_NUM_BANKS];
633 uint32_t mair0[M_REG_NUM_BANKS];
634 uint32_t mair1[M_REG_NUM_BANKS];
635 } pmsav8;
636
637 /* v8M SAU */
638 struct {
639 uint32_t *rbar;
640 uint32_t *rlar;
641 uint32_t rnr;
642 uint32_t ctrl;
643 } sau;
644
645 void *nvic;
646 const struct arm_boot_info *boot_info;
647 /* Store GICv3CPUState to access from this struct */
648 void *gicv3state;
649 } CPUARMState;
650
651 /**
652 * ARMELChangeHookFn:
653 * type of a function which can be registered via arm_register_el_change_hook()
654 * to get callbacks when the CPU changes its exception level or mode.
655 */
656 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
657 typedef struct ARMELChangeHook ARMELChangeHook;
658 struct ARMELChangeHook {
659 ARMELChangeHookFn *hook;
660 void *opaque;
661 QLIST_ENTRY(ARMELChangeHook) node;
662 };
663
664 /* These values map onto the return values for
665 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
666 typedef enum ARMPSCIState {
667 PSCI_ON = 0,
668 PSCI_OFF = 1,
669 PSCI_ON_PENDING = 2
670 } ARMPSCIState;
671
672 /**
673 * ARMCPU:
674 * @env: #CPUARMState
675 *
676 * An ARM CPU core.
677 */
678 struct ARMCPU {
679 /*< private >*/
680 CPUState parent_obj;
681 /*< public >*/
682
683 CPUARMState env;
684
685 /* Coprocessor information */
686 GHashTable *cp_regs;
687 /* For marshalling (mostly coprocessor) register state between the
688 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
689 * we use these arrays.
690 */
691 /* List of register indexes managed via these arrays; (full KVM style
692 * 64 bit indexes, not CPRegInfo 32 bit indexes)
693 */
694 uint64_t *cpreg_indexes;
695 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
696 uint64_t *cpreg_values;
697 /* Length of the indexes, values, reset_values arrays */
698 int32_t cpreg_array_len;
699 /* These are used only for migration: incoming data arrives in
700 * these fields and is sanity checked in post_load before copying
701 * to the working data structures above.
702 */
703 uint64_t *cpreg_vmstate_indexes;
704 uint64_t *cpreg_vmstate_values;
705 int32_t cpreg_vmstate_array_len;
706
707 DynamicGDBXMLInfo dyn_xml;
708
709 /* Timers used by the generic (architected) timer */
710 QEMUTimer *gt_timer[NUM_GTIMERS];
711 /* GPIO outputs for generic timer */
712 qemu_irq gt_timer_outputs[NUM_GTIMERS];
713 /* GPIO output for GICv3 maintenance interrupt signal */
714 qemu_irq gicv3_maintenance_interrupt;
715 /* GPIO output for the PMU interrupt */
716 qemu_irq pmu_interrupt;
717
718 /* MemoryRegion to use for secure physical accesses */
719 MemoryRegion *secure_memory;
720
721 /* For v8M, pointer to the IDAU interface provided by board/SoC */
722 Object *idau;
723
724 /* 'compatible' string for this CPU for Linux device trees */
725 const char *dtb_compatible;
726
727 /* PSCI version for this CPU
728 * Bits[31:16] = Major Version
729 * Bits[15:0] = Minor Version
730 */
731 uint32_t psci_version;
732
733 /* Should CPU start in PSCI powered-off state? */
734 bool start_powered_off;
735
736 /* Current power state, access guarded by BQL */
737 ARMPSCIState power_state;
738
739 /* CPU has virtualization extension */
740 bool has_el2;
741 /* CPU has security extension */
742 bool has_el3;
743 /* CPU has PMU (Performance Monitor Unit) */
744 bool has_pmu;
745
746 /* CPU has memory protection unit */
747 bool has_mpu;
748 /* PMSAv7 MPU number of supported regions */
749 uint32_t pmsav7_dregion;
750 /* v8M SAU number of supported regions */
751 uint32_t sau_sregion;
752
753 /* PSCI conduit used to invoke PSCI methods
754 * 0 - disabled, 1 - smc, 2 - hvc
755 */
756 uint32_t psci_conduit;
757
758 /* For v8M, initial value of the Secure VTOR */
759 uint32_t init_svtor;
760
761 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
762 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
763 */
764 uint32_t kvm_target;
765
766 /* KVM init features for this CPU */
767 uint32_t kvm_init_features[7];
768
769 /* Uniprocessor system with MP extensions */
770 bool mp_is_up;
771
772 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
773 * and the probe failed (so we need to report the error in realize)
774 */
775 bool host_cpu_probe_failed;
776
777 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
778 * register.
779 */
780 int32_t core_count;
781
782 /* The instance init functions for implementation-specific subclasses
783 * set these fields to specify the implementation-dependent values of
784 * various constant registers and reset values of non-constant
785 * registers.
786 * Some of these might become QOM properties eventually.
787 * Field names match the official register names as defined in the
788 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
789 * is used for reset values of non-constant registers; no reset_
790 * prefix means a constant register.
791 */
792 uint32_t midr;
793 uint32_t revidr;
794 uint32_t reset_fpsid;
795 uint32_t mvfr0;
796 uint32_t mvfr1;
797 uint32_t mvfr2;
798 uint32_t ctr;
799 uint32_t reset_sctlr;
800 uint32_t id_pfr0;
801 uint32_t id_pfr1;
802 uint32_t id_dfr0;
803 uint32_t pmceid0;
804 uint32_t pmceid1;
805 uint32_t id_afr0;
806 uint32_t id_mmfr0;
807 uint32_t id_mmfr1;
808 uint32_t id_mmfr2;
809 uint32_t id_mmfr3;
810 uint32_t id_mmfr4;
811 uint32_t id_isar0;
812 uint32_t id_isar1;
813 uint32_t id_isar2;
814 uint32_t id_isar3;
815 uint32_t id_isar4;
816 uint32_t id_isar5;
817 uint32_t id_isar6;
818 uint64_t id_aa64pfr0;
819 uint64_t id_aa64pfr1;
820 uint64_t id_aa64dfr0;
821 uint64_t id_aa64dfr1;
822 uint64_t id_aa64afr0;
823 uint64_t id_aa64afr1;
824 uint64_t id_aa64isar0;
825 uint64_t id_aa64isar1;
826 uint64_t id_aa64mmfr0;
827 uint64_t id_aa64mmfr1;
828 uint32_t dbgdidr;
829 uint32_t clidr;
830 uint64_t mp_affinity; /* MP ID without feature bits */
831 /* The elements of this array are the CCSIDR values for each cache,
832 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
833 */
834 uint32_t ccsidr[16];
835 uint64_t reset_cbar;
836 uint32_t reset_auxcr;
837 bool reset_hivecs;
838 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
839 uint32_t dcz_blocksize;
840 uint64_t rvbar;
841
842 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
843 int gic_num_lrs; /* number of list registers */
844 int gic_vpribits; /* number of virtual priority bits */
845 int gic_vprebits; /* number of virtual preemption bits */
846
847 /* Whether the cfgend input is high (i.e. this CPU should reset into
848 * big-endian mode). This setting isn't used directly: instead it modifies
849 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
850 * architecture version.
851 */
852 bool cfgend;
853
854 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
855 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
856
857 int32_t node_id; /* NUMA node this CPU belongs to */
858
859 /* Used to synchronize KVM and QEMU in-kernel device levels */
860 uint8_t device_irq_level;
861
862 /* Used to set the maximum vector length the cpu will support. */
863 uint32_t sve_max_vq;
864 };
865
arm_env_get_cpu(CPUARMState * env)866 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
867 {
868 return container_of(env, ARMCPU, env);
869 }
870
871 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
872
873 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
874
875 #define ENV_OFFSET offsetof(ARMCPU, env)
876
877 #ifndef CONFIG_USER_ONLY
878 extern const struct VMStateDescription vmstate_arm_cpu;
879 #endif
880
881 void arm_cpu_do_interrupt(CPUState *cpu);
882 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
883 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
884
885 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
886 int flags);
887
888 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
889 MemTxAttrs *attrs);
890
891 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
892 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
893
894 /* Dynamically generates for gdb stub an XML description of the sysregs from
895 * the cp_regs hashtable. Returns the registered sysregs number.
896 */
897 int arm_gen_dynamic_xml(CPUState *cpu);
898
899 /* Returns the dynamically generated XML for the gdb stub.
900 * Returns a pointer to the XML contents for the specified XML file or NULL
901 * if the XML name doesn't match the predefined one.
902 */
903 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
904
905 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
906 int cpuid, void *opaque);
907 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
908 int cpuid, void *opaque);
909
910 #ifdef TARGET_AARCH64
911 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
912 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
913 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
914 void aarch64_sve_change_el(CPUARMState *env, int old_el,
915 int new_el, bool el0_a64);
916 #else
aarch64_sve_narrow_vq(CPUARMState * env,unsigned vq)917 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
aarch64_sve_change_el(CPUARMState * env,int o,int n,bool a)918 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
919 int n, bool a)
920 { }
921 #endif
922
923 target_ulong do_arm_semihosting(CPUARMState *env);
924 void aarch64_sync_32_to_64(CPUARMState *env);
925 void aarch64_sync_64_to_32(CPUARMState *env);
926
927 int fp_exception_el(CPUARMState *env, int cur_el);
928 int sve_exception_el(CPUARMState *env, int cur_el);
929 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
930
is_a64(CPUARMState * env)931 static inline bool is_a64(CPUARMState *env)
932 {
933 return env->aarch64;
934 }
935
936 /* you can call this signal handler from your SIGBUS and SIGSEGV
937 signal handlers to inform the virtual CPU of exceptions. non zero
938 is returned if the signal was handled by the virtual CPU. */
939 int cpu_arm_signal_handler(int host_signum, void *pinfo,
940 void *puc);
941
942 /**
943 * pmccntr_sync
944 * @env: CPUARMState
945 *
946 * Synchronises the counter in the PMCCNTR. This must always be called twice,
947 * once before any action that might affect the timer and again afterwards.
948 * The function is used to swap the state of the register if required.
949 * This only happens when not in user mode (!CONFIG_USER_ONLY)
950 */
951 void pmccntr_sync(CPUARMState *env);
952
953 /* SCTLR bit meanings. Several bits have been reused in newer
954 * versions of the architecture; in that case we define constants
955 * for both old and new bit meanings. Code which tests against those
956 * bits should probably check or otherwise arrange that the CPU
957 * is the architectural version it expects.
958 */
959 #define SCTLR_M (1U << 0)
960 #define SCTLR_A (1U << 1)
961 #define SCTLR_C (1U << 2)
962 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
963 #define SCTLR_SA (1U << 3)
964 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
965 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
966 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
967 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
968 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
969 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
970 #define SCTLR_ITD (1U << 7) /* v8 onward */
971 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
972 #define SCTLR_SED (1U << 8) /* v8 onward */
973 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
974 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
975 #define SCTLR_F (1U << 10) /* up to v6 */
976 #define SCTLR_SW (1U << 10) /* v7 onward */
977 #define SCTLR_Z (1U << 11)
978 #define SCTLR_I (1U << 12)
979 #define SCTLR_V (1U << 13)
980 #define SCTLR_RR (1U << 14) /* up to v7 */
981 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
982 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
983 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
984 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
985 #define SCTLR_nTWI (1U << 16) /* v8 onward */
986 #define SCTLR_HA (1U << 17)
987 #define SCTLR_BR (1U << 17) /* PMSA only */
988 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
989 #define SCTLR_nTWE (1U << 18) /* v8 onward */
990 #define SCTLR_WXN (1U << 19)
991 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
992 #define SCTLR_UWXN (1U << 20) /* v7 onward */
993 #define SCTLR_FI (1U << 21)
994 #define SCTLR_U (1U << 22)
995 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
996 #define SCTLR_VE (1U << 24) /* up to v7 */
997 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
998 #define SCTLR_EE (1U << 25)
999 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1000 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1001 #define SCTLR_NMFI (1U << 27)
1002 #define SCTLR_TRE (1U << 28)
1003 #define SCTLR_AFE (1U << 29)
1004 #define SCTLR_TE (1U << 30)
1005
1006 #define CPTR_TCPAC (1U << 31)
1007 #define CPTR_TTA (1U << 20)
1008 #define CPTR_TFP (1U << 10)
1009 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
1010 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
1011
1012 #define MDCR_EPMAD (1U << 21)
1013 #define MDCR_EDAD (1U << 20)
1014 #define MDCR_SPME (1U << 17)
1015 #define MDCR_SDD (1U << 16)
1016 #define MDCR_SPD (3U << 14)
1017 #define MDCR_TDRA (1U << 11)
1018 #define MDCR_TDOSA (1U << 10)
1019 #define MDCR_TDA (1U << 9)
1020 #define MDCR_TDE (1U << 8)
1021 #define MDCR_HPME (1U << 7)
1022 #define MDCR_TPM (1U << 6)
1023 #define MDCR_TPMCR (1U << 5)
1024
1025 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1026 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1027
1028 #define CPSR_M (0x1fU)
1029 #define CPSR_T (1U << 5)
1030 #define CPSR_F (1U << 6)
1031 #define CPSR_I (1U << 7)
1032 #define CPSR_A (1U << 8)
1033 #define CPSR_E (1U << 9)
1034 #define CPSR_IT_2_7 (0xfc00U)
1035 #define CPSR_GE (0xfU << 16)
1036 #define CPSR_IL (1U << 20)
1037 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
1038 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
1039 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
1040 * where it is live state but not accessible to the AArch32 code.
1041 */
1042 #define CPSR_RESERVED (0x7U << 21)
1043 #define CPSR_J (1U << 24)
1044 #define CPSR_IT_0_1 (3U << 25)
1045 #define CPSR_Q (1U << 27)
1046 #define CPSR_V (1U << 28)
1047 #define CPSR_C (1U << 29)
1048 #define CPSR_Z (1U << 30)
1049 #define CPSR_N (1U << 31)
1050 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1051 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1052
1053 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1054 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1055 | CPSR_NZCV)
1056 /* Bits writable in user mode. */
1057 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1058 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1059 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1060 /* Mask of bits which may be set by exception return copying them from SPSR */
1061 #define CPSR_ERET_MASK (~CPSR_RESERVED)
1062
1063 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1064 #define XPSR_EXCP 0x1ffU
1065 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1066 #define XPSR_IT_2_7 CPSR_IT_2_7
1067 #define XPSR_GE CPSR_GE
1068 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1069 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1070 #define XPSR_IT_0_1 CPSR_IT_0_1
1071 #define XPSR_Q CPSR_Q
1072 #define XPSR_V CPSR_V
1073 #define XPSR_C CPSR_C
1074 #define XPSR_Z CPSR_Z
1075 #define XPSR_N CPSR_N
1076 #define XPSR_NZCV CPSR_NZCV
1077 #define XPSR_IT CPSR_IT
1078
1079 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1080 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1081 #define TTBCR_PD0 (1U << 4)
1082 #define TTBCR_PD1 (1U << 5)
1083 #define TTBCR_EPD0 (1U << 7)
1084 #define TTBCR_IRGN0 (3U << 8)
1085 #define TTBCR_ORGN0 (3U << 10)
1086 #define TTBCR_SH0 (3U << 12)
1087 #define TTBCR_T1SZ (3U << 16)
1088 #define TTBCR_A1 (1U << 22)
1089 #define TTBCR_EPD1 (1U << 23)
1090 #define TTBCR_IRGN1 (3U << 24)
1091 #define TTBCR_ORGN1 (3U << 26)
1092 #define TTBCR_SH1 (1U << 28)
1093 #define TTBCR_EAE (1U << 31)
1094
1095 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1096 * Only these are valid when in AArch64 mode; in
1097 * AArch32 mode SPSRs are basically CPSR-format.
1098 */
1099 #define PSTATE_SP (1U)
1100 #define PSTATE_M (0xFU)
1101 #define PSTATE_nRW (1U << 4)
1102 #define PSTATE_F (1U << 6)
1103 #define PSTATE_I (1U << 7)
1104 #define PSTATE_A (1U << 8)
1105 #define PSTATE_D (1U << 9)
1106 #define PSTATE_IL (1U << 20)
1107 #define PSTATE_SS (1U << 21)
1108 #define PSTATE_V (1U << 28)
1109 #define PSTATE_C (1U << 29)
1110 #define PSTATE_Z (1U << 30)
1111 #define PSTATE_N (1U << 31)
1112 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1113 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1114 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
1115 /* Mode values for AArch64 */
1116 #define PSTATE_MODE_EL3h 13
1117 #define PSTATE_MODE_EL3t 12
1118 #define PSTATE_MODE_EL2h 9
1119 #define PSTATE_MODE_EL2t 8
1120 #define PSTATE_MODE_EL1h 5
1121 #define PSTATE_MODE_EL1t 4
1122 #define PSTATE_MODE_EL0t 0
1123
1124 /* Write a new value to v7m.exception, thus transitioning into or out
1125 * of Handler mode; this may result in a change of active stack pointer.
1126 */
1127 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1128
1129 /* Map EL and handler into a PSTATE_MODE. */
aarch64_pstate_mode(unsigned int el,bool handler)1130 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1131 {
1132 return (el << 2) | handler;
1133 }
1134
1135 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1136 * interprocessing, so we don't attempt to sync with the cpsr state used by
1137 * the 32 bit decoder.
1138 */
pstate_read(CPUARMState * env)1139 static inline uint32_t pstate_read(CPUARMState *env)
1140 {
1141 int ZF;
1142
1143 ZF = (env->ZF == 0);
1144 return (env->NF & 0x80000000) | (ZF << 30)
1145 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1146 | env->pstate | env->daif;
1147 }
1148
pstate_write(CPUARMState * env,uint32_t val)1149 static inline void pstate_write(CPUARMState *env, uint32_t val)
1150 {
1151 env->ZF = (~val) & PSTATE_Z;
1152 env->NF = val;
1153 env->CF = (val >> 29) & 1;
1154 env->VF = (val << 3) & 0x80000000;
1155 env->daif = val & PSTATE_DAIF;
1156 env->pstate = val & ~CACHED_PSTATE_BITS;
1157 }
1158
1159 /* Return the current CPSR value. */
1160 uint32_t cpsr_read(CPUARMState *env);
1161
1162 typedef enum CPSRWriteType {
1163 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1164 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1165 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
1166 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1167 } CPSRWriteType;
1168
1169 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1170 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1171 CPSRWriteType write_type);
1172
1173 /* Return the current xPSR value. */
xpsr_read(CPUARMState * env)1174 static inline uint32_t xpsr_read(CPUARMState *env)
1175 {
1176 int ZF;
1177 ZF = (env->ZF == 0);
1178 return (env->NF & 0x80000000) | (ZF << 30)
1179 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1180 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1181 | ((env->condexec_bits & 0xfc) << 8)
1182 | env->v7m.exception;
1183 }
1184
1185 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
xpsr_write(CPUARMState * env,uint32_t val,uint32_t mask)1186 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1187 {
1188 if (mask & XPSR_NZCV) {
1189 env->ZF = (~val) & XPSR_Z;
1190 env->NF = val;
1191 env->CF = (val >> 29) & 1;
1192 env->VF = (val << 3) & 0x80000000;
1193 }
1194 if (mask & XPSR_Q) {
1195 env->QF = ((val & XPSR_Q) != 0);
1196 }
1197 if (mask & XPSR_T) {
1198 env->thumb = ((val & XPSR_T) != 0);
1199 }
1200 if (mask & XPSR_IT_0_1) {
1201 env->condexec_bits &= ~3;
1202 env->condexec_bits |= (val >> 25) & 3;
1203 }
1204 if (mask & XPSR_IT_2_7) {
1205 env->condexec_bits &= 3;
1206 env->condexec_bits |= (val >> 8) & 0xfc;
1207 }
1208 if (mask & XPSR_EXCP) {
1209 /* Note that this only happens on exception exit */
1210 write_v7m_exception(env, val & XPSR_EXCP);
1211 }
1212 }
1213
1214 #define HCR_VM (1ULL << 0)
1215 #define HCR_SWIO (1ULL << 1)
1216 #define HCR_PTW (1ULL << 2)
1217 #define HCR_FMO (1ULL << 3)
1218 #define HCR_IMO (1ULL << 4)
1219 #define HCR_AMO (1ULL << 5)
1220 #define HCR_VF (1ULL << 6)
1221 #define HCR_VI (1ULL << 7)
1222 #define HCR_VSE (1ULL << 8)
1223 #define HCR_FB (1ULL << 9)
1224 #define HCR_BSU_MASK (3ULL << 10)
1225 #define HCR_DC (1ULL << 12)
1226 #define HCR_TWI (1ULL << 13)
1227 #define HCR_TWE (1ULL << 14)
1228 #define HCR_TID0 (1ULL << 15)
1229 #define HCR_TID1 (1ULL << 16)
1230 #define HCR_TID2 (1ULL << 17)
1231 #define HCR_TID3 (1ULL << 18)
1232 #define HCR_TSC (1ULL << 19)
1233 #define HCR_TIDCP (1ULL << 20)
1234 #define HCR_TACR (1ULL << 21)
1235 #define HCR_TSW (1ULL << 22)
1236 #define HCR_TPC (1ULL << 23)
1237 #define HCR_TPU (1ULL << 24)
1238 #define HCR_TTLB (1ULL << 25)
1239 #define HCR_TVM (1ULL << 26)
1240 #define HCR_TGE (1ULL << 27)
1241 #define HCR_TDZ (1ULL << 28)
1242 #define HCR_HCD (1ULL << 29)
1243 #define HCR_TRVM (1ULL << 30)
1244 #define HCR_RW (1ULL << 31)
1245 #define HCR_CD (1ULL << 32)
1246 #define HCR_ID (1ULL << 33)
1247 #define HCR_E2H (1ULL << 34)
1248 /*
1249 * When we actually implement ARMv8.1-VHE we should add HCR_E2H to
1250 * HCR_MASK and then clear it again if the feature bit is not set in
1251 * hcr_write().
1252 */
1253 #define HCR_MASK ((1ULL << 34) - 1)
1254
1255 #define SCR_NS (1U << 0)
1256 #define SCR_IRQ (1U << 1)
1257 #define SCR_FIQ (1U << 2)
1258 #define SCR_EA (1U << 3)
1259 #define SCR_FW (1U << 4)
1260 #define SCR_AW (1U << 5)
1261 #define SCR_NET (1U << 6)
1262 #define SCR_SMD (1U << 7)
1263 #define SCR_HCE (1U << 8)
1264 #define SCR_SIF (1U << 9)
1265 #define SCR_RW (1U << 10)
1266 #define SCR_ST (1U << 11)
1267 #define SCR_TWI (1U << 12)
1268 #define SCR_TWE (1U << 13)
1269 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1270 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1271
1272 /* Return the current FPSCR value. */
1273 uint32_t vfp_get_fpscr(CPUARMState *env);
1274 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1275
1276 /* FPCR, Floating Point Control Register
1277 * FPSR, Floating Poiht Status Register
1278 *
1279 * For A64 the FPSCR is split into two logically distinct registers,
1280 * FPCR and FPSR. However since they still use non-overlapping bits
1281 * we store the underlying state in fpscr and just mask on read/write.
1282 */
1283 #define FPSR_MASK 0xf800009f
1284 #define FPCR_MASK 0x07ff9f00
1285
1286 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1287 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1288 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1289
vfp_get_fpsr(CPUARMState * env)1290 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1291 {
1292 return vfp_get_fpscr(env) & FPSR_MASK;
1293 }
1294
vfp_set_fpsr(CPUARMState * env,uint32_t val)1295 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1296 {
1297 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1298 vfp_set_fpscr(env, new_fpscr);
1299 }
1300
vfp_get_fpcr(CPUARMState * env)1301 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1302 {
1303 return vfp_get_fpscr(env) & FPCR_MASK;
1304 }
1305
vfp_set_fpcr(CPUARMState * env,uint32_t val)1306 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1307 {
1308 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1309 vfp_set_fpscr(env, new_fpscr);
1310 }
1311
1312 enum arm_cpu_mode {
1313 ARM_CPU_MODE_USR = 0x10,
1314 ARM_CPU_MODE_FIQ = 0x11,
1315 ARM_CPU_MODE_IRQ = 0x12,
1316 ARM_CPU_MODE_SVC = 0x13,
1317 ARM_CPU_MODE_MON = 0x16,
1318 ARM_CPU_MODE_ABT = 0x17,
1319 ARM_CPU_MODE_HYP = 0x1a,
1320 ARM_CPU_MODE_UND = 0x1b,
1321 ARM_CPU_MODE_SYS = 0x1f
1322 };
1323
1324 /* VFP system registers. */
1325 #define ARM_VFP_FPSID 0
1326 #define ARM_VFP_FPSCR 1
1327 #define ARM_VFP_MVFR2 5
1328 #define ARM_VFP_MVFR1 6
1329 #define ARM_VFP_MVFR0 7
1330 #define ARM_VFP_FPEXC 8
1331 #define ARM_VFP_FPINST 9
1332 #define ARM_VFP_FPINST2 10
1333
1334 /* iwMMXt coprocessor control registers. */
1335 #define ARM_IWMMXT_wCID 0
1336 #define ARM_IWMMXT_wCon 1
1337 #define ARM_IWMMXT_wCSSF 2
1338 #define ARM_IWMMXT_wCASF 3
1339 #define ARM_IWMMXT_wCGR0 8
1340 #define ARM_IWMMXT_wCGR1 9
1341 #define ARM_IWMMXT_wCGR2 10
1342 #define ARM_IWMMXT_wCGR3 11
1343
1344 /* V7M CCR bits */
1345 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1346 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1347 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1348 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1349 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1350 FIELD(V7M_CCR, STKALIGN, 9, 1)
1351 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1352 FIELD(V7M_CCR, DC, 16, 1)
1353 FIELD(V7M_CCR, IC, 17, 1)
1354 FIELD(V7M_CCR, BP, 18, 1)
1355
1356 /* V7M SCR bits */
1357 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1358 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1359 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1360 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1361
1362 /* V7M AIRCR bits */
1363 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1364 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1365 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1366 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1367 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1368 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1369 FIELD(V7M_AIRCR, PRIS, 14, 1)
1370 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1371 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1372
1373 /* V7M CFSR bits for MMFSR */
1374 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1375 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1376 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1377 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1378 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1379 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1380
1381 /* V7M CFSR bits for BFSR */
1382 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1383 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1384 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1385 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1386 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1387 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1388 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1389
1390 /* V7M CFSR bits for UFSR */
1391 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1392 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1393 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1394 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1395 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1396 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1397 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1398
1399 /* V7M CFSR bit masks covering all of the subregister bits */
1400 FIELD(V7M_CFSR, MMFSR, 0, 8)
1401 FIELD(V7M_CFSR, BFSR, 8, 8)
1402 FIELD(V7M_CFSR, UFSR, 16, 16)
1403
1404 /* V7M HFSR bits */
1405 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1406 FIELD(V7M_HFSR, FORCED, 30, 1)
1407 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1408
1409 /* V7M DFSR bits */
1410 FIELD(V7M_DFSR, HALTED, 0, 1)
1411 FIELD(V7M_DFSR, BKPT, 1, 1)
1412 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1413 FIELD(V7M_DFSR, VCATCH, 3, 1)
1414 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1415
1416 /* V7M SFSR bits */
1417 FIELD(V7M_SFSR, INVEP, 0, 1)
1418 FIELD(V7M_SFSR, INVIS, 1, 1)
1419 FIELD(V7M_SFSR, INVER, 2, 1)
1420 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1421 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1422 FIELD(V7M_SFSR, LSPERR, 5, 1)
1423 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1424 FIELD(V7M_SFSR, LSERR, 7, 1)
1425
1426 /* v7M MPU_CTRL bits */
1427 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1428 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1429 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1430
1431 /* v7M CLIDR bits */
1432 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1433 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1434 FIELD(V7M_CLIDR, LOC, 24, 3)
1435 FIELD(V7M_CLIDR, LOUU, 27, 3)
1436 FIELD(V7M_CLIDR, ICB, 30, 2)
1437
1438 FIELD(V7M_CSSELR, IND, 0, 1)
1439 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1440 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1441 * define a mask for this and check that it doesn't permit running off
1442 * the end of the array.
1443 */
1444 FIELD(V7M_CSSELR, INDEX, 0, 4)
1445
1446 /*
1447 * System register ID fields.
1448 */
1449 FIELD(ID_ISAR0, SWAP, 0, 4)
1450 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1451 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1452 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1453 FIELD(ID_ISAR0, COPROC, 16, 4)
1454 FIELD(ID_ISAR0, DEBUG, 20, 4)
1455 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1456
1457 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1458 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1459 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1460 FIELD(ID_ISAR1, EXTEND, 12, 4)
1461 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1462 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1463 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1464 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1465
1466 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1467 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1468 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1469 FIELD(ID_ISAR2, MULT, 12, 4)
1470 FIELD(ID_ISAR2, MULTS, 16, 4)
1471 FIELD(ID_ISAR2, MULTU, 20, 4)
1472 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1473 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1474
1475 FIELD(ID_ISAR3, SATURATE, 0, 4)
1476 FIELD(ID_ISAR3, SIMD, 4, 4)
1477 FIELD(ID_ISAR3, SVC, 8, 4)
1478 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1479 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1480 FIELD(ID_ISAR3, T32COPY, 20, 4)
1481 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1482 FIELD(ID_ISAR3, T32EE, 28, 4)
1483
1484 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1485 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1486 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1487 FIELD(ID_ISAR4, SMC, 12, 4)
1488 FIELD(ID_ISAR4, BARRIER, 16, 4)
1489 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1490 FIELD(ID_ISAR4, PSR_M, 24, 4)
1491 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1492
1493 FIELD(ID_ISAR5, SEVL, 0, 4)
1494 FIELD(ID_ISAR5, AES, 4, 4)
1495 FIELD(ID_ISAR5, SHA1, 8, 4)
1496 FIELD(ID_ISAR5, SHA2, 12, 4)
1497 FIELD(ID_ISAR5, CRC32, 16, 4)
1498 FIELD(ID_ISAR5, RDM, 24, 4)
1499 FIELD(ID_ISAR5, VCMA, 28, 4)
1500
1501 FIELD(ID_ISAR6, JSCVT, 0, 4)
1502 FIELD(ID_ISAR6, DP, 4, 4)
1503 FIELD(ID_ISAR6, FHM, 8, 4)
1504 FIELD(ID_ISAR6, SB, 12, 4)
1505 FIELD(ID_ISAR6, SPECRES, 16, 4)
1506
1507 FIELD(ID_AA64ISAR0, AES, 4, 4)
1508 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1509 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1510 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1511 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1512 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1513 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1514 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1515 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1516 FIELD(ID_AA64ISAR0, DP, 44, 4)
1517 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1518 FIELD(ID_AA64ISAR0, TS, 52, 4)
1519 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1520 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1521
1522 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1523 FIELD(ID_AA64ISAR1, APA, 4, 4)
1524 FIELD(ID_AA64ISAR1, API, 8, 4)
1525 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1526 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1527 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1528 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1529 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1530 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1531 FIELD(ID_AA64ISAR1, SB, 36, 4)
1532 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1533
1534 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1535
1536 /* If adding a feature bit which corresponds to a Linux ELF
1537 * HWCAP bit, remember to update the feature-bit-to-hwcap
1538 * mapping in linux-user/elfload.c:get_elf_hwcap().
1539 */
1540 enum arm_features {
1541 ARM_FEATURE_VFP,
1542 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1543 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1544 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1545 ARM_FEATURE_V6,
1546 ARM_FEATURE_V6K,
1547 ARM_FEATURE_V7,
1548 ARM_FEATURE_THUMB2,
1549 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
1550 ARM_FEATURE_VFP3,
1551 ARM_FEATURE_VFP_FP16,
1552 ARM_FEATURE_NEON,
1553 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
1554 ARM_FEATURE_M, /* Microcontroller profile. */
1555 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1556 ARM_FEATURE_THUMB2EE,
1557 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1558 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1559 ARM_FEATURE_V4T,
1560 ARM_FEATURE_V5,
1561 ARM_FEATURE_STRONGARM,
1562 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1563 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
1564 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
1565 ARM_FEATURE_GENERIC_TIMER,
1566 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1567 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1568 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1569 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1570 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1571 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1572 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1573 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1574 ARM_FEATURE_V8,
1575 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1576 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
1577 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1578 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1579 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1580 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1581 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1582 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
1583 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
1584 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
1585 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1586 ARM_FEATURE_PMU, /* has PMU support */
1587 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1588 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1589 ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
1590 ARM_FEATURE_SVE, /* has Scalable Vector Extension */
1591 ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */
1592 ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
1593 ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
1594 ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
1595 ARM_FEATURE_V8_ATOMICS, /* ARMv8.1-Atomics feature */
1596 ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
1597 ARM_FEATURE_V8_DOTPROD, /* implements v8.2 simd dot product */
1598 ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
1599 ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */
1600 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1601 };
1602
arm_feature(CPUARMState * env,int feature)1603 static inline int arm_feature(CPUARMState *env, int feature)
1604 {
1605 return (env->features & (1ULL << feature)) != 0;
1606 }
1607
1608 #if !defined(CONFIG_USER_ONLY)
1609 /* Return true if exception levels below EL3 are in secure state,
1610 * or would be following an exception return to that level.
1611 * Unlike arm_is_secure() (which is always a question about the
1612 * _current_ state of the CPU) this doesn't care about the current
1613 * EL or mode.
1614 */
arm_is_secure_below_el3(CPUARMState * env)1615 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1616 {
1617 if (arm_feature(env, ARM_FEATURE_EL3)) {
1618 return !(env->cp15.scr_el3 & SCR_NS);
1619 } else {
1620 /* If EL3 is not supported then the secure state is implementation
1621 * defined, in which case QEMU defaults to non-secure.
1622 */
1623 return false;
1624 }
1625 }
1626
1627 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
arm_is_el3_or_mon(CPUARMState * env)1628 static inline bool arm_is_el3_or_mon(CPUARMState *env)
1629 {
1630 if (arm_feature(env, ARM_FEATURE_EL3)) {
1631 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1632 /* CPU currently in AArch64 state and EL3 */
1633 return true;
1634 } else if (!is_a64(env) &&
1635 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1636 /* CPU currently in AArch32 state and monitor mode */
1637 return true;
1638 }
1639 }
1640 return false;
1641 }
1642
1643 /* Return true if the processor is in secure state */
arm_is_secure(CPUARMState * env)1644 static inline bool arm_is_secure(CPUARMState *env)
1645 {
1646 if (arm_is_el3_or_mon(env)) {
1647 return true;
1648 }
1649 return arm_is_secure_below_el3(env);
1650 }
1651
1652 #else
arm_is_secure_below_el3(CPUARMState * env)1653 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1654 {
1655 return false;
1656 }
1657
arm_is_secure(CPUARMState * env)1658 static inline bool arm_is_secure(CPUARMState *env)
1659 {
1660 return false;
1661 }
1662 #endif
1663
1664 /* Return true if the specified exception level is running in AArch64 state. */
arm_el_is_aa64(CPUARMState * env,int el)1665 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1666 {
1667 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1668 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1669 */
1670 assert(el >= 1 && el <= 3);
1671 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1672
1673 /* The highest exception level is always at the maximum supported
1674 * register width, and then lower levels have a register width controlled
1675 * by bits in the SCR or HCR registers.
1676 */
1677 if (el == 3) {
1678 return aa64;
1679 }
1680
1681 if (arm_feature(env, ARM_FEATURE_EL3)) {
1682 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1683 }
1684
1685 if (el == 2) {
1686 return aa64;
1687 }
1688
1689 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1690 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1691 }
1692
1693 return aa64;
1694 }
1695
1696 /* Function for determing whether guest cp register reads and writes should
1697 * access the secure or non-secure bank of a cp register. When EL3 is
1698 * operating in AArch32 state, the NS-bit determines whether the secure
1699 * instance of a cp register should be used. When EL3 is AArch64 (or if
1700 * it doesn't exist at all) then there is no register banking, and all
1701 * accesses are to the non-secure version.
1702 */
access_secure_reg(CPUARMState * env)1703 static inline bool access_secure_reg(CPUARMState *env)
1704 {
1705 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1706 !arm_el_is_aa64(env, 3) &&
1707 !(env->cp15.scr_el3 & SCR_NS));
1708
1709 return ret;
1710 }
1711
1712 /* Macros for accessing a specified CP register bank */
1713 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1714 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1715
1716 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1717 do { \
1718 if (_secure) { \
1719 (_env)->cp15._regname##_s = (_val); \
1720 } else { \
1721 (_env)->cp15._regname##_ns = (_val); \
1722 } \
1723 } while (0)
1724
1725 /* Macros for automatically accessing a specific CP register bank depending on
1726 * the current secure state of the system. These macros are not intended for
1727 * supporting instruction translation reads/writes as these are dependent
1728 * solely on the SCR.NS bit and not the mode.
1729 */
1730 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1731 A32_BANKED_REG_GET((_env), _regname, \
1732 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1733
1734 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1735 A32_BANKED_REG_SET((_env), _regname, \
1736 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1737 (_val))
1738
1739 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1740 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1741 uint32_t cur_el, bool secure);
1742
1743 /* Interface between CPU and Interrupt controller. */
1744 #ifndef CONFIG_USER_ONLY
1745 bool armv7m_nvic_can_take_pending_exception(void *opaque);
1746 #else
armv7m_nvic_can_take_pending_exception(void * opaque)1747 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
1748 {
1749 return true;
1750 }
1751 #endif
1752 /**
1753 * armv7m_nvic_set_pending: mark the specified exception as pending
1754 * @opaque: the NVIC
1755 * @irq: the exception number to mark pending
1756 * @secure: false for non-banked exceptions or for the nonsecure
1757 * version of a banked exception, true for the secure version of a banked
1758 * exception.
1759 *
1760 * Marks the specified exception as pending. Note that we will assert()
1761 * if @secure is true and @irq does not specify one of the fixed set
1762 * of architecturally banked exceptions.
1763 */
1764 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
1765 /**
1766 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
1767 * @opaque: the NVIC
1768 * @irq: the exception number to mark pending
1769 * @secure: false for non-banked exceptions or for the nonsecure
1770 * version of a banked exception, true for the secure version of a banked
1771 * exception.
1772 *
1773 * Similar to armv7m_nvic_set_pending(), but specifically for derived
1774 * exceptions (exceptions generated in the course of trying to take
1775 * a different exception).
1776 */
1777 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
1778 /**
1779 * armv7m_nvic_get_pending_irq_info: return highest priority pending
1780 * exception, and whether it targets Secure state
1781 * @opaque: the NVIC
1782 * @pirq: set to pending exception number
1783 * @ptargets_secure: set to whether pending exception targets Secure
1784 *
1785 * This function writes the number of the highest priority pending
1786 * exception (the one which would be made active by
1787 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
1788 * to true if the current highest priority pending exception should
1789 * be taken to Secure state, false for NS.
1790 */
1791 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
1792 bool *ptargets_secure);
1793 /**
1794 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
1795 * @opaque: the NVIC
1796 *
1797 * Move the current highest priority pending exception from the pending
1798 * state to the active state, and update v7m.exception to indicate that
1799 * it is the exception currently being handled.
1800 */
1801 void armv7m_nvic_acknowledge_irq(void *opaque);
1802 /**
1803 * armv7m_nvic_complete_irq: complete specified interrupt or exception
1804 * @opaque: the NVIC
1805 * @irq: the exception number to complete
1806 * @secure: true if this exception was secure
1807 *
1808 * Returns: -1 if the irq was not active
1809 * 1 if completing this irq brought us back to base (no active irqs)
1810 * 0 if there is still an irq active after this one was completed
1811 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
1812 */
1813 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
1814 /**
1815 * armv7m_nvic_raw_execution_priority: return the raw execution priority
1816 * @opaque: the NVIC
1817 *
1818 * Returns: the raw execution priority as defined by the v8M architecture.
1819 * This is the execution priority minus the effects of AIRCR.PRIS,
1820 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
1821 * (v8M ARM ARM I_PKLD.)
1822 */
1823 int armv7m_nvic_raw_execution_priority(void *opaque);
1824 /**
1825 * armv7m_nvic_neg_prio_requested: return true if the requested execution
1826 * priority is negative for the specified security state.
1827 * @opaque: the NVIC
1828 * @secure: the security state to test
1829 * This corresponds to the pseudocode IsReqExecPriNeg().
1830 */
1831 #ifndef CONFIG_USER_ONLY
1832 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
1833 #else
armv7m_nvic_neg_prio_requested(void * opaque,bool secure)1834 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
1835 {
1836 return false;
1837 }
1838 #endif
1839
1840 /* Interface for defining coprocessor registers.
1841 * Registers are defined in tables of arm_cp_reginfo structs
1842 * which are passed to define_arm_cp_regs().
1843 */
1844
1845 /* When looking up a coprocessor register we look for it
1846 * via an integer which encodes all of:
1847 * coprocessor number
1848 * Crn, Crm, opc1, opc2 fields
1849 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1850 * or via MRRC/MCRR?)
1851 * non-secure/secure bank (AArch32 only)
1852 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1853 * (In this case crn and opc2 should be zero.)
1854 * For AArch64, there is no 32/64 bit size distinction;
1855 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1856 * and 4 bit CRn and CRm. The encoding patterns are chosen
1857 * to be easy to convert to and from the KVM encodings, and also
1858 * so that the hashtable can contain both AArch32 and AArch64
1859 * registers (to allow for interprocessing where we might run
1860 * 32 bit code on a 64 bit core).
1861 */
1862 /* This bit is private to our hashtable cpreg; in KVM register
1863 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1864 * in the upper bits of the 64 bit ID.
1865 */
1866 #define CP_REG_AA64_SHIFT 28
1867 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1868
1869 /* To enable banking of coprocessor registers depending on ns-bit we
1870 * add a bit to distinguish between secure and non-secure cpregs in the
1871 * hashtable.
1872 */
1873 #define CP_REG_NS_SHIFT 29
1874 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1875
1876 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1877 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1878 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1879
1880 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1881 (CP_REG_AA64_MASK | \
1882 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1883 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1884 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1885 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1886 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1887 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1888
1889 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1890 * version used as a key for the coprocessor register hashtable
1891 */
kvm_to_cpreg_id(uint64_t kvmid)1892 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1893 {
1894 uint32_t cpregid = kvmid;
1895 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1896 cpregid |= CP_REG_AA64_MASK;
1897 } else {
1898 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1899 cpregid |= (1 << 15);
1900 }
1901
1902 /* KVM is always non-secure so add the NS flag on AArch32 register
1903 * entries.
1904 */
1905 cpregid |= 1 << CP_REG_NS_SHIFT;
1906 }
1907 return cpregid;
1908 }
1909
1910 /* Convert a truncated 32 bit hashtable key into the full
1911 * 64 bit KVM register ID.
1912 */
cpreg_to_kvm_id(uint32_t cpregid)1913 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1914 {
1915 uint64_t kvmid;
1916
1917 if (cpregid & CP_REG_AA64_MASK) {
1918 kvmid = cpregid & ~CP_REG_AA64_MASK;
1919 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1920 } else {
1921 kvmid = cpregid & ~(1 << 15);
1922 if (cpregid & (1 << 15)) {
1923 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1924 } else {
1925 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1926 }
1927 }
1928 return kvmid;
1929 }
1930
1931 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1932 * special-behaviour cp reg and bits [11..8] indicate what behaviour
1933 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1934 * TCG can assume the value to be constant (ie load at translate time)
1935 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1936 * indicates that the TB should not be ended after a write to this register
1937 * (the default is that the TB ends after cp writes). OVERRIDE permits
1938 * a register definition to override a previous definition for the
1939 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1940 * old must have the OVERRIDE bit set.
1941 * ALIAS indicates that this register is an alias view of some underlying
1942 * state which is also visible via another register, and that the other
1943 * register is handling migration and reset; registers marked ALIAS will not be
1944 * migrated but may have their state set by syncing of register state from KVM.
1945 * NO_RAW indicates that this register has no underlying state and does not
1946 * support raw access for state saving/loading; it will not be used for either
1947 * migration or KVM state synchronization. (Typically this is for "registers"
1948 * which are actually used as instructions for cache maintenance and so on.)
1949 * IO indicates that this register does I/O and therefore its accesses
1950 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1951 * registers which implement clocks or timers require this.
1952 */
1953 #define ARM_CP_SPECIAL 0x0001
1954 #define ARM_CP_CONST 0x0002
1955 #define ARM_CP_64BIT 0x0004
1956 #define ARM_CP_SUPPRESS_TB_END 0x0008
1957 #define ARM_CP_OVERRIDE 0x0010
1958 #define ARM_CP_ALIAS 0x0020
1959 #define ARM_CP_IO 0x0040
1960 #define ARM_CP_NO_RAW 0x0080
1961 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
1962 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
1963 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
1964 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
1965 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
1966 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1967 #define ARM_CP_FPU 0x1000
1968 #define ARM_CP_SVE 0x2000
1969 #define ARM_CP_NO_GDB 0x4000
1970 /* Used only as a terminator for ARMCPRegInfo lists */
1971 #define ARM_CP_SENTINEL 0xffff
1972 /* Mask of only the flag bits in a type field */
1973 #define ARM_CP_FLAG_MASK 0x70ff
1974
1975 /* Valid values for ARMCPRegInfo state field, indicating which of
1976 * the AArch32 and AArch64 execution states this register is visible in.
1977 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1978 * If the reginfo is declared to be visible in both states then a second
1979 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1980 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1981 * Note that we rely on the values of these enums as we iterate through
1982 * the various states in some places.
1983 */
1984 enum {
1985 ARM_CP_STATE_AA32 = 0,
1986 ARM_CP_STATE_AA64 = 1,
1987 ARM_CP_STATE_BOTH = 2,
1988 };
1989
1990 /* ARM CP register secure state flags. These flags identify security state
1991 * attributes for a given CP register entry.
1992 * The existence of both or neither secure and non-secure flags indicates that
1993 * the register has both a secure and non-secure hash entry. A single one of
1994 * these flags causes the register to only be hashed for the specified
1995 * security state.
1996 * Although definitions may have any combination of the S/NS bits, each
1997 * registered entry will only have one to identify whether the entry is secure
1998 * or non-secure.
1999 */
2000 enum {
2001 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
2002 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
2003 };
2004
2005 /* Return true if cptype is a valid type field. This is used to try to
2006 * catch errors where the sentinel has been accidentally left off the end
2007 * of a list of registers.
2008 */
cptype_valid(int cptype)2009 static inline bool cptype_valid(int cptype)
2010 {
2011 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2012 || ((cptype & ARM_CP_SPECIAL) &&
2013 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2014 }
2015
2016 /* Access rights:
2017 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2018 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2019 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2020 * (ie any of the privileged modes in Secure state, or Monitor mode).
2021 * If a register is accessible in one privilege level it's always accessible
2022 * in higher privilege levels too. Since "Secure PL1" also follows this rule
2023 * (ie anything visible in PL2 is visible in S-PL1, some things are only
2024 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2025 * terminology a little and call this PL3.
2026 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2027 * with the ELx exception levels.
2028 *
2029 * If access permissions for a register are more complex than can be
2030 * described with these bits, then use a laxer set of restrictions, and
2031 * do the more restrictive/complex check inside a helper function.
2032 */
2033 #define PL3_R 0x80
2034 #define PL3_W 0x40
2035 #define PL2_R (0x20 | PL3_R)
2036 #define PL2_W (0x10 | PL3_W)
2037 #define PL1_R (0x08 | PL2_R)
2038 #define PL1_W (0x04 | PL2_W)
2039 #define PL0_R (0x02 | PL1_R)
2040 #define PL0_W (0x01 | PL1_W)
2041
2042 #define PL3_RW (PL3_R | PL3_W)
2043 #define PL2_RW (PL2_R | PL2_W)
2044 #define PL1_RW (PL1_R | PL1_W)
2045 #define PL0_RW (PL0_R | PL0_W)
2046
2047 /* Return the highest implemented Exception Level */
arm_highest_el(CPUARMState * env)2048 static inline int arm_highest_el(CPUARMState *env)
2049 {
2050 if (arm_feature(env, ARM_FEATURE_EL3)) {
2051 return 3;
2052 }
2053 if (arm_feature(env, ARM_FEATURE_EL2)) {
2054 return 2;
2055 }
2056 return 1;
2057 }
2058
2059 /* Return true if a v7M CPU is in Handler mode */
arm_v7m_is_handler_mode(CPUARMState * env)2060 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2061 {
2062 return env->v7m.exception != 0;
2063 }
2064
2065 /* Return the current Exception Level (as per ARMv8; note that this differs
2066 * from the ARMv7 Privilege Level).
2067 */
arm_current_el(CPUARMState * env)2068 static inline int arm_current_el(CPUARMState *env)
2069 {
2070 if (arm_feature(env, ARM_FEATURE_M)) {
2071 return arm_v7m_is_handler_mode(env) ||
2072 !(env->v7m.control[env->v7m.secure] & 1);
2073 }
2074
2075 if (is_a64(env)) {
2076 return extract32(env->pstate, 2, 2);
2077 }
2078
2079 switch (env->uncached_cpsr & 0x1f) {
2080 case ARM_CPU_MODE_USR:
2081 return 0;
2082 case ARM_CPU_MODE_HYP:
2083 return 2;
2084 case ARM_CPU_MODE_MON:
2085 return 3;
2086 default:
2087 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2088 /* If EL3 is 32-bit then all secure privileged modes run in
2089 * EL3
2090 */
2091 return 3;
2092 }
2093
2094 return 1;
2095 }
2096 }
2097
2098 typedef struct ARMCPRegInfo ARMCPRegInfo;
2099
2100 typedef enum CPAccessResult {
2101 /* Access is permitted */
2102 CP_ACCESS_OK = 0,
2103 /* Access fails due to a configurable trap or enable which would
2104 * result in a categorized exception syndrome giving information about
2105 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2106 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2107 * PL1 if in EL0, otherwise to the current EL).
2108 */
2109 CP_ACCESS_TRAP = 1,
2110 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2111 * Note that this is not a catch-all case -- the set of cases which may
2112 * result in this failure is specifically defined by the architecture.
2113 */
2114 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2115 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2116 CP_ACCESS_TRAP_EL2 = 3,
2117 CP_ACCESS_TRAP_EL3 = 4,
2118 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2119 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2120 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2121 /* Access fails and results in an exception syndrome for an FP access,
2122 * trapped directly to EL2 or EL3
2123 */
2124 CP_ACCESS_TRAP_FP_EL2 = 7,
2125 CP_ACCESS_TRAP_FP_EL3 = 8,
2126 } CPAccessResult;
2127
2128 /* Access functions for coprocessor registers. These cannot fail and
2129 * may not raise exceptions.
2130 */
2131 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2132 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2133 uint64_t value);
2134 /* Access permission check functions for coprocessor registers. */
2135 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2136 const ARMCPRegInfo *opaque,
2137 bool isread);
2138 /* Hook function for register reset */
2139 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2140
2141 #define CP_ANY 0xff
2142
2143 /* Definition of an ARM coprocessor register */
2144 struct ARMCPRegInfo {
2145 /* Name of register (useful mainly for debugging, need not be unique) */
2146 const char *name;
2147 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2148 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2149 * 'wildcard' field -- any value of that field in the MRC/MCR insn
2150 * will be decoded to this register. The register read and write
2151 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2152 * used by the program, so it is possible to register a wildcard and
2153 * then behave differently on read/write if necessary.
2154 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2155 * must both be zero.
2156 * For AArch64-visible registers, opc0 is also used.
2157 * Since there are no "coprocessors" in AArch64, cp is purely used as a
2158 * way to distinguish (for KVM's benefit) guest-visible system registers
2159 * from demuxed ones provided to preserve the "no side effects on
2160 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2161 * visible (to match KVM's encoding); cp==0 will be converted to
2162 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2163 */
2164 uint8_t cp;
2165 uint8_t crn;
2166 uint8_t crm;
2167 uint8_t opc0;
2168 uint8_t opc1;
2169 uint8_t opc2;
2170 /* Execution state in which this register is visible: ARM_CP_STATE_* */
2171 int state;
2172 /* Register type: ARM_CP_* bits/values */
2173 int type;
2174 /* Access rights: PL*_[RW] */
2175 int access;
2176 /* Security state: ARM_CP_SECSTATE_* bits/values */
2177 int secure;
2178 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2179 * this register was defined: can be used to hand data through to the
2180 * register read/write functions, since they are passed the ARMCPRegInfo*.
2181 */
2182 void *opaque;
2183 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2184 * fieldoffset is non-zero, the reset value of the register.
2185 */
2186 uint64_t resetvalue;
2187 /* Offset of the field in CPUARMState for this register.
2188 *
2189 * This is not needed if either:
2190 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2191 * 2. both readfn and writefn are specified
2192 */
2193 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2194
2195 /* Offsets of the secure and non-secure fields in CPUARMState for the
2196 * register if it is banked. These fields are only used during the static
2197 * registration of a register. During hashing the bank associated
2198 * with a given security state is copied to fieldoffset which is used from
2199 * there on out.
2200 *
2201 * It is expected that register definitions use either fieldoffset or
2202 * bank_fieldoffsets in the definition but not both. It is also expected
2203 * that both bank offsets are set when defining a banked register. This
2204 * use indicates that a register is banked.
2205 */
2206 ptrdiff_t bank_fieldoffsets[2];
2207
2208 /* Function for making any access checks for this register in addition to
2209 * those specified by the 'access' permissions bits. If NULL, no extra
2210 * checks required. The access check is performed at runtime, not at
2211 * translate time.
2212 */
2213 CPAccessFn *accessfn;
2214 /* Function for handling reads of this register. If NULL, then reads
2215 * will be done by loading from the offset into CPUARMState specified
2216 * by fieldoffset.
2217 */
2218 CPReadFn *readfn;
2219 /* Function for handling writes of this register. If NULL, then writes
2220 * will be done by writing to the offset into CPUARMState specified
2221 * by fieldoffset.
2222 */
2223 CPWriteFn *writefn;
2224 /* Function for doing a "raw" read; used when we need to copy
2225 * coprocessor state to the kernel for KVM or out for
2226 * migration. This only needs to be provided if there is also a
2227 * readfn and it has side effects (for instance clear-on-read bits).
2228 */
2229 CPReadFn *raw_readfn;
2230 /* Function for doing a "raw" write; used when we need to copy KVM
2231 * kernel coprocessor state into userspace, or for inbound
2232 * migration. This only needs to be provided if there is also a
2233 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2234 * or similar behaviour.
2235 */
2236 CPWriteFn *raw_writefn;
2237 /* Function for resetting the register. If NULL, then reset will be done
2238 * by writing resetvalue to the field specified in fieldoffset. If
2239 * fieldoffset is 0 then no reset will be done.
2240 */
2241 CPResetFn *resetfn;
2242 };
2243
2244 /* Macros which are lvalues for the field in CPUARMState for the
2245 * ARMCPRegInfo *ri.
2246 */
2247 #define CPREG_FIELD32(env, ri) \
2248 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2249 #define CPREG_FIELD64(env, ri) \
2250 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2251
2252 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2253
2254 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2255 const ARMCPRegInfo *regs, void *opaque);
2256 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2257 const ARMCPRegInfo *regs, void *opaque);
define_arm_cp_regs(ARMCPU * cpu,const ARMCPRegInfo * regs)2258 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2259 {
2260 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2261 }
define_one_arm_cp_reg(ARMCPU * cpu,const ARMCPRegInfo * regs)2262 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2263 {
2264 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2265 }
2266 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2267
2268 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2269 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2270 uint64_t value);
2271 /* CPReadFn that can be used for read-as-zero behaviour */
2272 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2273
2274 /* CPResetFn that does nothing, for use if no reset is required even
2275 * if fieldoffset is non zero.
2276 */
2277 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2278
2279 /* Return true if this reginfo struct's field in the cpu state struct
2280 * is 64 bits wide.
2281 */
cpreg_field_is_64bit(const ARMCPRegInfo * ri)2282 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2283 {
2284 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2285 }
2286
cp_access_ok(int current_el,const ARMCPRegInfo * ri,int isread)2287 static inline bool cp_access_ok(int current_el,
2288 const ARMCPRegInfo *ri, int isread)
2289 {
2290 return (ri->access >> ((current_el * 2) + isread)) & 1;
2291 }
2292
2293 /* Raw read of a coprocessor register (as needed for migration, etc) */
2294 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2295
2296 /**
2297 * write_list_to_cpustate
2298 * @cpu: ARMCPU
2299 *
2300 * For each register listed in the ARMCPU cpreg_indexes list, write
2301 * its value from the cpreg_values list into the ARMCPUState structure.
2302 * This updates TCG's working data structures from KVM data or
2303 * from incoming migration state.
2304 *
2305 * Returns: true if all register values were updated correctly,
2306 * false if some register was unknown or could not be written.
2307 * Note that we do not stop early on failure -- we will attempt
2308 * writing all registers in the list.
2309 */
2310 bool write_list_to_cpustate(ARMCPU *cpu);
2311
2312 /**
2313 * write_cpustate_to_list:
2314 * @cpu: ARMCPU
2315 *
2316 * For each register listed in the ARMCPU cpreg_indexes list, write
2317 * its value from the ARMCPUState structure into the cpreg_values list.
2318 * This is used to copy info from TCG's working data structures into
2319 * KVM or for outbound migration.
2320 *
2321 * Returns: true if all register values were read correctly,
2322 * false if some register was unknown or could not be read.
2323 * Note that we do not stop early on failure -- we will attempt
2324 * reading all registers in the list.
2325 */
2326 bool write_cpustate_to_list(ARMCPU *cpu);
2327
2328 #define ARM_CPUID_TI915T 0x54029152
2329 #define ARM_CPUID_TI925T 0x54029252
2330
2331 #if defined(CONFIG_USER_ONLY)
2332 #define TARGET_PAGE_BITS 12
2333 #else
2334 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
2335 * have to support 1K tiny pages.
2336 */
2337 #define TARGET_PAGE_BITS_VARY
2338 #define TARGET_PAGE_BITS_MIN 10
2339 #endif
2340
2341 #if defined(TARGET_AARCH64)
2342 # define TARGET_PHYS_ADDR_SPACE_BITS 48
2343 # define TARGET_VIRT_ADDR_SPACE_BITS 64
2344 #else
2345 # define TARGET_PHYS_ADDR_SPACE_BITS 40
2346 # define TARGET_VIRT_ADDR_SPACE_BITS 32
2347 #endif
2348
2349 /**
2350 * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO.
2351 * Depending on the values of HCR_EL2.E2H and TGE, this may be
2352 * "behaves as 1 for all purposes other than direct read/write" or
2353 * "behaves as 0 for all purposes other than direct read/write"
2354 */
arm_hcr_el2_imo(CPUARMState * env)2355 static inline bool arm_hcr_el2_imo(CPUARMState *env)
2356 {
2357 switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
2358 case HCR_TGE:
2359 return true;
2360 case HCR_TGE | HCR_E2H:
2361 return false;
2362 default:
2363 return env->cp15.hcr_el2 & HCR_IMO;
2364 }
2365 }
2366
2367 /**
2368 * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO.
2369 */
arm_hcr_el2_fmo(CPUARMState * env)2370 static inline bool arm_hcr_el2_fmo(CPUARMState *env)
2371 {
2372 switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
2373 case HCR_TGE:
2374 return true;
2375 case HCR_TGE | HCR_E2H:
2376 return false;
2377 default:
2378 return env->cp15.hcr_el2 & HCR_FMO;
2379 }
2380 }
2381
2382 /**
2383 * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO.
2384 */
arm_hcr_el2_amo(CPUARMState * env)2385 static inline bool arm_hcr_el2_amo(CPUARMState *env)
2386 {
2387 switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
2388 case HCR_TGE:
2389 return true;
2390 case HCR_TGE | HCR_E2H:
2391 return false;
2392 default:
2393 return env->cp15.hcr_el2 & HCR_AMO;
2394 }
2395 }
2396
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx,unsigned int target_el)2397 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
2398 unsigned int target_el)
2399 {
2400 CPUARMState *env = cs->env_ptr;
2401 unsigned int cur_el = arm_current_el(env);
2402 bool secure = arm_is_secure(env);
2403 bool pstate_unmasked;
2404 int8_t unmasked = 0;
2405
2406 /* Don't take exceptions if they target a lower EL.
2407 * This check should catch any exceptions that would not be taken but left
2408 * pending.
2409 */
2410 if (cur_el > target_el) {
2411 return false;
2412 }
2413
2414 switch (excp_idx) {
2415 case EXCP_FIQ:
2416 pstate_unmasked = !(env->daif & PSTATE_F);
2417 break;
2418
2419 case EXCP_IRQ:
2420 pstate_unmasked = !(env->daif & PSTATE_I);
2421 break;
2422
2423 case EXCP_VFIQ:
2424 if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
2425 /* VFIQs are only taken when hypervized and non-secure. */
2426 return false;
2427 }
2428 return !(env->daif & PSTATE_F);
2429 case EXCP_VIRQ:
2430 if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
2431 /* VIRQs are only taken when hypervized and non-secure. */
2432 return false;
2433 }
2434 return !(env->daif & PSTATE_I);
2435 default:
2436 g_assert_not_reached();
2437 }
2438
2439 /* Use the target EL, current execution state and SCR/HCR settings to
2440 * determine whether the corresponding CPSR bit is used to mask the
2441 * interrupt.
2442 */
2443 if ((target_el > cur_el) && (target_el != 1)) {
2444 /* Exceptions targeting a higher EL may not be maskable */
2445 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2446 /* 64-bit masking rules are simple: exceptions to EL3
2447 * can't be masked, and exceptions to EL2 can only be
2448 * masked from Secure state. The HCR and SCR settings
2449 * don't affect the masking logic, only the interrupt routing.
2450 */
2451 if (target_el == 3 || !secure) {
2452 unmasked = 1;
2453 }
2454 } else {
2455 /* The old 32-bit-only environment has a more complicated
2456 * masking setup. HCR and SCR bits not only affect interrupt
2457 * routing but also change the behaviour of masking.
2458 */
2459 bool hcr, scr;
2460
2461 switch (excp_idx) {
2462 case EXCP_FIQ:
2463 /* If FIQs are routed to EL3 or EL2 then there are cases where
2464 * we override the CPSR.F in determining if the exception is
2465 * masked or not. If neither of these are set then we fall back
2466 * to the CPSR.F setting otherwise we further assess the state
2467 * below.
2468 */
2469 hcr = arm_hcr_el2_fmo(env);
2470 scr = (env->cp15.scr_el3 & SCR_FIQ);
2471
2472 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
2473 * CPSR.F bit masks FIQ interrupts when taken in non-secure
2474 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
2475 * when non-secure but only when FIQs are only routed to EL3.
2476 */
2477 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
2478 break;
2479 case EXCP_IRQ:
2480 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
2481 * we may override the CPSR.I masking when in non-secure state.
2482 * The SCR.IRQ setting has already been taken into consideration
2483 * when setting the target EL, so it does not have a further
2484 * affect here.
2485 */
2486 hcr = arm_hcr_el2_imo(env);
2487 scr = false;
2488 break;
2489 default:
2490 g_assert_not_reached();
2491 }
2492
2493 if ((scr || hcr) && !secure) {
2494 unmasked = 1;
2495 }
2496 }
2497 }
2498
2499 /* The PSTATE bits only mask the interrupt if we have not overriden the
2500 * ability above.
2501 */
2502 return unmasked || pstate_unmasked;
2503 }
2504
2505 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2506 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2507 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2508
2509 #define cpu_signal_handler cpu_arm_signal_handler
2510 #define cpu_list arm_cpu_list
2511
2512 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2513 *
2514 * If EL3 is 64-bit:
2515 * + NonSecure EL1 & 0 stage 1
2516 * + NonSecure EL1 & 0 stage 2
2517 * + NonSecure EL2
2518 * + Secure EL1 & EL0
2519 * + Secure EL3
2520 * If EL3 is 32-bit:
2521 * + NonSecure PL1 & 0 stage 1
2522 * + NonSecure PL1 & 0 stage 2
2523 * + NonSecure PL2
2524 * + Secure PL0 & PL1
2525 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2526 *
2527 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2528 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
2529 * may differ in access permissions even if the VA->PA map is the same
2530 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2531 * translation, which means that we have one mmu_idx that deals with two
2532 * concatenated translation regimes [this sort of combined s1+2 TLB is
2533 * architecturally permitted]
2534 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2535 * handling via the TLB. The only way to do a stage 1 translation without
2536 * the immediate stage 2 translation is via the ATS or AT system insns,
2537 * which can be slow-pathed and always do a page table walk.
2538 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2539 * translation regimes, because they map reasonably well to each other
2540 * and they can't both be active at the same time.
2541 * This gives us the following list of mmu_idx values:
2542 *
2543 * NS EL0 (aka NS PL0) stage 1+2
2544 * NS EL1 (aka NS PL1) stage 1+2
2545 * NS EL2 (aka NS PL2)
2546 * S EL3 (aka S PL1)
2547 * S EL0 (aka S PL0)
2548 * S EL1 (not used if EL3 is 32 bit)
2549 * NS EL0+1 stage 2
2550 *
2551 * (The last of these is an mmu_idx because we want to be able to use the TLB
2552 * for the accesses done as part of a stage 1 page table walk, rather than
2553 * having to walk the stage 2 page table over and over.)
2554 *
2555 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2556 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2557 * NS EL2 if we ever model a Cortex-R52).
2558 *
2559 * M profile CPUs are rather different as they do not have a true MMU.
2560 * They have the following different MMU indexes:
2561 * User
2562 * Privileged
2563 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2564 * Privileged, execution priority negative (ditto)
2565 * If the CPU supports the v8M Security Extension then there are also:
2566 * Secure User
2567 * Secure Privileged
2568 * Secure User, execution priority negative
2569 * Secure Privileged, execution priority negative
2570 *
2571 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2572 * are not quite the same -- different CPU types (most notably M profile
2573 * vs A/R profile) would like to use MMU indexes with different semantics,
2574 * but since we don't ever need to use all of those in a single CPU we
2575 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
2576 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2577 * the same for any particular CPU.
2578 * Variables of type ARMMUIdx are always full values, and the core
2579 * index values are in variables of type 'int'.
2580 *
2581 * Our enumeration includes at the end some entries which are not "true"
2582 * mmu_idx values in that they don't have corresponding TLBs and are only
2583 * valid for doing slow path page table walks.
2584 *
2585 * The constant names here are patterned after the general style of the names
2586 * of the AT/ATS operations.
2587 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2588 * For M profile we arrange them to have a bit for priv, a bit for negpri
2589 * and a bit for secure.
2590 */
2591 #define ARM_MMU_IDX_A 0x10 /* A profile */
2592 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2593 #define ARM_MMU_IDX_M 0x40 /* M profile */
2594
2595 /* meanings of the bits for M profile mmu idx values */
2596 #define ARM_MMU_IDX_M_PRIV 0x1
2597 #define ARM_MMU_IDX_M_NEGPRI 0x2
2598 #define ARM_MMU_IDX_M_S 0x4
2599
2600 #define ARM_MMU_IDX_TYPE_MASK (~0x7)
2601 #define ARM_MMU_IDX_COREIDX_MASK 0x7
2602
2603 typedef enum ARMMMUIdx {
2604 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
2605 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
2606 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
2607 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
2608 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
2609 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
2610 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
2611 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
2612 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
2613 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
2614 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M,
2615 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M,
2616 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M,
2617 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M,
2618 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M,
2619 /* Indexes below here don't have TLBs and are used only for AT system
2620 * instructions or for the first stage of an S12 page table walk.
2621 */
2622 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
2623 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
2624 } ARMMMUIdx;
2625
2626 /* Bit macros for the core-mmu-index values for each index,
2627 * for use when calling tlb_flush_by_mmuidx() and friends.
2628 */
2629 typedef enum ARMMMUIdxBit {
2630 ARMMMUIdxBit_S12NSE0 = 1 << 0,
2631 ARMMMUIdxBit_S12NSE1 = 1 << 1,
2632 ARMMMUIdxBit_S1E2 = 1 << 2,
2633 ARMMMUIdxBit_S1E3 = 1 << 3,
2634 ARMMMUIdxBit_S1SE0 = 1 << 4,
2635 ARMMMUIdxBit_S1SE1 = 1 << 5,
2636 ARMMMUIdxBit_S2NS = 1 << 6,
2637 ARMMMUIdxBit_MUser = 1 << 0,
2638 ARMMMUIdxBit_MPriv = 1 << 1,
2639 ARMMMUIdxBit_MUserNegPri = 1 << 2,
2640 ARMMMUIdxBit_MPrivNegPri = 1 << 3,
2641 ARMMMUIdxBit_MSUser = 1 << 4,
2642 ARMMMUIdxBit_MSPriv = 1 << 5,
2643 ARMMMUIdxBit_MSUserNegPri = 1 << 6,
2644 ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
2645 } ARMMMUIdxBit;
2646
2647 #define MMU_USER_IDX 0
2648
arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)2649 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
2650 {
2651 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
2652 }
2653
core_to_arm_mmu_idx(CPUARMState * env,int mmu_idx)2654 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
2655 {
2656 if (arm_feature(env, ARM_FEATURE_M)) {
2657 return mmu_idx | ARM_MMU_IDX_M;
2658 } else {
2659 return mmu_idx | ARM_MMU_IDX_A;
2660 }
2661 }
2662
2663 /* Return the exception level we're running at if this is our mmu_idx */
arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)2664 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
2665 {
2666 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
2667 case ARM_MMU_IDX_A:
2668 return mmu_idx & 3;
2669 case ARM_MMU_IDX_M:
2670 return mmu_idx & ARM_MMU_IDX_M_PRIV;
2671 default:
2672 g_assert_not_reached();
2673 }
2674 }
2675
2676 /* Return the MMU index for a v7M CPU in the specified security and
2677 * privilege state
2678 */
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState * env,bool secstate,bool priv)2679 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
2680 bool secstate,
2681 bool priv)
2682 {
2683 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
2684
2685 if (priv) {
2686 mmu_idx |= ARM_MMU_IDX_M_PRIV;
2687 }
2688
2689 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
2690 mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
2691 }
2692
2693 if (secstate) {
2694 mmu_idx |= ARM_MMU_IDX_M_S;
2695 }
2696
2697 return mmu_idx;
2698 }
2699
2700 /* Return the MMU index for a v7M CPU in the specified security state */
arm_v7m_mmu_idx_for_secstate(CPUARMState * env,bool secstate)2701 static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
2702 bool secstate)
2703 {
2704 bool priv = arm_current_el(env) != 0;
2705
2706 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
2707 }
2708
2709 /* Determine the current mmu_idx to use for normal loads/stores */
cpu_mmu_index(CPUARMState * env,bool ifetch)2710 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
2711 {
2712 int el = arm_current_el(env);
2713
2714 if (arm_feature(env, ARM_FEATURE_M)) {
2715 ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
2716
2717 return arm_to_core_mmu_idx(mmu_idx);
2718 }
2719
2720 if (el < 2 && arm_is_secure_below_el3(env)) {
2721 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
2722 }
2723 return el;
2724 }
2725
2726 /* Indexes used when registering address spaces with cpu_address_space_init */
2727 typedef enum ARMASIdx {
2728 ARMASIdx_NS = 0,
2729 ARMASIdx_S = 1,
2730 } ARMASIdx;
2731
2732 /* Return the Exception Level targeted by debug exceptions. */
arm_debug_target_el(CPUARMState * env)2733 static inline int arm_debug_target_el(CPUARMState *env)
2734 {
2735 bool secure = arm_is_secure(env);
2736 bool route_to_el2 = false;
2737
2738 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2739 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2740 env->cp15.mdcr_el2 & (1 << 8);
2741 }
2742
2743 if (route_to_el2) {
2744 return 2;
2745 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2746 !arm_el_is_aa64(env, 3) && secure) {
2747 return 3;
2748 } else {
2749 return 1;
2750 }
2751 }
2752
arm_v7m_csselr_razwi(ARMCPU * cpu)2753 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2754 {
2755 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2756 * CSSELR is RAZ/WI.
2757 */
2758 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2759 }
2760
aa64_generate_debug_exceptions(CPUARMState * env)2761 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2762 {
2763 if (arm_is_secure(env)) {
2764 /* MDCR_EL3.SDD disables debug events from Secure state */
2765 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
2766 || arm_current_el(env) == 3) {
2767 return false;
2768 }
2769 }
2770
2771 if (arm_current_el(env) == arm_debug_target_el(env)) {
2772 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
2773 || (env->daif & PSTATE_D)) {
2774 return false;
2775 }
2776 }
2777 return true;
2778 }
2779
aa32_generate_debug_exceptions(CPUARMState * env)2780 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2781 {
2782 int el = arm_current_el(env);
2783
2784 if (el == 0 && arm_el_is_aa64(env, 1)) {
2785 return aa64_generate_debug_exceptions(env);
2786 }
2787
2788 if (arm_is_secure(env)) {
2789 int spd;
2790
2791 if (el == 0 && (env->cp15.sder & 1)) {
2792 /* SDER.SUIDEN means debug exceptions from Secure EL0
2793 * are always enabled. Otherwise they are controlled by
2794 * SDCR.SPD like those from other Secure ELs.
2795 */
2796 return true;
2797 }
2798
2799 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2800 switch (spd) {
2801 case 1:
2802 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2803 case 0:
2804 /* For 0b00 we return true if external secure invasive debug
2805 * is enabled. On real hardware this is controlled by external
2806 * signals to the core. QEMU always permits debug, and behaves
2807 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2808 */
2809 return true;
2810 case 2:
2811 return false;
2812 case 3:
2813 return true;
2814 }
2815 }
2816
2817 return el != 2;
2818 }
2819
2820 /* Return true if debugging exceptions are currently enabled.
2821 * This corresponds to what in ARM ARM pseudocode would be
2822 * if UsingAArch32() then
2823 * return AArch32.GenerateDebugExceptions()
2824 * else
2825 * return AArch64.GenerateDebugExceptions()
2826 * We choose to push the if() down into this function for clarity,
2827 * since the pseudocode has it at all callsites except for the one in
2828 * CheckSoftwareStep(), where it is elided because both branches would
2829 * always return the same value.
2830 *
2831 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2832 * don't yet implement those exception levels or their associated trap bits.
2833 */
arm_generate_debug_exceptions(CPUARMState * env)2834 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2835 {
2836 if (env->aarch64) {
2837 return aa64_generate_debug_exceptions(env);
2838 } else {
2839 return aa32_generate_debug_exceptions(env);
2840 }
2841 }
2842
2843 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2844 * implicitly means this always returns false in pre-v8 CPUs.)
2845 */
arm_singlestep_active(CPUARMState * env)2846 static inline bool arm_singlestep_active(CPUARMState *env)
2847 {
2848 return extract32(env->cp15.mdscr_el1, 0, 1)
2849 && arm_el_is_aa64(env, arm_debug_target_el(env))
2850 && arm_generate_debug_exceptions(env);
2851 }
2852
arm_sctlr_b(CPUARMState * env)2853 static inline bool arm_sctlr_b(CPUARMState *env)
2854 {
2855 return
2856 /* We need not implement SCTLR.ITD in user-mode emulation, so
2857 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2858 * This lets people run BE32 binaries with "-cpu any".
2859 */
2860 #ifndef CONFIG_USER_ONLY
2861 !arm_feature(env, ARM_FEATURE_V7) &&
2862 #endif
2863 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2864 }
2865
2866 /* Return true if the processor is in big-endian mode. */
arm_cpu_data_is_big_endian(CPUARMState * env)2867 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2868 {
2869 int cur_el;
2870
2871 /* In 32bit endianness is determined by looking at CPSR's E bit */
2872 if (!is_a64(env)) {
2873 return
2874 #ifdef CONFIG_USER_ONLY
2875 /* In system mode, BE32 is modelled in line with the
2876 * architecture (as word-invariant big-endianness), where loads
2877 * and stores are done little endian but from addresses which
2878 * are adjusted by XORing with the appropriate constant. So the
2879 * endianness to use for the raw data access is not affected by
2880 * SCTLR.B.
2881 * In user mode, however, we model BE32 as byte-invariant
2882 * big-endianness (because user-only code cannot tell the
2883 * difference), and so we need to use a data access endianness
2884 * that depends on SCTLR.B.
2885 */
2886 arm_sctlr_b(env) ||
2887 #endif
2888 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2889 }
2890
2891 cur_el = arm_current_el(env);
2892
2893 if (cur_el == 0) {
2894 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2895 }
2896
2897 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2898 }
2899
2900 #include "exec/cpu-all.h"
2901
2902 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2903 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2904 * We put flags which are shared between 32 and 64 bit mode at the top
2905 * of the word, and flags which apply to only one mode at the bottom.
2906 */
2907 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2908 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2909 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2910 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2911 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2912 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2913 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2914 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2915 /* Target EL if we take a floating-point-disabled exception */
2916 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2917 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2918
2919 /* Bit usage when in AArch32 state: */
2920 #define ARM_TBFLAG_THUMB_SHIFT 0
2921 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2922 #define ARM_TBFLAG_VECLEN_SHIFT 1
2923 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2924 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2925 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2926 #define ARM_TBFLAG_VFPEN_SHIFT 7
2927 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2928 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2929 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2930 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2931 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2932 /* We store the bottom two bits of the CPAR as TB flags and handle
2933 * checks on the other bits at runtime
2934 */
2935 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2936 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2937 /* Indicates whether cp register reads and writes by guest code should access
2938 * the secure or nonsecure bank of banked registers; note that this is not
2939 * the same thing as the current security state of the processor!
2940 */
2941 #define ARM_TBFLAG_NS_SHIFT 19
2942 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2943 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2944 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2945 /* For M profile only, Handler (ie not Thread) mode */
2946 #define ARM_TBFLAG_HANDLER_SHIFT 21
2947 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
2948 /* For M profile only, whether we should generate stack-limit checks */
2949 #define ARM_TBFLAG_STACKCHECK_SHIFT 22
2950 #define ARM_TBFLAG_STACKCHECK_MASK (1 << ARM_TBFLAG_STACKCHECK_SHIFT)
2951
2952 /* Bit usage when in AArch64 state */
2953 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
2954 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2955 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */
2956 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2957 #define ARM_TBFLAG_SVEEXC_EL_SHIFT 2
2958 #define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT)
2959 #define ARM_TBFLAG_ZCR_LEN_SHIFT 4
2960 #define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT)
2961
2962 /* some convenience accessor macros */
2963 #define ARM_TBFLAG_AARCH64_STATE(F) \
2964 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2965 #define ARM_TBFLAG_MMUIDX(F) \
2966 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2967 #define ARM_TBFLAG_SS_ACTIVE(F) \
2968 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2969 #define ARM_TBFLAG_PSTATE_SS(F) \
2970 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2971 #define ARM_TBFLAG_FPEXC_EL(F) \
2972 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2973 #define ARM_TBFLAG_THUMB(F) \
2974 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2975 #define ARM_TBFLAG_VECLEN(F) \
2976 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2977 #define ARM_TBFLAG_VECSTRIDE(F) \
2978 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2979 #define ARM_TBFLAG_VFPEN(F) \
2980 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2981 #define ARM_TBFLAG_CONDEXEC(F) \
2982 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2983 #define ARM_TBFLAG_SCTLR_B(F) \
2984 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2985 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2986 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2987 #define ARM_TBFLAG_NS(F) \
2988 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2989 #define ARM_TBFLAG_BE_DATA(F) \
2990 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2991 #define ARM_TBFLAG_HANDLER(F) \
2992 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
2993 #define ARM_TBFLAG_STACKCHECK(F) \
2994 (((F) & ARM_TBFLAG_STACKCHECK_MASK) >> ARM_TBFLAG_STACKCHECK_SHIFT)
2995 #define ARM_TBFLAG_TBI0(F) \
2996 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2997 #define ARM_TBFLAG_TBI1(F) \
2998 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2999 #define ARM_TBFLAG_SVEEXC_EL(F) \
3000 (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT)
3001 #define ARM_TBFLAG_ZCR_LEN(F) \
3002 (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT)
3003
bswap_code(bool sctlr_b)3004 static inline bool bswap_code(bool sctlr_b)
3005 {
3006 #ifdef CONFIG_USER_ONLY
3007 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3008 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3009 * would also end up as a mixed-endian mode with BE code, LE data.
3010 */
3011 return
3012 #ifdef TARGET_WORDS_BIGENDIAN
3013 1 ^
3014 #endif
3015 sctlr_b;
3016 #else
3017 /* All code access in ARM is little endian, and there are no loaders
3018 * doing swaps that need to be reversed
3019 */
3020 return 0;
3021 #endif
3022 }
3023
3024 #ifdef CONFIG_USER_ONLY
arm_cpu_bswap_data(CPUARMState * env)3025 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3026 {
3027 return
3028 #ifdef TARGET_WORDS_BIGENDIAN
3029 1 ^
3030 #endif
3031 arm_cpu_data_is_big_endian(env);
3032 }
3033 #endif
3034
3035 #ifndef CONFIG_USER_ONLY
3036 /**
3037 * arm_regime_tbi0:
3038 * @env: CPUARMState
3039 * @mmu_idx: MMU index indicating required translation regime
3040 *
3041 * Extracts the TBI0 value from the appropriate TCR for the current EL
3042 *
3043 * Returns: the TBI0 value.
3044 */
3045 uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
3046
3047 /**
3048 * arm_regime_tbi1:
3049 * @env: CPUARMState
3050 * @mmu_idx: MMU index indicating required translation regime
3051 *
3052 * Extracts the TBI1 value from the appropriate TCR for the current EL
3053 *
3054 * Returns: the TBI1 value.
3055 */
3056 uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
3057 #else
3058 /* We can't handle tagged addresses properly in user-only mode */
arm_regime_tbi0(CPUARMState * env,ARMMMUIdx mmu_idx)3059 static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
3060 {
3061 return 0;
3062 }
3063
arm_regime_tbi1(CPUARMState * env,ARMMMUIdx mmu_idx)3064 static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
3065 {
3066 return 0;
3067 }
3068 #endif
3069
3070 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3071 target_ulong *cs_base, uint32_t *flags);
3072
3073 enum {
3074 QEMU_PSCI_CONDUIT_DISABLED = 0,
3075 QEMU_PSCI_CONDUIT_SMC = 1,
3076 QEMU_PSCI_CONDUIT_HVC = 2,
3077 };
3078
3079 #ifndef CONFIG_USER_ONLY
3080 /* Return the address space index to use for a memory access */
arm_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)3081 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3082 {
3083 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3084 }
3085
3086 /* Return the AddressSpace to use for a memory access
3087 * (which depends on whether the access is S or NS, and whether
3088 * the board gave us a separate AddressSpace for S accesses).
3089 */
arm_addressspace(CPUState * cs,MemTxAttrs attrs)3090 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3091 {
3092 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3093 }
3094 #endif
3095
3096 /**
3097 * arm_register_pre_el_change_hook:
3098 * Register a hook function which will be called immediately before this
3099 * CPU changes exception level or mode. The hook function will be
3100 * passed a pointer to the ARMCPU and the opaque data pointer passed
3101 * to this function when the hook was registered.
3102 *
3103 * Note that if a pre-change hook is called, any registered post-change hooks
3104 * are guaranteed to subsequently be called.
3105 */
3106 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3107 void *opaque);
3108 /**
3109 * arm_register_el_change_hook:
3110 * Register a hook function which will be called immediately after this
3111 * CPU changes exception level or mode. The hook function will be
3112 * passed a pointer to the ARMCPU and the opaque data pointer passed
3113 * to this function when the hook was registered.
3114 *
3115 * Note that any registered hooks registered here are guaranteed to be called
3116 * if pre-change hooks have been.
3117 */
3118 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3119 *opaque);
3120
3121 /**
3122 * aa32_vfp_dreg:
3123 * Return a pointer to the Dn register within env in 32-bit mode.
3124 */
aa32_vfp_dreg(CPUARMState * env,unsigned regno)3125 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3126 {
3127 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3128 }
3129
3130 /**
3131 * aa32_vfp_qreg:
3132 * Return a pointer to the Qn register within env in 32-bit mode.
3133 */
aa32_vfp_qreg(CPUARMState * env,unsigned regno)3134 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3135 {
3136 return &env->vfp.zregs[regno].d[0];
3137 }
3138
3139 /**
3140 * aa64_vfp_qreg:
3141 * Return a pointer to the Qn register within env in 64-bit mode.
3142 */
aa64_vfp_qreg(CPUARMState * env,unsigned regno)3143 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3144 {
3145 return &env->vfp.zregs[regno].d[0];
3146 }
3147
3148 /* Shared between translate-sve.c and sve_helper.c. */
3149 extern const uint64_t pred_esz_masks[4];
3150
3151 #endif
3152