1 /*
2 * Copyright (C) 2005 by Dominic Rath
3 * Dominic.Rath@gmx.de
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2018 by Liviu Ionescu
12 * <ilg@livius.net>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 */
27
28 #ifndef OPENOCD_TARGET_ARM_H
29 #define OPENOCD_TARGET_ARM_H
30
31 #include <helper/command.h>
32 #include "target.h"
33
34 /**
35 * @file
36 * Holds the interface to ARM cores.
37 *
38 * At this writing, only "classic ARM" cores built on the ARMv4 register
39 * and mode model are supported. The Thumb2-only microcontroller profile
40 * support has not yet been integrated, affecting Cortex-M parts.
41 */
42
43 /**
44 * Indicates what registers are in the ARM state core register set.
45 *
46 * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
47 * on for example ARM7TDMI cores.
48 * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
49 * three more registers are shadowed for "Secure Monitor" mode.
50 * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
51 * and also security extensions. Additional shadowed registers for
52 * "Secure Monitor" and "Hypervisor" modes.
53 * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
54 * which only shadows SP.
55 */
56 enum arm_core_type {
57 ARM_CORE_TYPE_STD = -1,
58 ARM_CORE_TYPE_SEC_EXT = 1,
59 ARM_CORE_TYPE_VIRT_EXT,
60 ARM_CORE_TYPE_M_PROFILE,
61 };
62
63 /**
64 * Represent state of an ARM core.
65 *
66 * Most numbers match the five low bits of the *PSR registers on
67 * "classic ARM" processors, which build on the ARMv4 processor
68 * modes and register set.
69 *
70 * ARM_MODE_ANY is a magic value, often used as a wildcard.
71 *
72 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
73 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
74 * they support.
75 */
76 enum arm_mode {
77 ARM_MODE_USR = 16,
78 ARM_MODE_FIQ = 17,
79 ARM_MODE_IRQ = 18,
80 ARM_MODE_SVC = 19,
81 ARM_MODE_MON = 22,
82 ARM_MODE_ABT = 23,
83 ARM_MODE_HYP = 26,
84 ARM_MODE_UND = 27,
85 ARM_MODE_1176_MON = 28,
86 ARM_MODE_SYS = 31,
87
88 ARM_MODE_THREAD = 0,
89 ARM_MODE_USER_THREAD = 1,
90 ARM_MODE_HANDLER = 2,
91
92 ARMV8_64_EL0T = 0x0,
93 ARMV8_64_EL1T = 0x4,
94 ARMV8_64_EL1H = 0x5,
95 ARMV8_64_EL2T = 0x8,
96 ARMV8_64_EL2H = 0x9,
97 ARMV8_64_EL3T = 0xC,
98 ARMV8_64_EL3H = 0xD,
99
100 ARM_MODE_ANY = -1
101 };
102
103 /* VFPv3 internal register numbers mapping to d0:31 */
104 enum {
105 ARM_VFP_V3_D0 = 51,
106 ARM_VFP_V3_D1,
107 ARM_VFP_V3_D2,
108 ARM_VFP_V3_D3,
109 ARM_VFP_V3_D4,
110 ARM_VFP_V3_D5,
111 ARM_VFP_V3_D6,
112 ARM_VFP_V3_D7,
113 ARM_VFP_V3_D8,
114 ARM_VFP_V3_D9,
115 ARM_VFP_V3_D10,
116 ARM_VFP_V3_D11,
117 ARM_VFP_V3_D12,
118 ARM_VFP_V3_D13,
119 ARM_VFP_V3_D14,
120 ARM_VFP_V3_D15,
121 ARM_VFP_V3_D16,
122 ARM_VFP_V3_D17,
123 ARM_VFP_V3_D18,
124 ARM_VFP_V3_D19,
125 ARM_VFP_V3_D20,
126 ARM_VFP_V3_D21,
127 ARM_VFP_V3_D22,
128 ARM_VFP_V3_D23,
129 ARM_VFP_V3_D24,
130 ARM_VFP_V3_D25,
131 ARM_VFP_V3_D26,
132 ARM_VFP_V3_D27,
133 ARM_VFP_V3_D28,
134 ARM_VFP_V3_D29,
135 ARM_VFP_V3_D30,
136 ARM_VFP_V3_D31,
137 ARM_VFP_V3_FPSCR,
138 };
139
140 const char *arm_mode_name(unsigned psr_mode);
141 bool is_arm_mode(unsigned psr_mode);
142
143 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
144 enum arm_state {
145 ARM_STATE_ARM,
146 ARM_STATE_THUMB,
147 ARM_STATE_JAZELLE,
148 ARM_STATE_THUMB_EE,
149 ARM_STATE_AARCH64,
150 };
151
152 /** ARM vector floating point enabled, if yes which version. */
153 enum arm_vfp_version {
154 ARM_VFP_DISABLED,
155 ARM_VFP_V1,
156 ARM_VFP_V2,
157 ARM_VFP_V3,
158 };
159
160 #define ARM_COMMON_MAGIC 0x0A450A45
161
162 /**
163 * Represents a generic ARM core, with standard application registers.
164 *
165 * There are sixteen application registers (including PC, SP, LR) and a PSR.
166 * Cortex-M series cores do not support as many core states or shadowed
167 * registers as traditional ARM cores, and only support Thumb2 instructions.
168 */
169 struct arm {
170 int common_magic;
171 struct reg_cache *core_cache;
172
173 /** Handle to the PC; valid in all core modes. */
174 struct reg *pc;
175
176 /** Handle to the CPSR/xPSR; valid in all core modes. */
177 struct reg *cpsr;
178
179 /** Handle to the SPSR; valid only in core modes with an SPSR. */
180 struct reg *spsr;
181
182 /** Support for arm_reg_current() */
183 const int *map;
184
185 /** Indicates what registers are in the ARM state core register set. */
186 enum arm_core_type core_type;
187
188 /** Record the current core mode: SVC, USR, or some other mode. */
189 enum arm_mode core_mode;
190
191 /** Record the current core state: ARM, Thumb, or otherwise. */
192 enum arm_state core_state;
193
194 /** Flag reporting unavailability of the BKPT instruction. */
195 bool is_armv4;
196
197 /** Flag reporting armv6m based core. */
198 bool is_armv6m;
199
200 /** Flag reporting armv8m based core. */
201 bool is_armv8m;
202
203 /** Floating point or VFP version, 0 if disabled. */
204 int arm_vfp_version;
205
206 int (*setup_semihosting)(struct target *target, int enable);
207
208 /** Backpointer to the target. */
209 struct target *target;
210
211 /** Handle for the debug module, if one is present. */
212 struct arm_dpm *dpm;
213
214 /** Handle for the Embedded Trace Module, if one is present. */
215 struct etm_context *etm;
216
217 /* FIXME all these methods should take "struct arm *" not target */
218
219 /** Retrieve all core registers, for display. */
220 int (*full_context)(struct target *target);
221
222 /** Retrieve a single core register. */
223 int (*read_core_reg)(struct target *target, struct reg *reg,
224 int num, enum arm_mode mode);
225 int (*write_core_reg)(struct target *target, struct reg *reg,
226 int num, enum arm_mode mode, uint8_t *value);
227
228 /** Read coprocessor register. */
229 int (*mrc)(struct target *target, int cpnum,
230 uint32_t op1, uint32_t op2,
231 uint32_t CRn, uint32_t CRm,
232 uint32_t *value);
233
234 /** Write coprocessor register. */
235 int (*mcr)(struct target *target, int cpnum,
236 uint32_t op1, uint32_t op2,
237 uint32_t CRn, uint32_t CRm,
238 uint32_t value);
239
240 void *arch_info;
241
242 /** For targets conforming to ARM Debug Interface v5,
243 * this handle references the Debug Access Port (DAP)
244 * used to make requests to the target.
245 */
246 struct adiv5_dap *dap;
247 };
248
249 /** Convert target handle to generic ARM target state handle. */
target_to_arm(struct target * target)250 static inline struct arm *target_to_arm(struct target *target)
251 {
252 assert(target != NULL);
253 return target->arch_info;
254 }
255
is_arm(struct arm * arm)256 static inline bool is_arm(struct arm *arm)
257 {
258 assert(arm != NULL);
259 return arm->common_magic == ARM_COMMON_MAGIC;
260 }
261
262 struct arm_algorithm {
263 int common_magic;
264
265 enum arm_mode core_mode;
266 enum arm_state core_state;
267 };
268
269 struct arm_reg {
270 int num;
271 enum arm_mode mode;
272 struct target *target;
273 struct arm *arm;
274 uint8_t value[16];
275 };
276
277 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
278 void arm_free_reg_cache(struct arm *arm);
279
280 struct reg_cache *armv8_build_reg_cache(struct target *target);
281
282 extern const struct command_registration arm_command_handlers[];
283
284 int arm_arch_state(struct target *target);
285 const char *arm_get_gdb_arch(struct target *target);
286 int arm_get_gdb_reg_list(struct target *target,
287 struct reg **reg_list[], int *reg_list_size,
288 enum target_register_class reg_class);
289 const char *armv8_get_gdb_arch(struct target *target);
290 int armv8_get_gdb_reg_list(struct target *target,
291 struct reg **reg_list[], int *reg_list_size,
292 enum target_register_class reg_class);
293
294 int arm_init_arch_info(struct target *target, struct arm *arm);
295
296 /* REVISIT rename this once it's usable by ARMv7-M */
297 int armv4_5_run_algorithm(struct target *target,
298 int num_mem_params, struct mem_param *mem_params,
299 int num_reg_params, struct reg_param *reg_params,
300 target_addr_t entry_point, target_addr_t exit_point,
301 int timeout_ms, void *arch_info);
302 int armv4_5_run_algorithm_inner(struct target *target,
303 int num_mem_params, struct mem_param *mem_params,
304 int num_reg_params, struct reg_param *reg_params,
305 uint32_t entry_point, uint32_t exit_point,
306 int timeout_ms, void *arch_info,
307 int (*run_it)(struct target *target, uint32_t exit_point,
308 int timeout_ms, void *arch_info));
309
310 int arm_checksum_memory(struct target *target,
311 target_addr_t address, uint32_t count, uint32_t *checksum);
312 int arm_blank_check_memory(struct target *target,
313 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
314
315 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
316 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
317 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
318
319 extern struct reg arm_gdb_dummy_fp_reg;
320 extern struct reg arm_gdb_dummy_fps_reg;
321
322 #endif /* OPENOCD_TARGET_ARM_H */
323