1 #ifndef __SYS_VM_ARM_H__ 2 #define __SYS_VM_ARM_H__ 3 /* 4 arm/vm.h 5 */ 6 7 8 /* 9 * We are using the following setup 10 * the system is configured to have the TRE (Tex remap enable bit) set to 0 11 * The TEX[2:0] B and C bits are used to determins memory attributes. 12 * These bits together with the S Bit (Shareability Bit) determines the 13 * memory attributes. 14 * 15 * The S bit is ignored when the other attribute define the memory as 16 * "device" or "strongly ordered" 17 * 18 * We are setting the tex[2] bit to one to end up with the following 19 * encoding 20 * 21 * 00 00 Non cacheable 22 * 01 01 Write back, Write allocate 23 * 10 10 Write trough, No write allocate 24 * 11 11 Write back , Write alloc 25 */ 26 #define ARM_PAGE_SIZE 4096 /* small page on ARM */ 27 #define ARM_SECTION_SIZE (1024 * 1024) /* 1 MB section */ 28 29 /* Second level page table entries */ 30 #define ARM_VM_PAGETABLE (1 << 1) /* Page table */ 31 #define ARM_VM_PTE_PRESENT (1 << 1) /* Page is present */ 32 #define ARM_VM_PTE_B (1 << 2) /* B bit */ 33 #define ARM_VM_PTE_C (1 << 3) /* C bit */ 34 #define ARM_VM_PTE_SUPER (0x1 << 4) /* Super access only AP[1:0] */ 35 #define ARM_VM_PTE_USER (0x3 << 4) /* Super/User access AP[1:0] */ 36 #define ARM_VM_PTE_TEX0 (1 << 6) /* TEX[0] */ 37 #define ARM_VM_PTE_TEX1 (1 << 7) /* TEX[1] */ 38 #define ARM_VM_PTE_TEX2 (1 << 8) /* TEX[2] */ 39 #define ARM_VM_PTE_RO (1 << 9) /* Read only access AP[2] */ 40 #define ARM_VM_PTE_RW (0 << 9) /* Read-write access AP[2] */ 41 42 #define ARM_VM_PTE_S (1 << 10) /* "Shareable" */ 43 44 45 #define ARM_VM_PTE_NOTGLOBAL (1 << 11) /* Not Global */ 46 47 /* inner and outer write-back, write-allocate */ 48 #define ARM_VM_PTE_WB (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX0 | ARM_VM_PTE_B) 49 /* inner and outer write-through, no write-allocate */ 50 #define ARM_VM_PTE_WT (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX1 | ARM_VM_PTE_C ) 51 /* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ 52 #define ARM_VM_PTE_WTWB (ARM_VM_PTE_TEX2 | ARM_VM_PTE_TEX0 | ARM_VM_PTE_C ) 53 54 #define ARM_VM_PTE_CACHED ARM_VM_PTE_WTWB 55 /* shareable device */ 56 #define ARM_VM_PTE_DEVICE (ARM_VM_PTE_B) 57 58 #define ARM_VM_ADDR_MASK 0xFFFFF000 /* physical address */ 59 #define ARM_VM_ADDR_MASK_1MB 0xFFF00000 /* physical address */ 60 #define ARM_VM_OFFSET_MASK_1MB 0x000FFFFF /* physical address */ 61 62 /* Big page (1MB section) specific flags. */ 63 #define ARM_VM_SECTION (1 << 1) /* 1MB section */ 64 #define ARM_VM_SECTION_PRESENT (1 << 1) /* Section is present */ 65 #define ARM_VM_SECTION_B (1 << 2) /* B Bit */ 66 #define ARM_VM_SECTION_C (1 << 3) /* C Bit */ 67 #define ARM_VM_SECTION_DOMAIN (0xF << 5) /* Domain Number */ 68 #define ARM_VM_SECTION_SUPER (0x1 << 10) /* Super access only AP[1:0] */ 69 #define ARM_VM_SECTION_USER (0x3 << 10) /* Super/User access AP[1:0] */ 70 #define ARM_VM_SECTION_TEX0 (1 << 12) /* TEX[0] */ 71 #define ARM_VM_SECTION_TEX1 (1 << 13) /* TEX[1] */ 72 #define ARM_VM_SECTION_TEX2 (1 << 14) /* TEX[2] */ 73 #define ARM_VM_SECTION_RO (1 << 15) /* Read only access AP[2] */ 74 #define ARM_VM_SECTION_SHAREABLE (1 << 16) /* Shareable */ 75 #define ARM_VM_SECTION_NOTGLOBAL (1 << 17) /* Not Global */ 76 77 /* inner and outer write-back, write-allocate */ 78 #define ARM_VM_SECTION_WB (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B ) 79 /* inner and outer write-through, no write-allocate */ 80 #define ARM_VM_SECTION_WT (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C ) 81 /* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */ 82 #define ARM_VM_SECTION_WTWB (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C ) 83 /* shareable device */ 84 85 #define ARM_VM_SECTION_CACHED ARM_VM_SECTION_WTWB 86 87 #define ARM_VM_SECTION_DEVICE (ARM_VM_SECTION_B) 88 89 /* Page directory specific flags. */ 90 #define ARM_VM_PAGEDIR (1 << 0) /* Page directory */ 91 #define ARM_VM_PDE_PRESENT (1 << 0) /* Page directory is present */ 92 #define ARM_VM_PDE_DOMAIN (0xF << 5) /* Domain Number */ 93 94 #define ARM_VM_PT_ENT_SIZE 4 /* Size of a page table entry */ 95 #define ARM_VM_DIR_ENT_SIZE 4 /* Size of a page dir entry */ 96 #define ARM_VM_DIR_ENTRIES 4096 /* Number of entries in a page dir */ 97 #define ARM_VM_DIR_ENT_SHIFT 20 /* Shift to get entry in page dir. */ 98 #define ARM_VM_PT_ENT_SHIFT 12 /* Shift to get entry in page table */ 99 #define ARM_VM_PT_ENT_MASK 0xFF /* Mask to get entry in page table */ 100 #define ARM_VM_PT_ENTRIES 256 /* Number of entries in a page table */ 101 102 103 #define ARM_VM_PTE(v) (((v) >> ARM_VM_PT_ENT_SHIFT) & ARM_VM_PT_ENT_MASK) 104 #define ARM_VM_PDE(v) ( (v) >> ARM_VM_DIR_ENT_SHIFT) 105 #define ARM_VM_PFA(e) ( (e) & ARM_VM_ADDR_MASK) 106 107 /* Second level small pages entry(Page Table Entry) points to 4K */ 108 #define ARM_VM_PTE_SHIFT 12 109 #define ARM_VM_PTE_MASK (~((1 << ARM_VM_PTE_SHIFT) - 1)) 110 111 /* First level entry(Page Directory Entry) to a second level small page PTE */ 112 #define ARM_VM_PDE_SHIFT 10 113 #define ARM_VM_PDE_MASK (~((1 << ARM_VM_PDE_SHIFT) - 1)) 114 115 /* First level entry(Page Directory Entry) to a 1MB section */ 116 #define ARM_VM_SECTION_SHIFT 20 117 #define ARM_VM_SECTION_MASK (~((1 << ARM_VM_SECTION_SHIFT) - 1)) 118 119 #define ARM_VM_DIR_SIZE (ARM_VM_DIR_ENTRIES * ARM_VM_DIR_ENT_SIZE) 120 #define ARM_PAGEDIR_SIZE (ARM_VM_DIR_SIZE) 121 #define ARM_VM_PT_SIZE (ARM_VM_PT_ENTRIES * ARM_VM_PT_ENT_SIZE) 122 #define ARM_PAGETABLE_SIZE (ARM_VM_PT_SIZE) 123 124 /* ARM pagefault status bits */ 125 #define ARM_VM_PFE_ALIGN 0x01 /* Pagefault caused by Alignment fault */ 126 #define ARM_VM_PFE_IMAINT 0x04 /* Caused by Instruction cache 127 maintenance fault */ 128 #define ARM_VM_PFE_TTWALK_L1ABORT 0x0c /* Caused by Synchronous external abort 129 * on translation table walk (Level 1) 130 */ 131 #define ARM_VM_PFE_TTWALK_L2ABORT 0x0e /* Caused by Synchronous external abort 132 * on translation table walk (Level 2) 133 */ 134 #define ARM_VM_PFE_TTWALK_L1PERR 0x1c /* Caused by Parity error 135 * on translation table walk (Level 1) 136 */ 137 #define ARM_VM_PFE_TTWALK_L2PERR 0x1e /* Caused by Parity error 138 * on translation table walk (Level 2) 139 */ 140 #define ARM_VM_PFE_L1TRANS 0x05 /* Caused by Translation fault (Level 1) 141 */ 142 #define ARM_VM_PFE_L2TRANS 0x07 /* Caused by Translation fault (Level 2) 143 */ 144 #define ARM_VM_PFE_L1ACCESS 0x03 /* Caused by Access flag fault (Level 1) 145 */ 146 #define ARM_VM_PFE_L2ACCESS 0x06 /* Caused by Access flag fault (Level 2) 147 */ 148 #define ARM_VM_PFE_L1DOMAIN 0x09 /* Caused by Domain fault (Level 1) 149 */ 150 #define ARM_VM_PFE_L2DOMAIN 0x0b /* Caused by Domain fault (Level 2) 151 */ 152 #define ARM_VM_PFE_L1PERM 0x0d /* Caused by Permission fault (Level 1) 153 */ 154 #define ARM_VM_PFE_L2PERM 0x0f /* Caused by Permission fault (Level 2) 155 */ 156 #define ARM_VM_PFE_DEBUG 0x02 /* Caused by Debug event */ 157 #define ARM_VM_PFE_ABORT 0x08 /* Caused by Synchronous external abort 158 */ 159 #define ARM_VM_PFE_TLB_CONFLICT 0x10 /* Caused by TLB conflict abort 160 */ 161 162 #define ARM_VM_PFE_W (1<<11) /* Caused by write (otherwise read) */ 163 #define ARM_VM_PFE_FS4 (1<<10) /* Fault status (bit 4) */ 164 #define ARM_VM_PFE_FS3_0 0xf /* Fault status (bits 3:0) */ 165 166 167 /* Translation table base register specfic flags */ 168 #define ARM_TTBR_C (0x01) /* Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory. */ 169 170 /* RGN bits[4:3] indicates the Outer cacheability attributes 171 for the memory associated with the translation table walks */ 172 #define ARM_TTBR_OUTER_NC (0x0 << 3) /* Non-cacheable*/ 173 #define ARM_TTBR_OUTER_WBWA (0x1 << 3) /* Outer Write-Back Write-Allocate Cacheable. */ 174 #define ARM_TTBR_OUTER_WT (0x2 << 3) /* Outer Write-Through Cacheable. */ 175 #define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back no Write-Allocate Cacheable. */ 176 177 178 #define ARM_TTBR_ADDR_MASK (0xffffc000) /* only the 18 upper bits are to be used as address */ 179 #define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA 180 181 /* Fault status */ 182 #define ARM_VM_PFE_FS(s) \ 183 ((((s) & ARM_VM_PFE_FS4) >> 6) | ((s) & ARM_VM_PFE_FS3_0)) 184 185 #ifndef __ASSEMBLY__ 186 187 #include <minix/type.h> 188 189 /* structure used by VM to pass data to the kernel while enabling paging */ 190 struct vm_ep_data { 191 struct mem_map * mem_map; 192 vir_bytes data_seg_limit; 193 }; 194 #endif 195 196 #endif /* __SYS_VM_ARM_H__ */ 197