1 /* $NetBSD: locore.h,v 1.37 2021/10/31 16:23:47 skrll Exp $ */
2
3 /*
4 * Copyright (c) 1994-1996 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * cpu.h
40 *
41 * CPU specific symbols
42 *
43 * Created : 18/09/94
44 *
45 * Based on kate/katelib/arm6.h
46 */
47
48 #ifndef _ARM_LOCORE_H_
49 #define _ARM_LOCORE_H_
50
51 #ifdef __arm__
52
53 #ifdef _KERNEL_OPT
54 #include "opt_cpuoptions.h"
55 #include "opt_cputypes.h"
56 #include "opt_arm_debug.h"
57 #endif
58
59 #include <sys/pcu.h>
60
61 #include <arm/cpuconf.h>
62 #include <arm/armreg.h>
63
64 #include <machine/frame.h>
65
66 #ifdef _LOCORE
67
68 #if defined(_ARM_ARCH_6)
69 #define IRQdisable cpsid i
70 #define IRQenable cpsie i
71 #else
72 #define IRQdisable \
73 stmfd sp!, {r0} ; \
74 mrs r0, cpsr ; \
75 orr r0, r0, #(I32_bit) ; \
76 msr cpsr_c, r0 ; \
77 ldmfd sp!, {r0}
78
79 #define IRQenable \
80 stmfd sp!, {r0} ; \
81 mrs r0, cpsr ; \
82 bic r0, r0, #(I32_bit) ; \
83 msr cpsr_c, r0 ; \
84 ldmfd sp!, {r0}
85 #endif
86
87 #if defined (TPIDRPRW_IS_CURCPU)
88 #define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4
89 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
90 #define GET_CURX(rCPU, rLWP) GET_CURCPU(rCPU); ldr rLWP, [rCPU, #CI_CURLWP]
91 #elif defined (TPIDRPRW_IS_CURLWP)
92 #define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4
93 #if defined (MULTIPROCESSOR)
94 #define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
95 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); ldr rCPU, [rLWP, #L_CPU]
96 #elif defined(_ARM_ARCH_7)
97 #define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store
98 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); GET_CURCPU(rCPU)
99 #else
100 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
101 #define GET_CURX(rCPU, rLWP) GET_CURLWP(rLWP); ldr rCPU, [rLWP, #L_CPU]
102 #endif
103 #elif !defined(MULTIPROCESSOR)
104 #define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
105 #define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
106 #define GET_CURX(rCPU, rLWP) GET_CURCPU(rCPU); ldr rLWP, [rCPU, #CI_CURLWP]
107 #endif
108 #define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB]
109
110 #else /* !_LOCORE */
111
112 #include <arm/cpufunc.h>
113
114 #define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
115 #define IRQenable __set_cpsr_c(I32_bit, 0);
116
117 /*
118 * Validate a PC or PSR for a user process. Used by various system calls
119 * that take a context passed by the user and restore it.
120 */
121
122 #ifdef __NO_FIQ
123 #define VALID_PSR(psr) \
124 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
125 #else
126 #define VALID_PSR(psr) \
127 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
128 #endif
129
130 /*
131 * Translation Table Base Register Share/Cache settings
132 */
133 #define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
134 #define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
135
136 /* The address of the vector page. */
137 extern vaddr_t vector_page;
138 void arm32_vector_init(vaddr_t, int);
139
140 #define ARM_VEC_RESET (1 << 0)
141 #define ARM_VEC_UNDEFINED (1 << 1)
142 #define ARM_VEC_SWI (1 << 2)
143 #define ARM_VEC_PREFETCH_ABORT (1 << 3)
144 #define ARM_VEC_DATA_ABORT (1 << 4)
145 #define ARM_VEC_ADDRESS_EXCEPTION (1 << 5)
146 #define ARM_VEC_IRQ (1 << 6)
147 #define ARM_VEC_FIQ (1 << 7)
148
149 #define ARM_NVEC 8
150 #define ARM_VEC_ALL 0xffffffff
151
152 /*
153 * cpu device glue (belongs in cpuvar.h)
154 */
155 void cpu_attach(device_t, cpuid_t);
156
157 /* 1 == use cpu_sleep(), 0 == don't */
158 extern int cpu_do_powersave;
159 extern int cpu_printfataltraps;
160 extern int cpu_fpu_present;
161 extern int cpu_hwdiv_present;
162 extern int cpu_neon_present;
163 extern int cpu_simd_present;
164 extern int cpu_simdex_present;
165 extern int cpu_umull_present;
166 extern int cpu_synchprim_present;
167
168 extern int cpu_instruction_set_attributes[6];
169 extern int cpu_memory_model_features[4];
170 extern int cpu_processor_features[2];
171 extern int cpu_media_and_vfp_features[2];
172
173 extern bool arm_has_tlbiasid_p;
174 extern bool arm_has_mpext_p;
175
176 #if !defined(CPU_ARMV7)
177 #define CPU_IS_ARMV7_P() false
178 #elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
179 extern bool cpu_armv7_p;
180 #define CPU_IS_ARMV7_P() (cpu_armv7_p)
181 #else
182 #define CPU_IS_ARMV7_P() true
183 #endif
184 #if !defined(CPU_ARMV6)
185 #define CPU_IS_ARMV6_P() false
186 #elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6)
187 extern bool cpu_armv6_p;
188 #define CPU_IS_ARMV6_P() (cpu_armv6_p)
189 #else
190 #define CPU_IS_ARMV6_P() true
191 #endif
192
193 /*
194 * Used by the fault code to read the current instruction.
195 */
196 static inline uint32_t
read_insn(vaddr_t va,bool user_p)197 read_insn(vaddr_t va, bool user_p)
198 {
199 uint32_t insn;
200 if (user_p) {
201 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
202 } else {
203 insn = *(const uint32_t *)va;
204 }
205 #ifdef _ARM_ARCH_BE8
206 insn = bswap32(insn);
207 #endif
208 return insn;
209 }
210
211 /*
212 * Used by the fault code to read the current thumb instruction.
213 */
214 static inline uint32_t
read_thumb_insn(vaddr_t va,bool user_p)215 read_thumb_insn(vaddr_t va, bool user_p)
216 {
217 va &= ~1;
218 uint32_t insn;
219 if (user_p) {
220 #if defined(__thumb__) && defined(_ARM_ARCH_T2)
221 __asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
222 #elif defined(_ARM_ARCH_7)
223 __asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
224 #else
225 __asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3));
226 #ifdef __ARMEB__
227 insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3));
228 #else
229 insn = (uint16_t) (insn >> ((va & 2) << 3));
230 #endif
231 #endif
232 } else {
233 insn = *(const uint16_t *)va;
234 }
235 #ifdef _ARM_ARCH_BE8
236 insn = bswap16(insn);
237 #endif
238 return insn;
239 }
240
241 /*
242 * Random cruft
243 */
244
245 struct lwp;
246
247 /* cpu.c */
248 void identify_arm_cpu(device_t, struct cpu_info *);
249
250 /* cpuswitch.S */
251 struct pcb;
252 void savectx(struct pcb *);
253
254 /* ast.c */
255 void userret(struct lwp *);
256
257 /* *_machdep.c */
258 void bootsync(void);
259
260 /* fault.c */
261 int badaddr_read(void *, size_t, void *);
262
263 /* syscall.c */
264 void swi_handler(trapframe_t *);
265
266 /* vfp_init.c */
267 void vfp_detect(struct cpu_info *);
268 void vfp_attach(struct cpu_info *);
269 void vfp_discardcontext(lwp_t *, bool);
270 void vfp_savecontext(lwp_t *);
271 void vfp_kernel_acquire(void);
272 void vfp_kernel_release(void);
273 bool vfp_used_p(const lwp_t *);
274 extern const pcu_ops_t arm_vfp_ops;
275
276 #endif /* !_LOCORE */
277
278 #elif defined(__aarch64__)
279
280 #include <aarch64/locore.h>
281
282 #endif /* __arm__/__aarch64__ */
283
284 #endif /* !_ARM_LOCORE_H_ */
285