xref: /netbsd/sys/dev/ic/arn9003reg.h (revision e480ee86)
1 /*	$NetBSD: arn9003reg.h,v 1.1 2013/03/30 02:53:01 christos Exp $	*/
2 /*	$OpenBSD: ar9003reg.h,v 1.8 2012/10/20 09:53:32 stsp Exp $	*/
3 
4 /*-
5  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
6  * Copyright (c) 2010 Atheros Communications Inc.
7  *
8  * Permission to use, copy, modify, and/or distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  */
20 
21 #ifndef _ARN9003REG_H_
22 #define _ARN9003REG_H_
23 
24 /*
25  * MAC registers.
26  */
27 #define AR_ISR_S2_S			0x00d0
28 #define AR_ISR_S3_S			0x00d4
29 #define AR_ISR_S4_S			0x00d8
30 #define AR_ISR_S5_S			0x00dc
31 #define AR_GPIO_IN_OUT			0x4048
32 #define AR_GPIO_IN			0x404c
33 #define AR9300_GPIO_IN_VAL		0x0001FFFF
34 #define AR_GPIO_OE_OUT			0x4050
35 #define AR_GPIO_INTR_POL		0x4058
36 #define AR_GPIO_INPUT_EN_VAL		0x405c
37 #define AR_GPIO_INPUT_MUX1		0x4060
38 #define AR_GPIO_INPUT_MUX2		0x4064
39 #define AR_GPIO_OUTPUT_MUX(i)		(0x4068 + (i) * 4)
40 #define AR_INPUT_STATE			0x4074
41 #define AR_EEPROM_STATUS_DATA		0x4084
42 #define AR_OBS				0x4088
43 #define AR_GPIO_PDPU			0x4090
44 #define AR_PCIE_MSI			0x40a4
45 #define AR_ENT_OTP			0x40d8
46 
47 /* Bits for AR_ENT_OTP. */
48 #define AR_ENT_OTP_CHAIN2_DISABLE	0x00020000
49 #define AR_ENT_OTP_MPSD			0x00800000
50 
51 /*
52  * PHY registers.
53  */
54 #define AR_PHY_TIMING1			0x09800
55 #define AR_PHY_TIMING2			0x09804
56 #define AR_PHY_TIMING3			0x09808
57 #define AR_PHY_TIMING4			0x0980c
58 #define AR_PHY_TIMING5			0x09810
59 #define AR_PHY_TIMING6			0x09814
60 #define AR_PHY_TIMING11			0x09818
61 #define AR_PHY_SPUR_REG			0x0981c
62 #define AR_PHY_FIND_SIG_LOW		0x09820
63 #define AR_PHY_SFCORR			0x09824
64 #define AR_PHY_SFCORR_LOW		0x09828
65 #define AR_PHY_SFCORR_EXT		0x0982c
66 #define AR_PHY_EXT_CCA(i)		(0x09830 + (i) * 0x1000)
67 #define AR_PHY_RADAR_0			0x09834
68 #define AR_PHY_RADAR_1			0x09838
69 #define AR_PHY_RADAR_EXT		0x0983c
70 #define AR_PHY_MULTICHAIN_CTRL		0x09880
71 #define AR_PHY_PERCHAIN_CSD		0x09884
72 #define AR_PHY_TX_CRC			0x098a0
73 #define AR_PHY_TST_DAC_CONST		0x098a4
74 #define AR_PHY_SPUR_REPORT_0		0x098a8
75 #define AR_PHY_TX_IQCAL_CONTROL_3	0x098b0
76 #define AR_PHY_IQ_ADC_MEAS_0_B(i)	(0x098c0 + (i) * 0x1000)
77 #define AR_PHY_IQ_ADC_MEAS_1_B(i)	(0x098c4 + (i) * 0x1000)
78 #define AR_PHY_IQ_ADC_MEAS_2_B(i)	(0x098c8 + (i) * 0x1000)
79 #define AR_PHY_IQ_ADC_MEAS_3_B(i)	(0x098cc + (i) * 0x1000)
80 #define AR_PHY_TX_PHASE_RAMP_0		0x098d0
81 #define AR_PHY_ADC_DC_GAIN_CORR(i)	(0x098d4 + (i) * 0x1000)
82 #define AR_PHY_RX_IQCAL_CORR_B(i)	(0x098dc + (i) * 0x1000)
83 #define AR_PHY_PAPRD_AM2AM		0x098e4
84 #define AR_PHY_PAPRD_AM2PM		0x098e8
85 #define AR_PHY_PAPRD_HT40		0x098ec
86 #define AR_PHY_PAPRD_CTRL0_B(i)		(0x098f0 + (i) * 0x1000)
87 #define AR_PHY_PAPRD_CTRL1_B(i)		(0x098f4 + (i) * 0x1000)
88 #define AR_PHY_PA_GAIN123_B(i)		(0x098f8 + (i) * 0x1000)
89 #define AR_PHY_PAPRD_PRE_POST_SCALE_B0(i)	\
90 					(0x09900 + (i) * 4)
91 #define AR_PHY_PAPRD_MEM_TAB_B(i, j)	(0x09920 + (i) * 0x1000 + (j) * 4)
92 #define AR_PHY_CHAN_INFO_TAB(i, j)	(0x09b00 + (i) * 0x1000 + (j) * 4)
93 #define AR_PHY_TIMING_3A		0x09c00
94 #define AR_PHY_LDPC_CNTL1		0x09c04
95 #define AR_PHY_LDPC_CNTL2		0x09c08
96 #define AR_PHY_PILOT_SPUR_MASK		0x09c0c
97 #define AR_PHY_CHAN_SPUR_MASK		0x09c10
98 #define AR_PHY_SGI_DELTA		0x09c14
99 #define AR_PHY_ML_CNTL_1		0x09c18
100 #define AR_PHY_ML_CNTL_2		0x09c1c
101 #define AR_PHY_TST_ADC			0x09c20
102 #define AR_PHY_SETTLING			0x09e00
103 #define AR_PHY_RXGAIN(i)		(0x09e04 + (i) * 0x1000)
104 #define AR_PHY_GAINS_MINOFF0		0x09e08
105 #define AR_PHY_DESIRED_SZ		0x09e0c
106 #define AR_PHY_FIND_SIG			0x09e10
107 #define AR_PHY_AGC			0x09e14
108 #define AR_PHY_EXT_ATTEN_CTL(i)		(0x09e18 + (i) * 0x1000)
109 #define AR_PHY_CCA(i)			(0x09e1c + (i) * 0x1000)
110 #define AR_PHY_CCA_CTRL(i)		(0x09e20 + (i) * 0x1000)
111 #define AR_PHY_RESTART			0x09e24
112 #define AR_PHY_MC_GAIN_CTRL		0x09e28
113 #define AR_PHY_EXTCHN_PWRTHR1		0x09e2c
114 #define AR_PHY_EXT_CHN_WIN		0x09e30
115 #define AR_PHY_20_40_DET_THR		0x09e34
116 #define AR_PHY_RIFS_SRCH		0x09e38
117 #define AR_PHY_PEAK_DET_CTRL_1		0x09e3c
118 #define AR_PHY_PEAK_DET_CTRL_2		0x09e40
119 #define AR_PHY_RX_GAIN_BOUNDS_1		0x09e44
120 #define AR_PHY_RX_GAIN_BOUNDS_2		0x09e48
121 #define AR_PHY_RSSI(i)			(0x09f80 + (i) * 0x1000)
122 #define AR_PHY_SPUR_CCK_REP0		0x09f84
123 #define AR_PHY_CCK_DETECT		0x09fc0
124 #define AR_PHY_DAG_CTRLCCK		0x09fc4
125 #define AR_PHY_IQCORR_CTRL_CCK		0x09fc8
126 #define AR_PHY_CCK_SPUR_MIT		0x09fcc
127 #define AR_PHY_RX_OCGAIN		0x0a000
128 #define AR_PHY_D2_CHIP_ID		0x0a200
129 #define AR_PHY_GEN_CTRL			0x0a204
130 #define AR_PHY_MODE			0x0a208
131 #define AR_PHY_ACTIVE			0x0a20c
132 #define AR_PHY_SPUR_MASK_A		0x0a220
133 #define AR_PHY_SPUR_MASK_B		0x0a224
134 #define AR_PHY_SPECTRAL_SCAN		0x0a228
135 #define AR_PHY_RADAR_BW_FILTER		0x0a22c
136 #define AR_PHY_SEARCH_START_DELAY	0x0a230
137 #define AR_PHY_MAX_RX_LEN		0x0a234
138 #define AR_PHY_FRAME_CTL		0x0a238
139 #define AR_PHY_RFBUS_REQ		0x0a23c
140 #define AR_PHY_RFBUS_GRANT		0x0a240
141 #define AR_PHY_RIFS			0x0a244
142 #define AR_PHY_RX_CLR_DELAY		0x0a250
143 #define AR_PHY_RX_DELAY			0x0a254
144 #define AR_PHY_XPA_TIMING_CTL		0x0a264
145 #define AR_PHY_MISC_PA_CTL		0x0a280
146 #define AR_PHY_SWITCH_CHAIN(i)		(0x0a284 + (i) * 0x1000)
147 #define AR_PHY_SWITCH_COM		0x0a288
148 #define AR_PHY_SWITCH_COM_2		0x0a28c
149 #define AR_PHY_RX_CHAINMASK		0x0a2a0
150 #define AR_PHY_CAL_CHAINMASK		0x0a2c0
151 #define AR_PHY_AGC_CONTROL		0x0a2c4
152 #define AR_PHY_CALMODE			0x0a2c8
153 #define AR_PHY_FCAL_1			0x0a2cc
154 #define AR_PHY_FCAL_2_0			0x0a2d0
155 #define AR_PHY_DFT_TONE_CTL_0		0x0a2d4
156 #define AR_PHY_CL_CAL_CTL		0x0a2d8
157 #define AR_PHY_CL_TAB_0			0x0a300
158 #define AR_PHY_SYNTH_CONTROL		0x0a340
159 #define AR_PHY_ADDAC_CLK_SEL		0x0a344
160 #define AR_PHY_PLL_CTL			0x0a348
161 #define AR_PHY_ANALOG_SWAP		0x0a34c
162 #define AR_PHY_ADDAC_PARA_CTL		0x0a350
163 #define AR_PHY_XPA_CFG			0x0a358
164 #define AR_PHY_TEST			0x0a360
165 #define AR_PHY_TEST_CTL_STATUS		0x0a364
166 #define AR_PHY_TSTDAC			0x0a368
167 #define AR_PHY_CHAN_STATUS		0x0a36c
168 #define AR_PHY_CHAN_INFO_MEMORY		0x0a370
169 #define AR_PHY_CHNINFO_NOISEPWR		0x0a374
170 #define AR_PHY_CHNINFO_GAINDIFF		0x0a378
171 #define AR_PHY_CHNINFO_FINETIM		0x0a37c
172 #define AR_PHY_CHAN_INFO_GAIN_0		0x0a380
173 #define AR_PHY_SCRAMBLER_SEED		0x0a390
174 #define AR_PHY_CCK_TX_CTRL		0x0a394
175 #define AR_PHY_HEAVYCLIP_CTL		0x0a3a4
176 #define AR_PHY_HEAVYCLIP_20		0x0a3a8
177 #define AR_PHY_HEAVYCLIP_40		0x0a3ac
178 #define AR_PHY_ILLEGAL_TXRATE		0x0a3b0
179 #define AR_PHY_PWRTX_RATE1		0x0a3c0
180 #define AR_PHY_PWRTX_RATE2		0x0a3c4
181 #define AR_PHY_PWRTX_RATE3		0x0a3c8
182 #define AR_PHY_PWRTX_RATE4		0x0a3cc
183 #define AR_PHY_PWRTX_RATE5		0x0a3d0
184 #define AR_PHY_PWRTX_RATE6		0x0a3d4
185 #define AR_PHY_PWRTX_RATE7		0x0a3d8
186 #define AR_PHY_PWRTX_RATE8		0x0a3dc
187 #define AR_PHY_PWRTX_RATE10		0x0a3e4
188 #define AR_PHY_PWRTX_RATE11		0x0a3e8
189 #define AR_PHY_PWRTX_RATE12		0x0a3ec
190 #define AR_PHY_PWRTX_MAX		0x0a3f0
191 #define AR_PHY_POWER_TX_SUB		0x0a3f4
192 #define AR_PHY_TPC_1			0x0a3f8
193 #define AR_PHY_TPC_4_B(i)		(0x0a404 + (i) * 0x1000)
194 #define AR_PHY_TPC_5_B(i)		(0x0a408 + (i) * 0x1000)
195 #define AR_PHY_TPC_6_B(i)		(0x0a40c + (i) * 0x1000)
196 #define AR_PHY_TPC_11_B(i)		(0x0a420 + (i) * 0x1000)
197 #define AR_PHY_TPC_12			0x0a424
198 #define AR_PHY_TPC_18			0x0a43c
199 #define AR_PHY_TPC_19			0x0a440
200 #define AR_PHY_BB_THERM_ADC_1		0x0a448
201 #define AR_PHY_BB_THERM_ADC_4		0x0a454
202 #define AR_PHY_TX_FORCED_GAIN		0x0a458
203 #define AR_PHY_PDADC_TAB(i)		(0x0a480 + (i) * 0x1000)
204 #define AR_PHY_TXGAIN_TABLE(i)		(0x0a500 + (i) * 4)
205 #define AR_PHY_TX_IQCAL_CONTROL_1	0x0a648
206 #define AR_PHY_TX_IQCAL_START		0x0a640
207 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)	\
208 					(0x0a650 + (i) * 0x1000)
209 #define AR_PHY_TX_IQCAL_STATUS_B(i)	(0x0a68c + (i) * 0x1000)
210 #define AR_PHY_PAPRD_TRAINER_CNTL1	0x0a690
211 #define AR_PHY_PAPRD_TRAINER_CNTL2	0x0a694
212 #define AR_PHY_PAPRD_TRAINER_CNTL3	0x0a698
213 #define AR_PHY_PAPRD_TRAINER_CNTL4	0x0a69c
214 #define AR_PHY_PAPRD_TRAINER_STAT1	0x0a6a0
215 #define AR_PHY_PAPRD_TRAINER_STAT2	0x0a6a4
216 #define AR_PHY_PAPRD_TRAINER_STAT3	0x0a6a8
217 #define AR_PHY_PANIC_WD_STATUS		0x0a7c0
218 #define AR_PHY_PANIC_WD_CTL_1		0x0a7c4
219 #define AR_PHY_PANIC_WD_CTL_2		0x0a7c8
220 #define AR_PHY_BT_CTL			0x0a7cc
221 #define AR_PHY_ONLY_WARMRESET		0x0a7d0
222 #define AR_PHY_ONLY_CTL			0x0a7d4
223 #define AR_PHY_ECO_CTRL			0x0a7dc
224 
225 /*
226  * Analog registers.
227  */
228 #define AR_IS_ANALOG_REG(reg)		((reg) >= 0x16000 && (reg) <= 0x17000)
229 #define AR_PHY_65NM_CH0_SYNTH4		0x1608c
230 #define AR_PHY_65NM_CH0_SYNTH7		0x16098
231 #define AR_PHY_65NM_CH0_BIAS1		0x160c0
232 #define AR_PHY_65NM_CH0_BIAS2		0x160c4
233 #define AR_PHY_65NM_CH0_BIAS4		0x160cc
234 #define AR_PHY_65NM_CH0_RXTX1		0x16100
235 #define AR_PHY_65NM_CH0_RXTX2		0x16104
236 #define AR_PHY_65NM_CH0_RXTX4		0x1610c
237 #define AR9485_PHY_65NM_CH0_TOP2	0x16284
238 #define AR_PHY_65NM_CH0_TOP		0x16288
239 #define AR_PHY_65NM_CH0_THERM		0x16290
240 #define AR9485_PHY_CH0_XTAL		0x16290
241 #define AR_PHY_65NM_CH1_RXTX1		0x16500
242 #define AR_PHY_65NM_CH1_RXTX2		0x16504
243 #define AR_PHY_65NM_CH2_RXTX1		0x16900
244 #define AR_PHY_65NM_CH2_RXTX2		0x16904
245 #define AR_PHY_PMU1			0x16c40
246 #define AR_PHY_PMU2			0x16c44
247 
248 
249 /* Bits for AR_PHY_TIMING2. */
250 #define AR_PHY_TIMING2_FORCE_PPM_VAL_M	0x00000fff
251 #define AR_PHY_TIMING2_FORCE_PPM_VAL_S	0
252 #define AR_PHY_TIMING2_USE_FORCE_PPM	0x00001000
253 
254 /* Bits for AR_PHY_TIMING3. */
255 #define AR_PHY_TIMING3_DSC_EXP_M	0x0001e000
256 #define AR_PHY_TIMING3_DSC_EXP_S	13
257 #define AR_PHY_TIMING3_DSC_MAN_M	0xfffe0000
258 #define AR_PHY_TIMING3_DSC_MAN_S	17
259 
260 /* Bits for AR_PHY_TIMING4. */
261 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M	0x0000f000
262 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S	12
263 #define AR_PHY_TIMING4_DO_CAL			0x00010000
264 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK	0x10000000
265 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK		0x20000000
266 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER	0x40000000
267 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI		0x80000000
268 
269 /* Bits for AR_PHY_TIMING5. */
270 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE	0x00000001
271 #define AR_PHY_TIMING5_CYCPWR_THR1_M		0x000000fe
272 #define AR_PHY_TIMING5_CYCPWR_THR1_S		1
273 #define AR_PHY_TIMING5_RSSI_THR1A_ENA		0x00008000
274 #define AR_PHY_TIMING5_CYCPWR_THR1A_M		0x007f0000
275 #define AR_PHY_TIMING5_CYCPWR_THR1A_S		16
276 #define AR_PHY_TIMING5_RSSI_THR1A_M		0x007f0000
277 #define AR_PHY_TIMING5_RSSI_THR1A_S		16
278 
279 /* Bits for AR_PHY_TIMING11. */
280 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M		0x000fffff
281 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S		0
282 #define AR_PHY_TIMING11_SPUR_FREQ_SD_M			0x3ff00000
283 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S			20
284 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC		0x40000000
285 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR	0x80000000
286 
287 /* Bits for AR_PHY_SPUR_REG. */
288 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M	0x000000ff
289 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
290 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI	0x00000100
291 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x00020000
292 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M	0x03fc0000
293 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S	18
294 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT	0x04000000
295 
296 /* Bits for AR_PHY_FIND_SIG_LOW. */
297 #define AR_PHY_FIND_SIG_LOW_RELSTEP_M		0x0000001f
298 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S		0
299 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M	0x00000fc0
300 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S	6
301 #define AR_PHY_FIND_SIG_LOW_FIRPWR_M		0x0007f000
302 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S		12
303 
304 /* Bits for AR_PHY_SFCORR. */
305 #define AR_PHY_SFCORR_M2COUNT_THR_M		0x0000001f
306 #define AR_PHY_SFCORR_M2COUNT_THR_S		0
307 #define AR_PHY_SFCORR_M1_THRESH_M		0x00fe0000
308 #define AR_PHY_SFCORR_M1_THRESH_S		17
309 #define AR_PHY_SFCORR_M2_THRESH_M		0x7f000000
310 #define AR_PHY_SFCORR_M2_THRESH_S		24
311 
312 /* Bits for AR_PHY_SFCORR_LOW. */
313 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
314 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M	0x00003f00
315 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
316 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M	0x001fc000
317 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
318 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M	0x0fe00000
319 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21
320 
321 /* Bits for AR_PHY_SFCORR_EXT. */
322 #define AR_PHY_SFCORR_EXT_M1_THRESH_M		0x0000007f
323 #define AR_PHY_SFCORR_EXT_M1_THRESH_S		0
324 #define AR_PHY_SFCORR_EXT_M2_THRESH_M		0x00003f80
325 #define AR_PHY_SFCORR_EXT_M2_THRESH_S		7
326 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M	0x001fc000
327 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
328 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M	0x0fe00000
329 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
330 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD	0x10000000
331 
332 /* Bits for AR_PHY_RADAR_0. */
333 #define AR_PHY_RADAR_0_ENA		0x00000001
334 #define AR_PHY_RADAR_0_INBAND_M		0x0000003e
335 #define AR_PHY_RADAR_0_INBAND_S		1
336 #define AR_PHY_RADAR_0_PRSSI_M		0x00000fc0
337 #define AR_PHY_RADAR_0_PRSSI_S		6
338 #define AR_PHY_RADAR_0_HEIGHT_M		0x0003f000
339 #define AR_PHY_RADAR_0_HEIGHT_S		12
340 #define AR_PHY_RADAR_0_RRSSI_M		0x00fc0000
341 #define AR_PHY_RADAR_0_RRSSI_S		18
342 #define AR_PHY_RADAR_0_FIRPWR_M		0x7f000000
343 #define AR_PHY_RADAR_0_FIRPWR_S		24
344 #define AR_PHY_RADAR_0_FFT_ENA		0x80000000
345 
346 /* Bits for AR_PHY_RADAR_1. */
347 #define AR_PHY_RADAR_1_MAXLEN_M		0x000000ff
348 #define AR_PHY_RADAR_1_MAXLEN_S		0
349 #define AR_PHY_RADAR_1_RELSTEP_THRESH_M	0x00001f00
350 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
351 #define AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
352 #define AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
353 #define AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
354 #define AR_PHY_RADAR_1_RELPWR_THRESH_M	0x003f0000
355 #define AR_PHY_RADAR_1_RELPWR_THRESH_S	16
356 #define AR_PHY_RADAR_1_USE_FIR128	0x00400000
357 #define AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
358 
359 /* Bits for AR_PHY_RADAR_EXT. */
360 #define AR_PHY_RADAR_EXT_ENA		0x00004000
361 #define AR_PHY_RADAR_DC_PWR_THRESH_M	0x007f8000
362 #define AR_PHY_RADAR_DC_PWR_THRESH_S	15
363 #define AR_PHY_RADAR_LB_DC_CAP_M  	0x7f800000
364 #define AR_PHY_RADAR_LB_DC_CAP_S	23
365 
366 /* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */
367 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN	0x80000000
368 
369 /* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */
370 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M		0x0000007f
371 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S		0
372 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M		0x00003f80
373 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S		7
374 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE		0x00004000
375 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M	0x003f8000
376 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S	15
377 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M	0x1fc00000
378 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S	22
379 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN	0x20000000
380 
381 /* Bits for AR_PHY_PAPRD_AM2AM. */
382 #define AR_PHY_PAPRD_AM2AM_MASK_M	0x01ffffff
383 #define AR_PHY_PAPRD_AM2AM_MASK_S	0
384 
385 /* Bits for AR_PHY_PAPRD_AM2PM. */
386 #define AR_PHY_PAPRD_AM2PM_MASK_M	0x01ffffff
387 #define AR_PHY_PAPRD_AM2PM_MASK_S	0
388 
389 /* Bits for AR_PHY_PAPRD_HT40. */
390 #define AR_PHY_PAPRD_HT40_MASK_M	0x01ffffff
391 #define AR_PHY_PAPRD_HT40_MASK_S	0
392 
393 /* Bits for AR_PHY_PAPRD_CTRL0_B(i). */
394 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE		0x00000001
395 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE	0x00000002
396 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_M	0xf8000000
397 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S	27
398 
399 /* Bits for AR_PHY_PAPRD_CTRL1_B(i). */
400 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA		0x00000001
401 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA		0x00000002
402 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA		0x00000004
403 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_M		0x000001f8
404 #define AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL_S		3
405 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_M		0x0001fe00
406 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_S		9
407 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_M		0x0ffe0000
408 #define AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT_S		17
409 
410 /* Bits for AR_PHY_PA_GAIN123_B(i). */
411 #define AR_PHY_PA_GAIN123_PA_GAIN1_M	0x000003ff
412 #define AR_PHY_PA_GAIN123_PA_GAIN1_S	0
413 
414 /* Bits for AR_PHY_PAPRD_PRE_POST_SCALE_B0(i). */
415 #define AR_PHY_PAPRD_PRE_POST_SCALING_M	0x0003ffff
416 #define AR_PHY_PAPRD_PRE_POST_SCALING_S	0
417 
418 /* Bits for AR_PHY_PAPRD_MEM_TAB_B(i). */
419 #define AR_PHY_PAPRD_ANGLE_M	0x000007ff
420 #define AR_PHY_PAPRD_ANGLE_S	0
421 #define AR_PHY_PAPRD_PA_IN_M	0x003ff800
422 #define AR_PHY_PAPRD_PA_IN_S	11
423 
424 /* Bits for AR_PHY_PILOT_SPUR_MASK. */
425 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M	0x0000001f
426 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S	0
427 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M	0x00000fe0
428 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S	5
429 
430 /* Bits for AR_PHY_CHAN_SPUR_MASK. */
431 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M		0x0000001f
432 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S		0
433 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M	0x00000fe0
434 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S	5
435 
436 /* Bits for AR_PHY_SGI_DELTA. */
437 #define AR_PHY_SGI_DSC_EXP_M	0x0000000f
438 #define AR_PHY_SGI_DSC_EXP_S	0
439 #define AR_PHY_SGI_DSC_MAN_M	0x0007fff0
440 #define AR_PHY_SGI_DSC_MAN_S	4
441 
442 /* Bits for AR_PHY_SETTLING. */
443 #define AR_PHY_SETTLING_SWITCH_M	0x00003f80
444 #define AR_PHY_SETTLING_SWITCH_S	7
445 
446 /* Bits for AR_PHY_RXGAIN(i). */
447 #define AR_PHY_RXGAIN_TXRX_ATTEN_M	0x0003f000
448 #define AR_PHY_RXGAIN_TXRX_ATTEN_S	12
449 #define AR_PHY_RXGAIN_TXRX_RF_MAX_M	0x007c0000
450 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
451 
452 /* Bits for AR_PHY_DESIRED_SZ. */
453 #define AR_PHY_DESIRED_SZ_ADC_M		0x000000ff
454 #define AR_PHY_DESIRED_SZ_ADC_S		0
455 #define AR_PHY_DESIRED_SZ_PGA_M		0x0000ff00
456 #define AR_PHY_DESIRED_SZ_PGA_S		8
457 #define AR_PHY_DESIRED_SZ_TOT_DES_M	0x0ff00000
458 #define AR_PHY_DESIRED_SZ_TOT_DES_S	20
459 
460 /* Bits for AR_PHY_FIND_SIG. */
461 #define AR_PHY_FIND_SIG_RELSTEP_M	0x0000001f
462 #define AR_PHY_FIND_SIG_RELSTEP_S	0
463 #define AR_PHY_FIND_SIG_RELPWR_M	0x000007c0
464 #define AR_PHY_FIND_SIG_RELPWR_S	6
465 #define AR_PHY_FIND_SIG_FIRSTEP_M	0x0003f000
466 #define AR_PHY_FIND_SIG_FIRSTEP_S	12
467 #define AR_PHY_FIND_SIG_FIRPWR_M	0x03fc0000
468 #define AR_PHY_FIND_SIG_FIRPWR_S	18
469 
470 /* Bits for AR_PHY_AGC. */
471 #define AR_PHY_AGC_COARSE_PWR_CONST_M	0x0000007f
472 #define AR_PHY_AGC_COARSE_PWR_CONST_S	0
473 #define AR_PHY_AGC_COARSE_LOW_M		0x00007f80
474 #define AR_PHY_AGC_COARSE_LOW_S		7
475 #define AR_PHY_AGC_COARSE_HIGH_M	0x003f8000
476 #define AR_PHY_AGC_COARSE_HIGH_S	15
477 
478 /* Bits for AR_PHY_EXT_ATTEN_CTL(i). */
479 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M	0x0000001f
480 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S	0
481 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M	0x0000003f
482 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S	0
483 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M	0x00000fc0
484 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S	6
485 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M	0x00003c00
486 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S	10
487 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M	0x0001f000
488 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S	12
489 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M	0x003e0000
490 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S	17
491 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M	0x00fc0000
492 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S	18
493 
494 /* Bits for AR_PHY_CCA(i). */
495 #define AR_PHY_MAXCCA_PWR_M	0x000001ff
496 #define AR_PHY_MAXCCA_PWR_S	0
497 #define AR_PHY_MINCCA_PWR_M	0x1ff00000
498 #define AR_PHY_MINCCA_PWR_S	20
499 
500 /* Bits for AR_PHY_EXT_CCA(i). */
501 #define AR_PHY_EXT_MAXCCA_PWR_M		0x000001ff
502 #define AR_PHY_EXT_MAXCCA_PWR_S		0
503 #define AR_PHY_EXT_MINCCA_PWR_M		0x01ff0000
504 #define AR_PHY_EXT_MINCCA_PWR_S		16
505 
506 /* Bits for AR_PHY_RESTART. */
507 #define AR_PHY_RESTART_ENA	0x00000001
508 #define AR_PHY_RESTART_DIV_GC_M	0x001c0000
509 #define AR_PHY_RESTART_DIV_GC_S	18
510 
511 /* Bits for AR_PHY_MC_GAIN_CTRL. */
512 #define AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV	0x01000000
513 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_M	0x7e000000
514 #define AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL_S	25
515 
516 /* Bits for AR_PHY_CCK_DETECT. */
517 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M		0x0000003f
518 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S		0
519 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M		0x00001fc0
520 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
521 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x00002000
522 
523 /* Bits for AR_PHY_DAG_CTRLCCK. */
524 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
525 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_M	0x0001fc00
526 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10
527 
528 /* Bits for AR_PHY_CCK_SPUR_MIT. */
529 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT	0x00000001
530 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M	0x000001fe
531 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S	1
532 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M	0x1ffffe00
533 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S	9
534 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M	0x60000000
535 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S  29
536 
537 /* Bits for AR_PHY_GEN_CTRL. */
538 #define AR_PHY_GC_TURBO_MODE		0x00000001
539 #define AR_PHY_GC_TURBO_SHORT		0x00000002
540 #define AR_PHY_GC_DYN2040_EN		0x00000004
541 #define AR_PHY_GC_DYN2040_PRI_ONLY	0x00000008
542 #define AR_PHY_GC_DYN2040_PRI_CH	0x00000010
543 #define AR_PHY_GC_DYN2040_EXT_CH	0x00000020
544 #define AR_PHY_GC_HT_EN			0x00000040
545 #define AR_PHY_GC_SHORT_GI_40		0x00000080
546 #define AR_PHY_GC_WALSH			0x00000100
547 #define AR_PHY_GC_SINGLE_HT_LTF1	0x00000200
548 #define AR_PHY_GC_GF_DETECT_EN		0x00000400
549 #define AR_PHY_GC_ENABLE_DAC_FIFO	0x00000800
550 
551 /* Bits for AR_PHY_MODE. */
552 #define AR_PHY_MODE_OFDM		0x00000000
553 #define AR_PHY_MODE_CCK			0x00000001
554 #define AR_PHY_MODE_DYNAMIC		0x00000004
555 #define AR_PHY_MODE_HALF		0x00000020
556 #define AR_PHY_MODE_QUARTER		0x00000040
557 #define AR_PHY_MODE_DYN_CCK_DISABLE	0x00000100
558 #define AR_PHY_MODE_SVD_HALF		0x00000200
559 
560 /* Bits for AR_PHY_ACTIVE. */
561 #define AR_PHY_ACTIVE_DIS	0x00000000
562 #define AR_PHY_ACTIVE_EN	0x00000001
563 
564 /* Bits for AR_PHY_SPUR_MASK_A. */
565 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M	0x000003ff
566 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S	0
567 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M	0x0001fc00
568 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S	10
569 
570 /* Bits for AR_PHY_SPECTRAL_SCAN. */
571 #define AR_PHY_SPECTRAL_SCAN_ENABLE		0x00000001
572 #define AR_PHY_SPECTRAL_SCAN_ACTIVE		0x00000002
573 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M	0x000000f0
574 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S	4
575 #define AR_PHY_SPECTRAL_SCAN_PERIOD_M		0x0000ff00
576 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S		8
577 #define AR_PHY_SPECTRAL_SCAN_COUNT_M		0x00ff0000
578 #define AR_PHY_SPECTRAL_SCAN_COUNT_S		16
579 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT	0x01000000
580 
581 /* Bits for AR_PHY_RFBUS_REQ. */
582 #define AR_PHY_RFBUS_REQ_EN	0x00000001
583 
584 /* Bits for AR_PHY_RFBUS_GRANT. */
585 #define AR_PHY_RFBUS_GRANT_EN	0x00000001
586 
587 /* Bits for AR_PHY_RIFS. */
588 #define AR_PHY_RIFS_INIT_DELAY	0x3ff0000
589 
590 /* Bits for AR_PHY_RX_DELAY. */
591 #define AR_PHY_RX_DELAY_DELAY_M	0x00003fff
592 #define AR_PHY_RX_DELAY_DELAY_S	0
593 
594 /* Bits for AR_PHY_XPA_TIMING_CTL. */
595 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M	0x000000ff
596 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S	0
597 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M	0x0000ff00
598 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S	8
599 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M	0x00ff0000
600 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S	16
601 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M	0xff000000
602 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S	24
603 
604 /* Bits for AR_PHY_SWITCH_CHAIN. */
605 #define AR_SWITCH_TABLE_ALL_M	0x00000fff
606 #define AR_SWITCH_TABLE_ALL_S	0
607 
608 /* Bits for AR_PHY_SWITCH_COM. */
609 #define AR_SWITCH_TABLE_COM_ALL_M	0x0000ffff
610 #define AR_SWITCH_TABLE_COM_ALL_S	0
611 
612 /* Bits for AR_SWITCH_TABLE_COM_2. */
613 #define AR_SWITCH_TABLE_COM_2_ALL_M	0x00ffffff
614 #define AR_SWITCH_TABLE_COM_2_ALL_S	0
615 
616 /* Bits for AR_PHY_AGC_CONTROL. */
617 #define AR_PHY_AGC_CONTROL_CAL			0x00000001
618 #define AR_PHY_AGC_CONTROL_NF			0x00000002
619 #define AR_PHY_AGC_CONTROL_YCOK_MAX_M		0x000003c0
620 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S		6
621 #define AR_PHY_AGC_CONTROL_OFFSET_CAL		0x00000800
622 #define AR_PHY_AGC_CONTROL_ENABLE_NF		0x00008000
623 #define AR_PHY_AGC_CONTROL_FLTR_CAL		0x00010000
624 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000
625 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000
626 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000
627 
628 /* Bits for AR_PHY_CALMODE. */
629 #define AR_PHY_CALMODE_IQ		0x00000000
630 #define AR_PHY_CALMODE_ADC_GAIN		0x00000001
631 #define AR_PHY_CALMODE_ADC_DC_PER	0x00000002
632 #define AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
633 
634 /* Bits for AR_PHY_FCAL_2_0. */
635 #define AR_PHY_FCAL20_CAP_STATUS_0_M	0x01f00000
636 #define AR_PHY_FCAL20_CAP_STATUS_0_S	20
637 
638 /* Bits for AR_PHY_SYNTH_CONTROL. */
639 #define AR9380_BMODE	0x20000000
640 
641 /* Bits for AR_PHY_ANALOG_SWAP. */
642 #define AR_PHY_SWAP_ALT_CHAIN	0x00000040
643 
644 /* Bits for AR_PHY_ADDAC_PARA_CTL. */
645 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC	0x00008000
646 
647 /* Bits for AR_PHY_TEST. */
648 #define AR_PHY_TEST_RFSILENT_BB		0x00002000
649 #define AR_PHY_TEST_BBB_OBS_SEL_M	0x00780000
650 #define AR_PHY_TEST_BBB_OBS_SEL_S	19
651 #define AR_PHY_TEST_RX_OBS_SEL_BIT5	0x00800000
652 #define AR_PHY_TEST_CHAIN_SEL_M		0xc0000000
653 #define AR_PHY_TEST_CHAIN_SEL_S		30
654 
655 /* Bits for AR_PHY_TEST_CTL_STATUS. */
656 #define AR_PHY_TEST_CTL_TSTDAC_EN		0x00000001
657 #define AR_PHY_TEST_CTL_TX_OBS_SEL_M		0x0000001c
658 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S		2
659 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M	0x00000060
660 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S	5
661 #define AR_PHY_TEST_CTL_TSTADC_EN		0x00000100
662 #define AR_PHY_TEST_CTL_RX_OBS_SEL_M		0x00003c00
663 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S		10
664 
665 /* Bits for AR_PHY_CHAN_INFO_MEMORY. */
666 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x00000001
667 #define AR_PHY_CHAN_INFO_TAB_S2_READ		0x00000008
668 
669 /* Bits for AR_PHY_CHAN_INFO_GAIN_0. */
670 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK	0x00000fff
671 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320
672 
673 /* Bits for AR_PHY_CCK_TX_CTRL. */
674 #define AR_PHY_CCK_TX_CTRL_JAPAN	0x00000010
675 
676 /* Bits for AR_PHY_PWRTX_RATE5. */
677 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_M	0x0000003f
678 #define AR_PHY_PWRTX_RATE5_POWERTXHT20_0_S	0
679 
680 /* Bits for AR_PHY_PWRTX_MAX. */
681 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
682 
683 /* Bits for AR_PHY_TPC_1. */
684 #define AR_PHY_TPC_1_FORCE_DAC_GAIN	0x00000001
685 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_M	0x0000003e
686 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S	1
687 
688 /* Bits for AR_PHY_TPC_5_B(i). */
689 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_M		0x0000000f
690 #define AR_PHY_TPC_5_PD_GAIN_OVERLAP_S		0
691 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_M	0x000003f0
692 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_1_S	4
693 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_M	0x0000fc00
694 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_2_S	10
695 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_M	0x003f0000
696 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_3_S	16
697 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_M	0x0fc00000
698 #define AR_PHY_TPC_5_PD_GAIN_BOUNDARY_4_S	22
699 
700 /* Bits for AR_PHY_TPC_6_B(i). */
701 #define AR_PHY_TPC_6_ERROR_EST_MODE_M	0x03000000
702 #define AR_PHY_TPC_6_ERROR_EST_MODE_S	24
703 
704 /* Bits for AR_PHY_TPC_11_B(i). */
705 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_M		0x00ff0000
706 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S		16
707 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_M	0xff000000
708 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_PAL_ON_S	24
709 
710 /* Bits for AR_PHY_TPC_12. */
711 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_M	0x3e000000
712 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S	25
713 
714 /* Bits for AR_PHY_TPC_18. */
715 #define AR_PHY_TPC_18_THERM_CAL_M	0x000000ff
716 #define AR_PHY_TPC_18_THERM_CAL_S	0
717 #define AR_PHY_TPC_18_VOLT_CAL_M	0x0000ff00
718 #define AR_PHY_TPC_18_VOLT_CAL_S	8
719 
720 /* Bits for AR_PHY_TPC_19. */
721 #define AR_PHY_TPC_19_ALPHA_THERM_M	0x000000ff
722 #define AR_PHY_TPC_19_ALPHA_THERM_S	0
723 #define AR_PHY_TPC_19_ALPHA_VOLT_M	0x001f0000
724 #define AR_PHY_TPC_19_ALPHA_VOLT_S	16
725 
726 /* Bits for AR_PHY_BB_THERM_ADC_1. */
727 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M	0x000000ff
728 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S	0
729 
730 /* Bits for AR_PHY_BB_THERM_ADC_4. */
731 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_M	0x000000ff
732 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_S	0
733 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_M	0x0000ff00
734 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_S	8
735 
736 /* Bits for AR_PHY_TX_FORCED_GAIN. */
737 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN	0x00000001
738 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_M	0x0000000e
739 #define AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN_S	1
740 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_M	0x00000030
741 #define AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN_S	4
742 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_M	0x000003c0
743 #define AR_PHY_TX_FORCED_GAIN_TXMXRGAIN_S	6
744 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_M	0x00003c00
745 #define AR_PHY_TX_FORCED_GAIN_PADRVGNA_S	10
746 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_M	0x0003c000
747 #define AR_PHY_TX_FORCED_GAIN_PADRVGNB_S	14
748 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_M	0x003c0000
749 #define AR_PHY_TX_FORCED_GAIN_PADRVGNC_S	18
750 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_M	0x00c00000
751 #define AR_PHY_TX_FORCED_GAIN_PADRVGND_S	22
752 #define AR_PHY_TX_FORCED_GAIN_ENABLE_PAL	0x01000000
753 
754 /* Bits for AR_PHY_TXGAIN_TABLE(i). */
755 #define AR_PHY_TXGAIN_TXBB1DBGAIN_M	0x00000007
756 #define AR_PHY_TXGAIN_TXBB1DBGAIN_S	0
757 #define AR_PHY_TXGAIN_TXBB6DBGAIN_M	0x00000018
758 #define AR_PHY_TXGAIN_TXBB6DBGAIN_S	3
759 #define AR_PHY_TXGAIN_TXMXRGAIN_M	0x000001e0
760 #define AR_PHY_TXGAIN_TXMXRGAIN_S	5
761 #define AR_PHY_TXGAIN_PADRVGNA_M	0x00001e00
762 #define AR_PHY_TXGAIN_PADRVGNA_S	9
763 #define AR_PHY_TXGAIN_PADRVGNB_M	0x0001e000
764 #define AR_PHY_TXGAIN_PADRVGNB_S	13
765 #define AR_PHY_TXGAIN_PADRVGNC_M	0x001e0000
766 #define AR_PHY_TXGAIN_PADRVGNC_S	17
767 #define AR_PHY_TXGAIN_PADRVGND_M	0x00600000
768 #define AR_PHY_TXGAIN_PADRVGND_S	21
769 #define AR_PHY_TXGAIN_INDEX_M		0xff000000
770 #define AR_PHY_TXGAIN_INDEX_S		24
771 
772 /* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
773 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M	0x01fc0000
774 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S	18
775 
776 /* Bits for AR_PHY_TX_IQCAL_START. */
777 #define AR_PHY_TX_IQCAL_START_DO_CAL	0x00000001
778 
779 /* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */
780 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M	0x00003fff
781 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S	0
782 
783 /* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */
784 #define AR_PHY_TX_IQCAL_STATUS_FAILED	0x00000001
785 
786 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL1. */
787 #define AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE		0x00000001
788 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_M	0x0000007e
789 #define AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING_S	1
790 #define AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE	0x00000100
791 #define AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE	0x00000200
792 #define AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE	0x00000400
793 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE		0x00000800
794 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_M		0x0003f000
795 #define AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP_S		12
796 
797 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL3. */
798 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_M	0x0000003f
799 #define AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE_S	0
800 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_M		0x00000fc0
801 #define AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP_S		6
802 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_M	0x0001f000
803 #define AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL_S	12
804 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_M	0x000e0000
805 #define AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES_S	17
806 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_M	0x00f00000
807 #define AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN_S	20
808 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_M	0x0f000000
809 #define AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN_S	24
810 #define AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE	0x20000000
811 
812 /* Bits for AR_PHY_PAPRD_TRAINER_CNTL4. */
813 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_M		0x00000fff
814 #define AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR_S		0
815 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_M	0x0000f000
816 #define AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA_S	12
817 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_M	0x03ff0000
818 #define AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES_S	16
819 
820 /* Bits for AR_PHY_PAPRD_TRAINER_STAT1. */
821 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_DONE		0x00000001
822 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_INCOMPLETE	0x00000002
823 #define AR_PHY_PAPRD_TRAINER_STAT1_CORR_ERR		0x00000004
824 #define AR_PHY_PAPRD_TRAINER_STAT1_TRAIN_ACTIVE		0x00000008
825 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_M	0x000001f0
826 #define AR_PHY_PAPRD_TRAINER_STAT1_RX_GAIN_IDX_S	4
827 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_M		0x0001fe00
828 #define AR_PHY_PAPRD_TRAINER_STAT1_AGC2_PWR_S		9
829 
830 /* Bits for AR_PHY_PAPRD_TRAINER_STAT2. */
831 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_M	0x0000ffff
832 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_VAL_S	0
833 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_M	0x001f0000
834 #define AR_PHY_PAPRD_TRAINER_STAT2_COARSE_IDX_S	16
835 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_M	0x00600000
836 #define AR_PHY_PAPRD_TRAINER_STAT2_FINE_IDX_S	21
837 
838 /* Bits for AR_PHY_PAPRD_TRAINER_STAT3. */
839 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_M	0x000fffff
840 #define AR_PHY_PAPRD_TRAINER_STAT3_TRAIN_SAMPLES_CNT_S	0
841 
842 /* Bits for AR_PHY_65NM_CH0_SYNTH4. */
843 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT	0x00000002
844 
845 /* Bits for AR_PHY_65NM_CH0_SYNTH7. */
846 #define AR9380_FRACMODE		0x40000000
847 #define AR9380_LOAD_SYNTH	0x80000000
848 
849 /* Bits for AR_PHY_65NM_CH0_BIAS1. */
850 #define AR_PHY_65NM_CH0_BIAS1_0_M	0x000001c0
851 #define AR_PHY_65NM_CH0_BIAS1_0_S	6
852 #define AR_PHY_65NM_CH0_BIAS1_1_M	0x00000e00
853 #define AR_PHY_65NM_CH0_BIAS1_1_S	9
854 #define AR_PHY_65NM_CH0_BIAS1_2_M	0x00007000
855 #define AR_PHY_65NM_CH0_BIAS1_2_S	12
856 #define AR_PHY_65NM_CH0_BIAS1_3_M	0x00038000
857 #define AR_PHY_65NM_CH0_BIAS1_3_S	15
858 #define AR_PHY_65NM_CH0_BIAS1_4_M	0x001c0000
859 #define AR_PHY_65NM_CH0_BIAS1_4_S	18
860 #define AR_PHY_65NM_CH0_BIAS1_5_M	0x00e00000
861 #define AR_PHY_65NM_CH0_BIAS1_5_S	21
862 
863 /* Bits for AR_PHY_65NM_CH0_BIAS2. */
864 #define AR_PHY_65NM_CH0_BIAS2_0_M	0x000000e0
865 #define AR_PHY_65NM_CH0_BIAS2_0_S	5
866 #define AR_PHY_65NM_CH0_BIAS2_1_M	0x00000700
867 #define AR_PHY_65NM_CH0_BIAS2_1_S	8
868 #define AR_PHY_65NM_CH0_BIAS2_2_M	0x00003800
869 #define AR_PHY_65NM_CH0_BIAS2_2_S	11
870 #define AR_PHY_65NM_CH0_BIAS2_3_M	0x0001c000
871 #define AR_PHY_65NM_CH0_BIAS2_3_S	14
872 #define AR_PHY_65NM_CH0_BIAS2_4_M	0x000e0000
873 #define AR_PHY_65NM_CH0_BIAS2_4_S	17
874 #define AR_PHY_65NM_CH0_BIAS2_5_M	0x00700000
875 #define AR_PHY_65NM_CH0_BIAS2_5_S	20
876 #define AR_PHY_65NM_CH0_BIAS2_6_M	0x03800000
877 #define AR_PHY_65NM_CH0_BIAS2_6_S	23
878 #define AR_PHY_65NM_CH0_BIAS2_7_M	0x1c000000
879 #define AR_PHY_65NM_CH0_BIAS2_7_S	26
880 #define AR_PHY_65NM_CH0_BIAS2_8_M	0xe0000000
881 #define AR_PHY_65NM_CH0_BIAS2_8_S	29
882 
883 /* Bits for AR_PHY_65NM_CH0_BIAS4. */
884 #define AR_PHY_65NM_CH0_BIAS4_0_M	0x03800000
885 #define AR_PHY_65NM_CH0_BIAS4_0_S	23
886 #define AR_PHY_65NM_CH0_BIAS4_1_M	0x1c000000
887 #define AR_PHY_65NM_CH0_BIAS4_1_S	26
888 #define AR_PHY_65NM_CH0_BIAS4_2_M	0xe0000000
889 #define AR_PHY_65NM_CH0_BIAS4_2_S	29
890 
891 /* Bits for AR_PHY_65NM_CH0_RXTX4. */
892 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON  0x10000000
893 
894 /* Bits for AR9485_PHY_65NM_CH0_TOP2. */
895 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_M	0x0000f000
896 #define AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL_S	12
897 
898 /* Bits for AR_PHY_65NM_CH0_TOP. */
899 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M	0x00000300
900 #define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S	8
901 
902 /* Bits for AR_PHY_65NM_CH0_THERM. */
903 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_M	0x00000003
904 #define AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB_S	0
905 #define AR_PHY_65NM_CH0_THERM_XPASHORT2GND	0x00000004
906 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M	0x0000ff00
907 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S	8
908 #define AR_PHY_65NM_CH0_THERM_START		0x20000000
909 #define AR_PHY_65NM_CH0_THERM_LOCAL		0x80000000
910 
911 /* Bits for AR9485_PHY_CH0_XTAL. */
912 #define AR9485_PHY_CH0_XTAL_CAPINDAC_M	0x7f000000
913 #define AR9485_PHY_CH0_XTAL_CAPINDAC_S	24
914 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_M	0x00fe0000
915 #define AR9485_PHY_CH0_XTAL_CAPOUTDAC_S	17
916 
917 /* Bits for AR_PHY_PMU1. */
918 #define AR_PHY_PMU1_PWD	0x00000001
919 
920 /* Bits for AR_PHY_PMU2. */
921 #define AR_PHY_PMU2_PGM	0x00200000
922 
923 /*
924  * OTP registers.
925  */
926 #define AR_OTP_BASE(i)			(0x14000 + (i) * 4)
927 #define AR_OTP_STATUS			0x15f18
928 #define AR_OTP_READ_DATA		0x15f1c
929 
930 /* Bits for AR_OTP_STATUS. */
931 #define AR_OTP_STATUS_TYPE_M		0x00000007
932 #define AR_OTP_STATUS_TYPE_S		0
933 #define AR_OTP_STATUS_SM_BUSY		0x1
934 #define AR_OTP_STATUS_ACCESS_BUSY	0x2
935 #define AR_OTP_STATUS_VALID		0x4
936 
937 
938 #define AR9003_MAX_CHAINS	3
939 
940 #define AR9003_TX_QDEPTH	8
941 #define AR9003_RX_LP_QDEPTH	128
942 #define AR9003_RX_HP_QDEPTH	16
943 
944 #define AR9003_NTXSTATUS	64
945 
946 /* Maximum number of DMA segments per Tx descriptor. */
947 #define AR9003_MAX_SCATTER	4
948 
949 /*
950  * Tx DMA descriptor.
951  */
952 struct ar_tx_desc {
953 	uint32_t	ds_info;
954 	uint32_t	ds_link;
955 	struct {
956 		uint32_t	ds_data;
957 		uint32_t	ds_ctl;
958 	} __packed	ds_segs[AR9003_MAX_SCATTER];
959 	uint32_t	ds_ctl10;
960 	uint32_t	ds_ctl11;
961 	uint32_t	ds_ctl12;
962 	uint32_t	ds_ctl13;
963 	uint32_t	ds_ctl14;
964 	uint32_t	ds_ctl15;
965 	uint32_t	ds_ctl16;
966 	uint32_t	ds_ctl17;
967 	uint32_t	ds_ctl18;
968 	uint32_t	ds_ctl19;
969 	uint32_t	ds_ctl20;
970 	uint32_t	ds_ctl21;
971 	uint32_t	ds_ctl22;
972 	/*
973 	 * Padding to make Tx descriptors 128 bytes such that they will
974 	 * not cross a 4KB boundary.
975 	 */
976 	uint32_t	pad[9];
977 } __packed  __attribute__((aligned(4)));
978 
979 /* Bits for ds_info. */
980 #define AR_TXI_DESC_NDWORDS_M		0x000000ff
981 #define AR_TXI_DESC_NDWORDS_S		0
982 #define AR_TXI_QCU_NUM_M		0x00000f00
983 #define AR_TXI_QCU_NUM_S		8
984 #define AR_TXI_CTRL_STAT		0x00004000
985 #define AR_TXI_DESC_TX			0x00008000
986 #define AR_TXI_DESC_ID_M		0xffff0000
987 #define AR_TXI_DESC_ID_S		16
988 #define AR_VENDOR_ATHEROS		0x168c	/* NB: PCI_VENDOR_ATHEROS */
989 
990 /* Bits for ds_ctl. */
991 #define AR_TXC_BUF_LEN_M		0x0fff0000
992 #define AR_TXC_BUF_LEN_S		16
993 
994 /* Bits for ds_ctl10. */
995 #define AR_TXC10_PTR_CHK_SUM_M		0x0000ffff
996 #define AR_TXC10_PTR_CHK_SUM_S		0
997 
998 /* Bits for ds_ctl11. */
999 #define AR_TXC11_FRAME_LEN_M		0x00000fff
1000 #define AR_TXC11_FRAME_LEN_S		0
1001 #define AR_TXC11_XMIT_POWER_M		0x003f0000
1002 #define AR_TXC11_XMIT_POWER_S		16
1003 #define AR_TXC11_RTS_ENABLE		0x00400000
1004 #define AR_TXC11_CLR_DEST_MASK		0x01000000
1005 #define AR_TXC11_DEST_IDX_VALID		0x40000000
1006 #define AR_TXC11_CTS_ENABLE		0x80000000
1007 
1008 /* Bits for ds_ctl12. */
1009 #define AR_TXC12_PAPRD_CHAIN_MASK_M	0x00000e00
1010 #define AR_TXC12_PAPRD_CHAIN_MASK_S	9
1011 #define AR_TXC12_DEST_IDX_M		0x000fe000
1012 #define AR_TXC12_DEST_IDX_S		13
1013 #define AR_TXC12_FRAME_TYPE_M		0x00f00000
1014 #define AR_TXC12_FRAME_TYPE_S		20
1015 #define AR_FRAME_TYPE_NORMAL		0
1016 #define AR_FRAME_TYPE_ATIM		1
1017 #define AR_FRAME_TYPE_PSPOLL		2
1018 #define AR_FRAME_TYPE_BEACON		3
1019 #define AR_FRAME_TYPE_PROBE_RESP	4
1020 #define AR_TXC12_NO_ACK			0x01000000
1021 
1022 /* Bits for ds_ctl13. */
1023 #define AR_TXC13_BURST_DUR_M		0x00007fff
1024 #define AR_TXC13_BURST_DUR_S		0
1025 #define AR_TXC13_DUR_UPDATE_ENA		0x00008000
1026 #define AR_TXC13_XMIT_DATA_TRIES0_M	0x000f0000
1027 #define AR_TXC13_XMIT_DATA_TRIES0_S	16
1028 #define AR_TXC13_XMIT_DATA_TRIES1_M	0x00f00000
1029 #define AR_TXC13_XMIT_DATA_TRIES1_S	20
1030 #define AR_TXC13_XMIT_DATA_TRIES2_M	0x0f000000
1031 #define AR_TXC13_XMIT_DATA_TRIES2_S	24
1032 #define AR_TXC13_XMIT_DATA_TRIES3_M	0xf0000000
1033 #define AR_TXC13_XMIT_DATA_TRIES3_S	28
1034 
1035 /* Bits for ds_ctl14. */
1036 #define AR_TXC14_XMIT_RATE0_M		0x000000ff
1037 #define AR_TXC14_XMIT_RATE0_S		0
1038 #define AR_TXC14_XMIT_RATE1_M		0x0000ff00
1039 #define AR_TXC14_XMIT_RATE1_S		8
1040 #define AR_TXC14_XMIT_RATE2_M		0x00ff0000
1041 #define AR_TXC14_XMIT_RATE2_S		16
1042 #define AR_TXC14_XMIT_RATE3_M		0xff000000
1043 #define AR_TXC14_XMIT_RATE3_S		24
1044 
1045 /* Bits for ds_ctl15. */
1046 #define AR_TXC15_PACKET_DUR0_M		0x00007fff
1047 #define AR_TXC15_PACKET_DUR0_S		0
1048 #define AR_TXC15_RTSCTS_QUAL0		0x00008000
1049 #define AR_TXC15_PACKET_DUR1_M		0x7fff0000
1050 #define AR_TXC15_PACKET_DUR1_S		16
1051 #define AR_TXC15_RTSCTS_QUAL1		0x80000000
1052 /* Shortcut. */
1053 #define AR_TXC15_RTSCTS_QUAL01	\
1054 	(AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1)
1055 
1056 /* Bits for ds_ctl16. */
1057 #define AR_TXC16_PACKET_DUR2_M		0x00007fff
1058 #define AR_TXC16_PACKET_DUR2_S		0
1059 #define AR_TXC16_RTSCTS_QUAL2		0x00008000
1060 #define AR_TXC16_PACKET_DUR3_M		0x7fff0000
1061 #define AR_TXC16_PACKET_DUR3_S		16
1062 #define AR_TXC16_RTSCTS_QUAL3		0x80000000
1063 /* Shortcut. */
1064 #define AR_TXC16_RTSCTS_QUAL23	\
1065 	(AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3)
1066 
1067 /* Bits for ds_ctl17. */
1068 #define AR_TXC17_ENCR_TYPE_M		0x0c000000
1069 #define AR_TXC17_ENCR_TYPE_S		26
1070 #define AR_ENCR_TYPE_CLEAR		0
1071 #define AR_ENCR_TYPE_WEP		1
1072 #define AR_ENCR_TYPE_AES		2
1073 #define AR_ENCR_TYPE_TKIP		3
1074 
1075 /* Bits for ds_ctl18. */
1076 #define AR_TXC18_2040_0			0x00000001
1077 #define AR_TXC18_GI0			0x00000002
1078 #define AR_TXC18_CHAIN_SEL0_M		0x0000001c
1079 #define AR_TXC18_CHAIN_SEL0_S		2
1080 #define AR_TXC18_2040_1			0x00000020
1081 #define AR_TXC18_GI1			0x00000040
1082 #define AR_TXC18_CHAIN_SEL1_M		0x00000380
1083 #define AR_TXC18_CHAIN_SEL1_S		7
1084 #define AR_TXC18_2040_2			0x00000400
1085 #define AR_TXC18_GI2			0x00000800
1086 #define AR_TXC18_CHAIN_SEL2_M		0x00007000
1087 #define AR_TXC18_CHAIN_SEL2_S		12
1088 #define AR_TXC18_2040_3			0x00008000
1089 #define AR_TXC18_GI3			0x00010000
1090 #define AR_TXC18_CHAIN_SEL3_M		0x000e0000
1091 #define AR_TXC18_CHAIN_SEL3_S		17
1092 #define AR_TXC18_RTSCTS_RATE_M		0x0ff00000
1093 #define AR_TXC18_RTSCTS_RATE_S		20
1094 /* Shortcuts. */
1095 #define AR_TXC18_2040_0123	\
1096 	(AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3)
1097 #define AR_TXC18_GI0123		\
1098 	(AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3)
1099 
1100 /* Bits for ds_ctl19. */
1101 #define AR_TXC19_NOT_SOUNDING		0x20000000
1102 
1103 /*
1104  * Tx status DMA descriptor.
1105  */
1106 struct ar_tx_status {
1107 	uint32_t	ds_info;
1108 	uint32_t	ds_status1;
1109 	uint32_t	ds_status2;
1110 	uint32_t	ds_status3;
1111 	uint32_t	ds_status4;
1112 	uint32_t	ds_status5;
1113 	uint32_t	ds_status6;
1114 	uint32_t	ds_status7;
1115 	uint32_t	ds_status8;
1116 } __packed  __attribute__((aligned(4)));
1117 
1118 /* Bits for ds_status3. */
1119 #define AR_TXS3_EXCESSIVE_RETRIES	0x00000002
1120 #define AR_TXS3_FIFO_UNDERRUN		0x00000004
1121 #define AR_TXS3_RTS_FAIL_CNT_M		0x000000f0
1122 #define AR_TXS3_RTS_FAIL_CNT_S		4
1123 #define AR_TXS3_DATA_FAIL_CNT_M		0x00000f00
1124 #define AR_TXS3_DATA_FAIL_CNT_S		8
1125 #define AR_TXS3_TX_DELIM_UNDERRUN	0x00010000
1126 #define AR_TXS3_TX_DATA_UNDERRUN	0x00020000
1127 /* Shortcut. */
1128 #define AR_TXS3_UNDERRUN		\
1129 	(AR_TXS3_FIFO_UNDERRUN |	\
1130 	 AR_TXS3_TX_DELIM_UNDERRUN |	\
1131 	 AR_TXS3_TX_DATA_UNDERRUN)
1132 
1133 /* Bits for ds_status8. */
1134 #define AR_TXS8_DONE			0x00000001
1135 #define AR_TXS8_FINAL_IDX_M		0x00600000
1136 #define AR_TXS8_FINAL_IDX_S		21
1137 
1138 /*
1139  * Rx status DMA descriptor.
1140  */
1141 struct ar_rx_status {
1142 	uint32_t	ds_info;
1143 	uint32_t	ds_status1;
1144 	uint32_t	ds_status2;
1145 	uint32_t	ds_status3;
1146 	uint32_t	ds_status4;
1147 	uint32_t	ds_status5;
1148 	uint32_t	ds_status6;
1149 	uint32_t	ds_status7;
1150 	uint32_t	ds_status8;
1151 	uint32_t	ds_status9;
1152 	uint32_t	ds_status10;
1153 	uint32_t	ds_status11;
1154 } __packed  __attribute__((aligned(4)));
1155 
1156 /* Bits for ds_info. */
1157 #define AR_RXI_CTRL_STAT		0x00004000
1158 #define AR_RXI_DESC_TX			0x00008000
1159 #define AR_RXI_DESC_ID_M		0xffff0000
1160 #define AR_RXI_DESC_ID_S		16
1161 
1162 /* Bits for ds_status1. */
1163 #define AR_RXS1_DONE			0x00000001
1164 #define AR_RXS1_RATE_M			0x000003fc
1165 #define AR_RXS1_RATE_S			2
1166 
1167 /* Bits for ds_status2. */
1168 #define AR_RXS2_DATA_LEN_M		0x00000fff
1169 #define AR_RXS2_DATA_LEN_S		0
1170 
1171 /* Bits for ds_status4. */
1172 #define AR_RXS4_GI			0x00000001
1173 #define AR_RXS4_ANTENNA_M		0xffffff00
1174 #define AR_RXS4_ANTENNA_S		8
1175 
1176 /* Bits for ds_status5. */
1177 #define AR_RXS5_RSSI_COMBINED_M		0xff000000
1178 #define AR_RXS5_RSSI_COMBINED_S		24
1179 
1180 /* Bits for ds_status11. */
1181 #define AR_RXS11_FRAME_OK		0x00000002
1182 #define AR_RXS11_CRC_ERR		0x00000004
1183 #define AR_RXS11_DECRYPT_CRC_ERR	0x00000008
1184 #define AR_RXS11_PHY_ERR		0x00000010
1185 #define AR_RXS11_PHY_ERR_CODE_M		0x0000ff00
1186 #define AR_RXS11_PHY_ERR_CODE_S		8
1187 #define AR_RXS11_MICHAEL_ERR		0x00000020
1188 
1189 /*
1190  * AR9003 family common ROM structures.
1191  */
1192 #define AR_EEP_COMPRESS_NONE	0
1193 #define AR_EEP_COMPRESS_LZMA	1
1194 #define AR_EEP_COMPRESS_PAIRS	2
1195 #define AR_EEP_COMPRESS_BLOCK	3
1196 
1197 struct ar_cal_target_power_leg {
1198 	uint8_t	tPow2x[4];
1199 } __packed;
1200 
1201 struct ar_cal_target_power_ht {
1202 	uint8_t	tPow2x[14];
1203 } __packed;
1204 
1205 #endif /* _ARN9003REG_H_ */
1206