xref: /freebsd/sys/dev/ath/ath_hal/ar5416/ar5416desc.h (revision 95ee2897)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 #ifndef _ATH_AR5416_DESC_H_
20 #define _ATH_AR5416_DESC_H_
21 
22 /*
23  * Hardware-specific descriptor structures.
24  */
25 
26 /* XXX Need to replace this with a dynamic
27  * method of determining Owl2 if possible
28  */
29 #define _get_index(_ah) ( IS_5416V1(_ah)  ? -4 : 0 )
30 #define AR5416_DS_TXSTATUS(_ah, _ads) \
31 	((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
32 #define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \
33 	((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)]))
34 
35 #define AR5416_NUM_TX_STATUS	10 /* Number of TX status words */
36 /* Clear the whole descriptor */
37 #define AR5416_DESC_TX_CTL_SZ	sizeof(struct ar5416_tx_desc)
38 
39 struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */
40 	uint32_t	ctl2;
41 	uint32_t	ctl3;
42 	uint32_t	ctl4;
43 	uint32_t	ctl5;
44 	uint32_t	ctl6;
45 	uint32_t	ctl7;
46 	uint32_t	ctl8;
47 	uint32_t	ctl9;
48 	uint32_t	ctl10;
49 	uint32_t	ctl11;
50 	uint32_t	status[AR5416_NUM_TX_STATUS];
51 };
52 
53 struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */
54 	uint32_t	status0;
55 	uint32_t	status1;
56 	uint32_t	status2;
57 	uint32_t	status3;
58 	uint32_t	status4;
59 	uint32_t	status5;
60 	uint32_t	status6;
61  	uint32_t	status7;
62 	uint32_t	status8;
63 };
64 
65 struct ar5416_desc {
66 	uint32_t   ds_link;    /* link pointer */
67 	uint32_t   ds_data;    /* data buffer pointer */
68 	uint32_t   ds_ctl0;    /* DMA control 0 */
69 	uint32_t   ds_ctl1;    /* DMA control 1 */
70 	union {
71 		struct ar5416_tx_desc tx;
72 		struct ar5416_rx_desc rx;
73 	} u;
74 } __packed;
75 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
76 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
77 
78 #define ds_ctl2     u.tx.ctl2
79 #define ds_ctl3     u.tx.ctl3
80 #define ds_ctl4     u.tx.ctl4
81 #define ds_ctl5     u.tx.ctl5
82 #define ds_ctl6     u.tx.ctl6
83 #define ds_ctl7     u.tx.ctl7
84 #define ds_ctl8     u.tx.ctl8
85 #define ds_ctl9     u.tx.ctl9
86 #define ds_ctl10    u.tx.ctl10
87 #define ds_ctl11    u.tx.ctl11
88 
89 #define ds_rxstatus0    u.rx.status0
90 #define ds_rxstatus1    u.rx.status1
91 #define ds_rxstatus2    u.rx.status2
92 #define ds_rxstatus3    u.rx.status3
93 #define ds_rxstatus4    u.rx.status4
94 #define ds_rxstatus5    u.rx.status5
95 #define ds_rxstatus6    u.rx.status6
96 #define ds_rxstatus7    u.rx.status7
97 #define ds_rxstatus8    u.rx.status8
98 
99 /***********
100  * TX Desc *
101  ***********/
102 
103 /* ds_ctl0 */
104 #define AR_FrameLen         0x00000fff
105 #define AR_VirtMoreFrag     0x00001000
106 #define AR_TxCtlRsvd00      0x0000e000
107 #define AR_XmitPower        0x003f0000
108 #define AR_XmitPower_S      16
109 #define AR_RTSEnable        0x00400000
110 #define AR_VEOL             0x00800000
111 #define AR_ClrDestMask      0x01000000
112 #define AR_TxCtlRsvd01      0x1e000000
113 #define AR_TxIntrReq        0x20000000
114 #define AR_DestIdxValid     0x40000000
115 #define AR_CTSEnable        0x80000000
116 
117 /* ds_ctl1 */
118 #define AR_BufLen           0x00000fff
119 #define AR_TxMore           0x00001000
120 #define AR_DestIdx          0x000fe000
121 #define AR_DestIdx_S        13
122 #define AR_FrameType        0x00f00000
123 #define AR_FrameType_S      20
124 #define AR_NoAck            0x01000000
125 #define AR_InsertTS         0x02000000
126 #define AR_CorruptFCS       0x04000000
127 #define AR_ExtOnly          0x08000000
128 #define AR_ExtAndCtl        0x10000000
129 #define AR_MoreAggr         0x20000000
130 #define AR_IsAggr           0x40000000
131 #define AR_MoreRifs	    0x80000000
132 
133 /* ds_ctl2 */
134 #define AR_BurstDur         0x00007fff
135 #define AR_BurstDur_S       0
136 #define AR_DurUpdateEn      0x00008000
137 #define AR_XmitDataTries0   0x000f0000
138 #define AR_XmitDataTries0_S 16
139 #define AR_XmitDataTries1   0x00f00000
140 #define AR_XmitDataTries1_S 20
141 #define AR_XmitDataTries2   0x0f000000
142 #define AR_XmitDataTries2_S 24
143 #define AR_XmitDataTries3   0xf0000000
144 #define AR_XmitDataTries3_S 28
145 
146 /* ds_ctl3 */
147 #define AR_XmitRate0        0x000000ff
148 #define AR_XmitRate0_S      0
149 #define AR_XmitRate1        0x0000ff00
150 #define AR_XmitRate1_S      8
151 #define AR_XmitRate2        0x00ff0000
152 #define AR_XmitRate2_S      16
153 #define AR_XmitRate3        0xff000000
154 #define AR_XmitRate3_S      24
155 
156 /* ds_ctl4 */
157 #define AR_PacketDur0       0x00007fff
158 #define AR_PacketDur0_S     0
159 #define AR_RTSCTSQual0      0x00008000
160 #define AR_PacketDur1       0x7fff0000
161 #define AR_PacketDur1_S     16
162 #define AR_RTSCTSQual1      0x80000000
163 
164 /* ds_ctl5 */
165 #define AR_PacketDur2       0x00007fff
166 #define AR_PacketDur2_S     0
167 #define AR_RTSCTSQual2      0x00008000
168 #define AR_PacketDur3       0x7fff0000
169 #define AR_PacketDur3_S     16
170 #define AR_RTSCTSQual3      0x80000000
171 
172 /* ds_ctl6 */
173 #define AR_AggrLen          0x0000ffff
174 #define AR_AggrLen_S        0
175 #define AR_TxCtlRsvd60      0x00030000
176 #define AR_PadDelim         0x03fc0000
177 #define AR_PadDelim_S       18
178 #define AR_EncrType         0x0c000000
179 #define AR_EncrType_S       26
180 #define AR_TxCtlRsvd61      0xf0000000
181 
182 /* ds_ctl7 */
183 #define AR_2040_0           0x00000001
184 #define AR_GI0              0x00000002
185 #define AR_ChainSel0        0x0000001c
186 #define AR_ChainSel0_S      2
187 #define AR_2040_1           0x00000020
188 #define AR_GI1              0x00000040
189 #define AR_ChainSel1        0x00000380
190 #define AR_ChainSel1_S      7
191 #define AR_2040_2           0x00000400
192 #define AR_GI2              0x00000800
193 #define AR_ChainSel2        0x00007000
194 #define AR_ChainSel2_S      12
195 #define AR_2040_3           0x00008000
196 #define AR_GI3              0x00010000
197 #define AR_ChainSel3        0x000e0000
198 #define AR_ChainSel3_S      17
199 #define AR_RTSCTSRate       0x0ff00000
200 #define AR_RTSCTSRate_S     20
201 #define	AR_STBC0	    0x10000000
202 #define	AR_STBC1	    0x20000000
203 #define	AR_STBC2	    0x40000000
204 #define	AR_STBC3	    0x80000000
205 
206 /* ds_ctl8 */
207 #define	AR_AntCtl0	    0x00ffffff
208 #define	AR_AntCtl0_S	    0
209 /* Xmit 0 TPC is AR_XmitPower in ctl0 */
210 
211 /* ds_ctl9 */
212 #define	AR_AntCtl1	    0x00ffffff
213 #define	AR_AntCtl1_S	    0
214 #define	AR_XmitPower1	    0xff000000
215 #define	AR_XmitPower1_S	    24
216 
217 /* ds_ctl10 */
218 #define	AR_AntCtl2	    0x00ffffff
219 #define	AR_AntCtl2_S	    0
220 #define	AR_XmitPower2	    0xff000000
221 #define	AR_XmitPower2_S	    24
222 
223 /* ds_ctl11 */
224 #define	AR_AntCtl3	    0x00ffffff
225 #define	AR_AntCtl3_S	    0
226 #define	AR_XmitPower3	    0xff000000
227 #define	AR_XmitPower3_S	    24
228 
229 /*************
230  * TX Status *
231  *************/
232 
233 /* ds_status0 */
234 #define AR_TxRSSIAnt00      0x000000ff
235 #define AR_TxRSSIAnt00_S    0
236 #define AR_TxRSSIAnt01      0x0000ff00
237 #define AR_TxRSSIAnt01_S    8
238 #define AR_TxRSSIAnt02      0x00ff0000
239 #define AR_TxRSSIAnt02_S    16
240 #define AR_TxStatusRsvd00   0x3f000000
241 #define AR_TxBaStatus       0x40000000
242 #define AR_TxStatusRsvd01   0x80000000
243 
244 /* ds_status1 */
245 #define AR_FrmXmitOK            0x00000001
246 #define AR_ExcessiveRetries     0x00000002
247 #define AR_FIFOUnderrun         0x00000004
248 #define AR_Filtered             0x00000008
249 #define AR_RTSFailCnt           0x000000f0
250 #define AR_RTSFailCnt_S         4
251 #define AR_DataFailCnt          0x00000f00
252 #define AR_DataFailCnt_S        8
253 #define AR_VirtRetryCnt         0x0000f000
254 #define AR_VirtRetryCnt_S       12
255 #define AR_TxDelimUnderrun      0x00010000
256 #define AR_TxDelimUnderrun_S    13
257 #define AR_TxDataUnderrun       0x00020000
258 #define AR_TxDataUnderrun_S     14
259 #define AR_DescCfgErr           0x00040000
260 #define AR_DescCfgErr_S         15
261 #define	AR_TxTimerExpired	0x00080000
262 #define AR_TxStatusRsvd10       0xfff00000
263 
264 /* ds_status2 */
265 #define AR_SendTimestamp(_ptr)   (_ptr)[2]
266 
267 /* ds_status3 */
268 #define AR_BaBitmapLow(_ptr)     (_ptr)[3]
269 
270 /* ds_status4 */
271 #define AR_BaBitmapHigh(_ptr)    (_ptr)[4]
272 
273 /* ds_status5 */
274 #define AR_TxRSSIAnt10      0x000000ff
275 #define AR_TxRSSIAnt10_S    0
276 #define AR_TxRSSIAnt11      0x0000ff00
277 #define AR_TxRSSIAnt11_S    8
278 #define AR_TxRSSIAnt12      0x00ff0000
279 #define AR_TxRSSIAnt12_S    16
280 #define AR_TxRSSICombined   0xff000000
281 #define AR_TxRSSICombined_S 24
282 
283 /* ds_status6 */
284 #define AR_TxEVM0(_ptr)     (_ptr)[6]
285 
286 /* ds_status7 */
287 #define AR_TxEVM1(_ptr)    (_ptr)[7]
288 
289 /* ds_status8 */
290 #define AR_TxEVM2(_ptr)   (_ptr)[8]
291 
292 /* ds_status9 */
293 #define AR_TxDone           0x00000001
294 #define AR_SeqNum           0x00001ffe
295 #define AR_SeqNum_S         1
296 #define AR_TxStatusRsvd80   0x0001e000
297 #define AR_TxOpExceeded     0x00020000
298 #define AR_TxStatusRsvd81   0x001c0000
299 #define AR_FinalTxIdx       0x00600000
300 #define AR_FinalTxIdx_S     21
301 #define AR_TxStatusRsvd82   0x01800000
302 #define AR_PowerMgmt        0x02000000
303 #define AR_TxTid            0xf0000000
304 #define AR_TxTid_S          28
305 #define AR_TxStatusRsvd83   0xfc000000
306 
307 /***********
308  * RX Desc *
309  ***********/
310 
311 /* ds_ctl0 */
312 #define AR_RxCTLRsvd00  0xffffffff
313 
314 /* ds_ctl1 */
315 #define AR_BufLen       0x00000fff
316 #define AR_RxCtlRsvd00  0x00001000
317 #define AR_RxIntrReq    0x00002000
318 #define AR_RxCtlRsvd01  0xffffc000
319 
320 /*************
321  * Rx Status *
322  *************/
323 
324 /* ds_status0 */
325 #define AR_RxRSSIAnt00      0x000000ff
326 #define AR_RxRSSIAnt00_S    0
327 #define AR_RxRSSIAnt01      0x0000ff00
328 #define AR_RxRSSIAnt01_S    8
329 #define AR_RxRSSIAnt02      0x00ff0000
330 #define AR_RxRSSIAnt02_S    16
331 /* Rev specific */
332 /* Owl 1.x only */
333 #define AR_RxStatusRsvd00   0xff000000
334 /* Owl 2.x only */
335 #define AR_RxRate           0xff000000
336 #define AR_RxRate_S         24
337 
338 /* ds_status1 */
339 #define AR_DataLen          0x00000fff
340 #define AR_RxMore           0x00001000
341 #define AR_NumDelim         0x003fc000
342 #define AR_NumDelim_S       14
343 #define AR_RxStatusRsvd10   0xff800000
344 
345 /* ds_status2 */
346 #define AR_RcvTimestamp     ds_rxstatus2
347 
348 /* ds_status3 */
349 #define AR_GI               0x00000001
350 #define AR_2040             0x00000002
351 /* Rev specific */
352 /* Owl 1.x only */
353 #define AR_RxRateV1         0x000003fc
354 #define AR_RxRateV1_S       2
355 #define AR_Parallel40       0x00000400
356 #define AR_RxStatusRsvd30   0xfffff800
357 /* Owl 2.x only */
358 #define AR_DupFrame	    0x00000004
359 #define AR_STBCFrame        0x00000008
360 #define AR_RxAntenna        0xffffff00
361 #define AR_RxAntenna_S      8
362 
363 /* ds_status4 */
364 #define AR_RxRSSIAnt10            0x000000ff
365 #define AR_RxRSSIAnt10_S          0
366 #define AR_RxRSSIAnt11            0x0000ff00
367 #define AR_RxRSSIAnt11_S          8
368 #define AR_RxRSSIAnt12            0x00ff0000
369 #define AR_RxRSSIAnt12_S          16
370 #define AR_RxRSSICombined         0xff000000
371 #define AR_RxRSSICombined_S       24
372 
373 /* ds_status5 */
374 #define AR_RxEVM0           ds_rxstatus5
375 
376 /* ds_status6 */
377 #define AR_RxEVM1           ds_rxstatus6
378 
379 /* ds_status7 */
380 #define AR_RxEVM2           ds_rxstatus7
381 
382 /* ds_status8 */
383 #define AR_RxDone           0x00000001
384 #define AR_RxFrameOK        0x00000002
385 #define AR_CRCErr           0x00000004
386 #define AR_DecryptCRCErr    0x00000008
387 #define AR_PHYErr           0x00000010
388 #define AR_MichaelErr       0x00000020
389 #define AR_PreDelimCRCErr   0x00000040
390 #define AR_RxStatusRsvd70   0x00000080
391 #define AR_RxKeyIdxValid    0x00000100
392 #define AR_KeyIdx           0x0000fe00
393 #define AR_KeyIdx_S         9
394 #define AR_PHYErrCode       0x0000ff00
395 #define AR_PHYErrCode_S     8
396 #define AR_RxMoreAggr       0x00010000
397 #define AR_RxAggr           0x00020000
398 #define AR_PostDelimCRCErr  0x00040000
399 #define AR_RxStatusRsvd71   0x2ff80000
400 #define	AR_HiRxChain	    0x10000000
401 #define AR_DecryptBusyErr   0x40000000
402 #define AR_KeyMiss          0x80000000
403 
404 #define TXCTL_OFFSET(ah)	2
405 #define TXCTL_NUMWORDS(ah)	(AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8)
406 #define TXSTATUS_OFFSET(ah)	(AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10)
407 #define TXSTATUS_NUMWORDS(ah)	10
408 
409 #define RXCTL_OFFSET(ah)	3
410 #define RXCTL_NUMWORDS(ah)	1
411 #define RXSTATUS_OFFSET(ah)	4
412 #define RXSTATUS_NUMWORDS(ah)	9
413 #define RXSTATUS_RATE(ah, ads) \
414 	(AR_SREV_5416_V20_OR_LATER(ah) ? \
415 	 MS((ads)->ds_rxstatus0, AR_RxRate) : \
416 	 ((ads)->ds_rxstatus3 >> 2) & 0xFF)
417 #define RXSTATUS_DUPLICATE(ah, ads) \
418 	(AR_SREV_5416_V20_OR_LATER(ah) ?	\
419 	 MS((ads)->ds_rxstatus3, AR_Parallel40) : \
420 	 ((ads)->ds_rxstatus3 >> 10) & 0x1)
421 #endif /* _ATH_AR5416_DESC_H_ */
422