1 /* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
2 #ifndef DT_BINDINGS_AST2600_CLOCK_H
3 #define DT_BINDINGS_AST2600_CLOCK_H
4 
5 #define ASPEED_CLK_GATE_ECLK		0
6 #define ASPEED_CLK_GATE_GCLK		1
7 
8 #define ASPEED_CLK_GATE_MCLK		2
9 
10 #define ASPEED_CLK_GATE_VCLK		3
11 #define ASPEED_CLK_GATE_BCLK		4
12 #define ASPEED_CLK_GATE_DCLK		5
13 
14 #define ASPEED_CLK_GATE_LCLK		6
15 #define ASPEED_CLK_GATE_LHCCLK		7
16 
17 #define ASPEED_CLK_GATE_D1CLK		8
18 #define ASPEED_CLK_GATE_YCLK		9
19 
20 #define ASPEED_CLK_GATE_REF0CLK		10
21 #define ASPEED_CLK_GATE_REF1CLK		11
22 
23 #define ASPEED_CLK_GATE_ESPICLK		12
24 
25 #define ASPEED_CLK_GATE_USBUHCICLK	13
26 #define ASPEED_CLK_GATE_USBPORT1CLK	14
27 #define ASPEED_CLK_GATE_USBPORT2CLK	15
28 
29 #define ASPEED_CLK_GATE_RSACLK		16
30 #define ASPEED_CLK_GATE_RVASCLK		17
31 
32 #define ASPEED_CLK_GATE_MAC1CLK		18
33 #define ASPEED_CLK_GATE_MAC2CLK		19
34 #define ASPEED_CLK_GATE_MAC3CLK		20
35 #define ASPEED_CLK_GATE_MAC4CLK		21
36 
37 #define ASPEED_CLK_GATE_UART1CLK	22
38 #define ASPEED_CLK_GATE_UART2CLK	23
39 #define ASPEED_CLK_GATE_UART3CLK	24
40 #define ASPEED_CLK_GATE_UART4CLK	25
41 #define ASPEED_CLK_GATE_UART5CLK	26
42 #define ASPEED_CLK_GATE_UART6CLK	27
43 #define ASPEED_CLK_GATE_UART7CLK	28
44 #define ASPEED_CLK_GATE_UART8CLK	29
45 #define ASPEED_CLK_GATE_UART9CLK	30
46 #define ASPEED_CLK_GATE_UART10CLK	31
47 #define ASPEED_CLK_GATE_UART11CLK	32
48 #define ASPEED_CLK_GATE_UART12CLK	33
49 #define ASPEED_CLK_GATE_UART13CLK	34
50 
51 #define ASPEED_CLK_GATE_SDCLK		35
52 #define ASPEED_CLK_GATE_EMMCCLK		36
53 
54 #define ASPEED_CLK_GATE_I3C0CLK		37
55 #define ASPEED_CLK_GATE_I3C1CLK		38
56 #define ASPEED_CLK_GATE_I3C2CLK		39
57 #define ASPEED_CLK_GATE_I3C3CLK		40
58 #define ASPEED_CLK_GATE_I3C4CLK		41
59 #define ASPEED_CLK_GATE_I3C5CLK		42
60 
61 #define ASPEED_CLK_GATE_FSICLK		45
62 
63 #define ASPEED_CLK_HPLL			46
64 #define ASPEED_CLK_MPLL			47
65 #define ASPEED_CLK_DPLL			48
66 #define ASPEED_CLK_EPLL			49
67 #define ASPEED_CLK_APLL			50
68 #define ASPEED_CLK_AHB			51
69 #define ASPEED_CLK_APB1			52
70 #define ASPEED_CLK_APB2			53
71 #define ASPEED_CLK_BCLK			54
72 #define ASPEED_CLK_D1CLK		55
73 #define ASPEED_CLK_VCLK			56
74 #define ASPEED_CLK_LHCLK		57
75 #define ASPEED_CLK_UART			58
76 #define ASPEED_CLK_UARTX		59
77 #define ASPEED_CLK_SDIO			60
78 #define ASPEED_CLK_EMMC			61
79 #define ASPEED_CLK_ECLK			62
80 #define ASPEED_CLK_ECLK_MUX		63
81 #define ASPEED_CLK_MAC12		64
82 #define ASPEED_CLK_MAC34		65
83 #define ASPEED_CLK_USBPHY_40M		66
84 #define ASPEED_CLK_MAC1RCLK		67
85 #define ASPEED_CLK_MAC2RCLK		68
86 #define ASPEED_CLK_MAC3RCLK		69
87 #define ASPEED_CLK_MAC4RCLK		70
88 #define ASPEED_CLK_I3C			71
89 
90 /* Only list resets here that are not part of a clock gate + reset pair */
91 #define ASPEED_RESET_ADC		55
92 #define ASPEED_RESET_JTAG_MASTER2	54
93 
94 #define ASPEED_RESET_MAC4		53
95 #define ASPEED_RESET_MAC3		52
96 
97 #define ASPEED_RESET_I3C5		45
98 #define ASPEED_RESET_I3C4		44
99 #define ASPEED_RESET_I3C3		43
100 #define ASPEED_RESET_I3C2		42
101 #define ASPEED_RESET_I3C1		41
102 #define ASPEED_RESET_I3C0		40
103 #define ASPEED_RESET_I3C		39
104 #define ASPEED_RESET_I3C_DMA		39
105 
106 #define ASPEED_RESET_PWM		37
107 #define ASPEED_RESET_PECI		36
108 #define ASPEED_RESET_MII		35
109 #define ASPEED_RESET_I2C		34
110 #define ASPEED_RESET_H2X		31
111 #define ASPEED_RESET_GP_MCU		30
112 #define ASPEED_RESET_DP_MCU		29
113 #define ASPEED_RESET_DP			28
114 #define ASPEED_RESET_RC_XDMA		27
115 #define ASPEED_RESET_GRAPHICS		26
116 #define ASPEED_RESET_DEV_XDMA		25
117 #define ASPEED_RESET_DEV_MCTP		24
118 #define ASPEED_RESET_RC_MCTP		23
119 #define ASPEED_RESET_JTAG_MASTER	22
120 #define ASPEED_RESET_PCIE_DEV_O		21
121 #define ASPEED_RESET_PCIE_DEV_OEN	20
122 #define ASPEED_RESET_PCIE_RC_O		19
123 #define ASPEED_RESET_PCIE_RC_OEN	18
124 #define ASPEED_RESET_PCI_DP		5
125 #define ASPEED_RESET_HACE		4
126 #define ASPEED_RESET_AHB		1
127 #define ASPEED_RESET_SDRAM		0
128 
129 #endif
130