1 /* $OpenBSD: athvar.h,v 1.36 2023/03/26 08:45:27 jsg Exp $ */ 2 /* $NetBSD: athvar.h,v 1.10 2004/08/10 01:03:53 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * NO WARRANTY 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGES. 34 * 35 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.14 2004/04/03 03:33:02 sam Exp $ 36 */ 37 38 /* 39 * Definitions for the Atheros Wireless LAN controller driver. 40 */ 41 #ifndef _DEV_ATH_ATHVAR_H 42 #define _DEV_ATH_ATHVAR_H 43 44 #ifdef _KERNEL 45 46 #include <net80211/ieee80211_radiotap.h> 47 #include <dev/ic/ar5xxx.h> 48 49 #include "bpfilter.h" 50 51 #ifdef notyet 52 #include "gpio.h" 53 #endif 54 55 #define ATH_TIMEOUT 1000 56 57 #define ATH_RXBUF 40 /* number of RX buffers */ 58 #define ATH_TXBUF 60 /* number of TX buffers */ 59 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 60 #define ATH_MAXGPIO 10 /* maximal number of gpio pins */ 61 62 struct ath_recv_hist { 63 int arh_ticks; /* sample time by system clock */ 64 u_int8_t arh_rssi; /* rssi */ 65 u_int8_t arh_antenna; /* antenna */ 66 }; 67 #define ATH_RHIST_SIZE 16 /* number of samples */ 68 #define ATH_RHIST_NOTIME (~0) 69 70 /* 71 * Ioctl-related definitions for the Atheros Wireless LAN controller driver. 72 */ 73 struct ath_stats { 74 u_int32_t ast_watchdog; /* device reset by watchdog */ 75 u_int32_t ast_hardware; /* fatal hardware error interrupts */ 76 u_int32_t ast_bmiss; /* beacon miss interrupts */ 77 u_int32_t ast_mib; /* MIB counter interrupts */ 78 u_int32_t ast_rxorn; /* rx overrun interrupts */ 79 u_int32_t ast_rxeol; /* rx eol interrupts */ 80 u_int32_t ast_txurn; /* tx underrun interrupts */ 81 u_int32_t ast_intrcoal; /* interrupts coalesced */ 82 u_int32_t ast_tx_mgmt; /* management frames transmitted */ 83 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 84 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 85 u_int32_t ast_tx_encap; /* tx encapsulation failed */ 86 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 87 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 88 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 89 u_int32_t ast_tx_linear; /* tx linearized to cluster */ 90 u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 91 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 92 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 93 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 94 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 95 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 96 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 97 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 98 u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 99 u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 100 u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 101 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 102 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 103 u_int32_t ast_tx_protect; /* tx frames with protection */ 104 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 105 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 106 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 107 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 108 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 109 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 110 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 111 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 112 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 113 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 114 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 115 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 116 u_int32_t ast_per_cal; /* periodic calibration calls */ 117 u_int32_t ast_per_calfail;/* periodic calibration failed */ 118 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 119 u_int32_t ast_rate_calls; /* rate control checks */ 120 u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 121 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 122 }; 123 124 /* 125 * Radio capture format. 126 */ 127 #define ATH_RX_RADIOTAP_PRESENT ( \ 128 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 129 (1 << IEEE80211_RADIOTAP_RATE) | \ 130 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 131 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 132 (1 << IEEE80211_RADIOTAP_RSSI) | \ 133 0) 134 135 struct ath_rx_radiotap_header { 136 struct ieee80211_radiotap_header wr_ihdr; 137 u_int8_t wr_flags; 138 u_int8_t wr_rate; 139 u_int16_t wr_chan_freq; 140 u_int16_t wr_chan_flags; 141 u_int8_t wr_antenna; 142 u_int8_t wr_rssi; 143 u_int8_t wr_max_rssi; 144 } __packed; 145 146 #define ATH_TX_RADIOTAP_PRESENT ( \ 147 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 148 (1 << IEEE80211_RADIOTAP_RATE) | \ 149 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 150 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 151 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 152 0) 153 154 struct ath_tx_radiotap_header { 155 struct ieee80211_radiotap_header wt_ihdr; 156 u_int8_t wt_flags; 157 u_int8_t wt_rate; 158 u_int16_t wt_chan_freq; 159 u_int16_t wt_chan_flags; 160 u_int8_t wt_txpower; 161 u_int8_t wt_antenna; 162 } __packed; 163 164 /* 165 * driver-specific node 166 */ 167 struct ath_node { 168 struct ieee80211_node an_node; /* base class */ 169 struct ieee80211_rssadapt an_rssadapt; /* rate adaption */ 170 u_int an_tx_antenna; /* antenna for last good frame */ 171 u_int an_rx_antenna; /* antenna for last rcvd frame */ 172 struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE]; 173 u_int an_rx_hist_next;/* index of next ``free entry'' */ 174 }; 175 #define ATH_NODE(_n) ((struct ath_node *)(_n)) 176 177 struct ath_buf { 178 TAILQ_ENTRY(ath_buf) bf_list; 179 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 180 #define bf_nseg bf_dmamap->dm_nsegs 181 #define bf_mapsize bf_dmamap->dm_mapsize 182 #define bf_segs bf_dmamap->dm_segs 183 struct ath_desc *bf_desc; /* virtual addr of desc */ 184 bus_addr_t bf_daddr; /* physical addr of desc */ 185 struct mbuf *bf_m; /* mbuf for buf */ 186 struct ieee80211_node *bf_node; /* pointer to the node */ 187 struct ieee80211_rssdesc bf_id; 188 #define ATH_MAX_SCATTER 64 189 }; 190 191 typedef struct ath_task { 192 void (*t_func)(void*, int); 193 void *t_context; 194 } ath_task_t; 195 196 struct ath_softc { 197 struct device sc_dev; 198 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 199 int (*sc_enable)(struct ath_softc *); 200 void (*sc_disable)(struct ath_softc *); 201 void (*sc_power)(struct ath_softc *, int); 202 int (*sc_newstate)(struct ieee80211com *, 203 enum ieee80211_state, int); 204 void (*sc_node_free)(struct ieee80211com *, 205 struct ieee80211_node *); 206 void (*sc_node_copy)(struct ieee80211com *, 207 struct ieee80211_node *, 208 const struct ieee80211_node *); 209 void (*sc_recv_mgmt)(struct ieee80211com *, 210 struct mbuf *, struct ieee80211_node *, 211 struct ieee80211_rxinfo *, int); 212 bus_space_tag_t sc_st; /* bus space tag */ 213 bus_space_handle_t sc_sh; /* bus space handle */ 214 bus_size_t sc_ss; /* bus space size */ 215 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 216 struct ath_hal *sc_ah; /* Atheros HAL */ 217 unsigned int sc_invalid : 1, /* disable hardware accesses */ 218 sc_doani : 1, /* dynamic noise immunity */ 219 sc_veol : 1, /* tx VEOL support */ 220 sc_softled : 1, /* GPIO software LED */ 221 sc_probing : 1, /* probing AP on beacon miss */ 222 sc_pcie : 1; /* indicates PCI Express */ 223 u_int sc_nchan; /* number of valid channels */ 224 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 225 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 226 enum ieee80211_phymode sc_curmode; /* current phy mode */ 227 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 228 u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */ 229 HAL_INT sc_imask; /* interrupt mask copy */ 230 231 #if NBPFILTER > 0 232 caddr_t sc_drvbpf; 233 234 union { 235 struct ath_rx_radiotap_header th; 236 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 237 } sc_rxtapu; 238 #define sc_rxtap sc_rxtapu.th 239 int sc_rxtap_len; 240 241 union { 242 struct ath_tx_radiotap_header th; 243 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN]; 244 } sc_txtapu; 245 #define sc_txtap sc_txtapu.th 246 int sc_txtap_len; 247 #endif 248 249 struct ath_desc *sc_desc; /* TX/RX descriptors */ 250 bus_dma_segment_t sc_dseg; 251 int sc_dnseg; /* number of segments */ 252 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 253 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 254 bus_addr_t sc_desc_len; /* size of sc_desc */ 255 256 ath_task_t sc_fataltask; /* fatal int processing */ 257 ath_task_t sc_rxorntask; /* rxorn int processing */ 258 259 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 260 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 261 ath_task_t sc_rxtask; /* rx int processing */ 262 263 u_int sc_txhalq[HAL_NUM_TX_QUEUES]; /* HAL q for outgoing frames */ 264 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 265 int sc_tx_timer; /* transmit timeout */ 266 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 267 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 268 ath_task_t sc_txtask; /* tx int processing */ 269 270 u_int sc_bhalq; /* HAL q for outgoing beacons */ 271 struct ath_buf *sc_bcbuf; /* beacon buffer */ 272 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 273 ath_task_t sc_swbatask; /* swba int processing */ 274 ath_task_t sc_bmisstask; /* bmiss int processing */ 275 276 struct timeval sc_last_ch; 277 struct timeout sc_cal_to; 278 struct timeval sc_last_beacon; 279 struct timeout sc_scan_to; 280 struct timeout sc_rssadapt_to; 281 struct ath_stats sc_stats; /* interface statistics */ 282 HAL_MIB_STATS sc_mib_stats; /* MIB counter statistics */ 283 284 u_int sc_flags; /* misc flags */ 285 286 u_int8_t sc_broadcast_addr[IEEE80211_ADDR_LEN]; 287 288 struct gpio_chipset_tag sc_gpio_gc; /* gpio(4) framework */ 289 gpio_pin_t sc_gpio_pins[ATH_MAXGPIO]; 290 }; 291 292 /* unaligned little endian access */ 293 #define LE_READ_2(p) \ 294 ((u_int16_t) \ 295 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 296 #define LE_READ_4(p) \ 297 ((u_int32_t) \ 298 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 299 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 300 301 #ifdef AR_DEBUG 302 enum { 303 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 304 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 305 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 306 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 307 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 308 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 309 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 310 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 311 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 312 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 313 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 314 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 315 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 316 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 317 ATH_DEBUG_ANY = 0xffffffff 318 }; 319 #define IFF_DUMPPKTS(_ifp, _m) \ 320 ((ath_debug & _m) || \ 321 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 322 #define DPRINTF(_m,X) if (ath_debug & (_m)) printf X 323 #else 324 #define IFF_DUMPPKTS(_ifp, _m) \ 325 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 326 #define DPRINTF(_m, X) 327 #endif 328 329 /* 330 * Wrapper code 331 */ 332 #undef KASSERT 333 #define KASSERT(cond, complaint) if (!(cond)) panic complaint 334 335 #define ATH_ATTACHED 0x0001 /* attach has succeeded */ 336 #define ATH_ENABLED 0x0002 /* chip is enabled */ 337 #define ATH_GPIO 0x0004 /* gpio device attached */ 338 339 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED) 340 341 #define ATH_LOCK_INIT(_sc) \ 342 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 343 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE) 344 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 345 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 346 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 347 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 348 349 #define ATH_TXBUF_LOCK_INIT(_sc) \ 350 mtx_init(&(_sc)->sc_txbuflock, \ 351 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF) 352 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 353 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 354 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 355 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 356 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 357 358 #define ATH_TXQ_LOCK_INIT(_sc) \ 359 mtx_init(&(_sc)->sc_txqlock, \ 360 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF) 361 #define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock) 362 #define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock) 363 #define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock) 364 #define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED) 365 366 #define ATH_TICKS() (ticks) 367 #define ATH_CALLOUT_INIT(chp) callout_init((chp)) 368 #define ATH_TASK_INIT(task, func, context) \ 369 do { \ 370 (task)->t_func = (func); \ 371 (task)->t_context = (context); \ 372 } while (0) 373 #define ATH_TASK_RUN_OR_ENQUEUE(task) ((*(task)->t_func)((task)->t_context, 1)) 374 375 typedef unsigned long u_intptr_t; 376 377 int ath_attach(u_int16_t, struct ath_softc *); 378 int ath_detach(struct ath_softc *, int); 379 int ath_enable(struct ath_softc *); 380 int ath_activate(struct device *, int); 381 int ath_intr(void *); 382 int ath_enable(struct ath_softc *); 383 384 /* 385 * HAL definitions to comply with local coding convention. 386 */ 387 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 388 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 389 #define ath_hal_get_rate_table(_ah, _mode) \ 390 ((*(_ah)->ah_get_rate_table)((_ah), (_mode))) 391 #define ath_hal_get_lladdr(_ah, _mac) \ 392 ((*(_ah)->ah_get_lladdr)((_ah), (_mac))) 393 #define ath_hal_set_lladdr(_ah, _mac) \ 394 ((*(_ah)->ah_set_lladdr)((_ah), (_mac))) 395 #define ath_hal_set_intr(_ah, _mask) \ 396 ((*(_ah)->ah_set_intr)((_ah), (_mask))) 397 #define ath_hal_get_intr(_ah) \ 398 ((*(_ah)->ah_get_intr)((_ah))) 399 #define ath_hal_is_intr_pending(_ah) \ 400 ((*(_ah)->ah_is_intr_pending)((_ah))) 401 #define ath_hal_get_isr(_ah, _pmask) \ 402 ((*(_ah)->ah_get_isr)((_ah), (_pmask))) 403 #define ath_hal_update_tx_triglevel(_ah, _inc) \ 404 ((*(_ah)->ah_update_tx_triglevel)((_ah), (_inc))) 405 #define ath_hal_set_power(_ah, _mode, _sleepduration) \ 406 ((*(_ah)->ah_set_power)((_ah), (_mode), AH_TRUE, (_sleepduration))) 407 #define ath_hal_reset_key(_ah, _ix) \ 408 ((*(_ah)->ah_reset_key)((_ah), (_ix))) 409 #define ath_hal_set_key(_ah, _ix, _pk) \ 410 ((*(_ah)->ah_set_key)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 411 #define ath_hal_is_key_valid(_ah, _ix) \ 412 (((*(_ah)->ah_is_key_valid)((_ah), (_ix)))) 413 #define ath_hal_set_key_lladdr(_ah, _ix, _mac) \ 414 ((*(_ah)->ah_set_key_lladdr)((_ah), (_ix), (_mac))) 415 #define ath_hal_softcrypto(_ah, _val ) \ 416 ((*(_ah)->ah_softcrypto)((_ah), (_val))) 417 #define ath_hal_get_rx_filter(_ah) \ 418 ((*(_ah)->ah_get_rx_filter)((_ah))) 419 #define ath_hal_set_rx_filter(_ah, _filter) \ 420 ((*(_ah)->ah_set_rx_filter)((_ah), (_filter))) 421 #define ath_hal_set_mcast_filter(_ah, _mfilt0, _mfilt1) \ 422 ((*(_ah)->ah_set_mcast_filter)((_ah), (_mfilt0), (_mfilt1))) 423 #define ath_hal_wait_for_beacon(_ah, _bf) \ 424 ((*(_ah)->ah_wait_for_beacon)((_ah), (_bf)->bf_daddr)) 425 #define ath_hal_put_rx_buf(_ah, _bufaddr) \ 426 ((*(_ah)->ah_put_rx_buf)((_ah), (_bufaddr))) 427 #define ath_hal_get_tsf32(_ah) \ 428 ((*(_ah)->ah_get_tsf32)((_ah))) 429 #define ath_hal_get_tsf64(_ah) \ 430 ((*(_ah)->ah_get_tsf64)((_ah))) 431 #define ath_hal_reset_tsf(_ah) \ 432 ((*(_ah)->ah_reset_tsf)((_ah))) 433 #define ath_hal_start_rx(_ah) \ 434 ((*(_ah)->ah_start_rx)((_ah))) 435 #define ath_hal_put_tx_buf(_ah, _q, _bufaddr) \ 436 ((*(_ah)->ah_put_tx_buf)((_ah), (_q), (_bufaddr))) 437 #define ath_hal_get_tx_buf(_ah, _q) \ 438 ((*(_ah)->ah_get_tx_buf)((_ah), (_q))) 439 #define ath_hal_get_rx_buf(_ah) \ 440 ((*(_ah)->ah_get_rx_buf)((_ah))) 441 #define ath_hal_tx_start(_ah, _q) \ 442 ((*(_ah)->ah_tx_start)((_ah), (_q))) 443 #define ath_hal_setchannel(_ah, _chan) \ 444 ((*(_ah)->ah_setchannel)((_ah), (_chan))) 445 #define ath_hal_calibrate(_ah, _chan) \ 446 ((*(_ah)->ah_calibrate)((_ah), (_chan))) 447 #define ath_hal_set_ledstate(_ah, _state) \ 448 ((*(_ah)->ah_set_ledstate)((_ah), (_state))) 449 #define ath_hal_init_beacon(_ah, _nextb, _bperiod) \ 450 ((*(_ah)->ah_init_beacon)((_ah), (_nextb), (_bperiod))) 451 #define ath_hal_reset_beacon(_ah) \ 452 ((*(_ah)->ah_reset_beacon)((_ah))) 453 #define ath_hal_set_beacon_timers(_ah, _bs, _tsf, _dc, _cc) \ 454 ((*(_ah)->ah_set_beacon_timers)((_ah), (_bs), (_tsf), \ 455 (_dc), (_cc))) 456 #define ath_hal_set_associd(_ah, _bss, _associd) \ 457 ((*(_ah)->ah_set_associd)((_ah), (_bss), (_associd), 0)) 458 #define ath_hal_get_regdomain(_ah, _prd) \ 459 (*(_prd) = (_ah)->ah_get_regdomain(_ah)) 460 #define ath_hal_detach(_ah) \ 461 ((*(_ah)->ah_detach)(_ah)) 462 #define ath_hal_set_slot_time(_ah, _t) \ 463 ((*(_ah)->ah_set_slot_time)(_ah, _t)) 464 #define ath_hal_set_gpio_output(_ah, _gpio) \ 465 ((*(_ah)->ah_set_gpio_output)((_ah), (_gpio))) 466 #define ath_hal_set_gpio_input(_ah, _gpio) \ 467 ((*(_ah)->ah_set_gpio_input)((_ah), (_gpio))) 468 #define ath_hal_get_gpio(_ah, _gpio) \ 469 ((*(_ah)->ah_get_gpio)((_ah), (_gpio))) 470 #define ath_hal_set_gpio(_ah, _gpio, _b) \ 471 ((*(_ah)->ah_set_gpio)((_ah), (_gpio), (_b))) 472 #define ath_hal_set_gpio_intr(_ah, _gpio, _b) \ 473 ((*(_ah)->ah_set_gpio_intr)((_ah), (_gpio), (_b))) 474 475 #define ath_hal_set_opmode(_ah) \ 476 ((*(_ah)->ah_set_opmode)((_ah))) 477 #define ath_hal_stop_tx_dma(_ah, _qnum) \ 478 ((*(_ah)->ah_stop_tx_dma)((_ah), (_qnum))) 479 #define ath_hal_stop_pcu_recv(_ah) \ 480 ((*(_ah)->ah_stop_pcu_recv)((_ah))) 481 #define ath_hal_start_rx_pcu(_ah) \ 482 ((*(_ah)->ah_start_rx_pcu)((_ah))) 483 #define ath_hal_stop_rx_dma(_ah) \ 484 ((*(_ah)->ah_stop_rx_dma)((_ah))) 485 #define ath_hal_get_diag_state(_ah, _id, _indata, _insize, _outdata, _outsize) \ 486 ((*(_ah)->ah_get_diag_state)((_ah), (_id), \ 487 (_indata), (_insize), (_outdata), (_outsize))) 488 489 #define ath_hal_setup_tx_queue(_ah, _type, _qinfo) \ 490 ((*(_ah)->ah_setup_tx_queue)((_ah), (_type), (_qinfo))) 491 #define ath_hal_reset_tx_queue(_ah, _q) \ 492 ((*(_ah)->ah_reset_tx_queue)((_ah), (_q))) 493 #define ath_hal_release_tx_queue(_ah, _q) \ 494 ((*(_ah)->ah_release_tx_queue)((_ah), (_q))) 495 #define ath_hal_has_veol(_ah) \ 496 ((*(_ah)->ah_has_veol)((_ah))) 497 #define ath_hal_update_mib_counters(_ah, _stats) \ 498 ((*(_ah)->ah_update_mib_counters)((_ah), (_stats))) 499 #define ath_hal_get_rf_gain(_ah) \ 500 ((*(_ah)->ah_get_rf_gain)((_ah))) 501 #define ath_hal_set_rx_signal(_ah) \ 502 ((*(_ah)->ah_set_rx_signal)((_ah))) 503 504 #define ath_hal_setup_rx_desc(_ah, _ds, _size, _intreq) \ 505 ((*(_ah)->ah_setup_rx_desc)((_ah), (_ds), (_size), (_intreq))) 506 #define ath_hal_proc_rx_desc(_ah, _ds, _dspa, _dsnext) \ 507 ((*(_ah)->ah_proc_rx_desc)((_ah), (_ds), (_dspa), (_dsnext))) 508 #define ath_hal_setup_tx_desc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 509 _txr0, _txtr0, _keyix, _ant, _flags, \ 510 _rtsrate, _rtsdura) \ 511 ((*(_ah)->ah_setup_tx_desc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 512 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 513 (_flags), (_rtsrate), (_rtsdura))) 514 #define ath_hal_setup_xtx_desc(_ah, _ds, \ 515 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 516 ((*(_ah)->ah_setup_xtx_desc)((_ah), (_ds), \ 517 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 518 #define ath_hal_fill_tx_desc(_ah, _ds, _l, _first, _last) \ 519 ((*(_ah)->ah_fill_tx_desc)((_ah), (_ds), (_l), (_first), (_last))) 520 #define ath_hal_proc_tx_desc(_ah, _ds) \ 521 ((*(_ah)->ah_proc_tx_desc)((_ah), (_ds))) 522 523 #endif /* _KERNEL */ 524 525 #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 526 527 #endif /* _DEV_ATH_ATHVAR_H */ 528