1 /** @file 2 Intel CPUID leaf definitions. 3 4 Provides defines for CPUID leaf indexes. Data structures are provided for 5 registers returned by a CPUID leaf that contain one or more bit fields. 6 If a register returned is a single 32-bit value, then a data structure is 7 not provided for that register. 8 9 Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR> 10 SPDX-License-Identifier: BSD-2-Clause-Patent 11 12 @par Specification Reference: 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, 14 November 2018, CPUID instruction. 15 Architecture Specification: Intel(R) Trust Domain Extensions Module, Chap 10.2 16 344425-003US, August 2021 17 18 **/ 19 20 #ifndef __INTEL_CPUID_H__ 21 #define __INTEL_CPUID_H__ 22 23 /** 24 CPUID Signature Information 25 26 @param EAX CPUID_SIGNATURE (0x00) 27 28 @retval EAX Returns the highest value the CPUID instruction recognizes for 29 returning basic processor information. The value is returned is 30 processor specific. 31 @retval EBX First 4 characters of a vendor identification string. 32 @retval ECX Last 4 characters of a vendor identification string. 33 @retval EDX Middle 4 characters of a vendor identification string. 34 35 <b>Example usage</b> 36 @code 37 UINT32 Eax; 38 UINT32 Ebx; 39 UINT32 Ecx; 40 UINT32 Edx; 41 42 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); 43 @endcode 44 **/ 45 #define CPUID_SIGNATURE 0x00 46 47 /// 48 /// @{ CPUID signature values returned by Intel processors 49 /// 50 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u') 51 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I') 52 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l') 53 /// 54 /// @} 55 /// 56 57 /** 58 CPUID Version Information 59 60 @param EAX CPUID_VERSION_INFO (0x01) 61 62 @retval EAX Returns Model, Family, Stepping Information described by the 63 type CPUID_VERSION_INFO_EAX. 64 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by 65 the type CPUID_VERSION_INFO_EBX. 66 @retval ECX CPU Feature Information described by the type 67 CPUID_VERSION_INFO_ECX. 68 @retval EDX CPU Feature Information described by the type 69 CPUID_VERSION_INFO_EDX. 70 71 <b>Example usage</b> 72 @code 73 CPUID_VERSION_INFO_EAX Eax; 74 CPUID_VERSION_INFO_EBX Ebx; 75 CPUID_VERSION_INFO_ECX Ecx; 76 CPUID_VERSION_INFO_EDX Edx; 77 78 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 79 @endcode 80 **/ 81 #define CPUID_VERSION_INFO 0x01 82 83 /** 84 CPUID Version Information returned in EAX for CPUID leaf 85 #CPUID_VERSION_INFO. 86 **/ 87 typedef union { 88 /// 89 /// Individual bit fields 90 /// 91 struct { 92 UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID 93 UINT32 Model : 4; ///< [Bits 7:4] Model 94 UINT32 FamilyId : 4; ///< [Bits 11:8] Family 95 UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type 96 UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved 97 UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID 98 UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID 99 UINT32 Reserved2 : 4; ///< Reserved 100 } Bits; 101 /// 102 /// All bit fields as a 32-bit value 103 /// 104 UINT32 Uint32; 105 } CPUID_VERSION_INFO_EAX; 106 107 /// 108 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType 109 /// 110 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00 111 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01 112 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02 113 /// 114 /// @} 115 /// 116 117 /** 118 CPUID Version Information returned in EBX for CPUID leaf 119 #CPUID_VERSION_INFO. 120 **/ 121 typedef union { 122 /// 123 /// Individual bit fields 124 /// 125 struct { 126 /// 127 /// [Bits 7:0] Provides an entry into a brand string table that contains 128 /// brand strings for IA-32 processors. 129 /// 130 UINT32 BrandIndex : 8; 131 /// 132 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH 133 /// and CLFLUSHOPT instructions in 8-byte increments. This field was 134 /// introduced in the Pentium 4 processor. 135 /// 136 UINT32 CacheLineSize : 8; 137 /// 138 /// [Bits 23:16] Maximum number of addressable IDs for logical processors 139 /// in this physical package. 140 /// 141 /// @note 142 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is 143 /// the number of unique initial APICIDs reserved for addressing different 144 /// logical processors in a physical package. This field is only valid if 145 /// CPUID.1.EDX.HTT[bit 28]= 1. 146 /// 147 UINT32 MaximumAddressableIdsForLogicalProcessors : 8; 148 /// 149 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the 150 /// processor during power up. This field was introduced in the Pentium 4 151 /// processor. 152 /// 153 UINT32 InitialLocalApicId : 8; 154 } Bits; 155 /// 156 /// All bit fields as a 32-bit value 157 /// 158 UINT32 Uint32; 159 } CPUID_VERSION_INFO_EBX; 160 161 /** 162 CPUID Version Information returned in ECX for CPUID leaf 163 #CPUID_VERSION_INFO. 164 **/ 165 typedef union { 166 /// 167 /// Individual bit fields 168 /// 169 struct { 170 /// 171 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the 172 /// processor supports this technology 173 /// 174 UINT32 SSE3 : 1; 175 /// 176 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ 177 /// instruction. Carryless Multiplication 178 /// 179 UINT32 PCLMULQDQ : 1; 180 /// 181 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports 182 /// DS area using 64-bit layout. 183 /// 184 UINT32 DTES64 : 1; 185 /// 186 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports 187 /// this feature. 188 /// 189 UINT32 MONITOR : 1; 190 /// 191 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor 192 /// supports the extensions to the Debug Store feature to allow for branch 193 /// message storage qualified by CPL 194 /// 195 UINT32 DS_CPL : 1; 196 /// 197 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the 198 /// processor supports this technology. 199 /// 200 UINT32 VMX : 1; 201 /// 202 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor 203 /// supports this technology 204 /// 205 UINT32 SMX : 1; 206 /// 207 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates 208 /// that the processor supports this technology 209 /// 210 UINT32 EIST : 1; 211 /// 212 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor 213 /// supports this technology 214 /// 215 UINT32 TM2 : 1; 216 /// 217 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming 218 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction 219 /// extensions are not present in the processor. 220 /// 221 UINT32 SSSE3 : 1; 222 /// 223 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode 224 /// can be set to either adaptive mode or shared mode. A value of 0 indicates 225 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR 226 /// Bit 24 (L1 Data Cache Context Mode) for details 227 /// 228 UINT32 CNXT_ID : 1; 229 /// 230 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE 231 /// MSR for silicon debug 232 /// 233 UINT32 SDBG : 1; 234 /// 235 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple 236 /// Add) extensions using YMM state. 237 /// 238 UINT32 FMA : 1; 239 /// 240 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature 241 /// is available. 242 /// 243 UINT32 CMPXCHG16B : 1; 244 /// 245 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor 246 /// supports changing IA32_MISC_ENABLE[Bit 23]. 247 /// 248 UINT32 xTPR_Update_Control : 1; 249 /// 250 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the 251 /// processor supports the performance and debug feature indication MSR 252 /// IA32_PERF_CAPABILITIES. 253 /// 254 UINT32 PDCM : 1; 255 UINT32 Reserved : 1; 256 /// 257 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the 258 /// processor supports PCIDs and that software may set CR4.PCIDE to 1. 259 /// 260 UINT32 PCID : 1; 261 /// 262 /// [Bit 18] A value of 1 indicates the processor supports the ability to 263 /// prefetch data from a memory mapped device. Direct Cache Access. 264 /// 265 UINT32 DCA : 1; 266 /// 267 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1. 268 /// 269 UINT32 SSE4_1 : 1; 270 /// 271 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2. 272 /// 273 UINT32 SSE4_2 : 1; 274 /// 275 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC 276 /// feature. 277 /// 278 UINT32 x2APIC : 1; 279 /// 280 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE 281 /// instruction. 282 /// 283 UINT32 MOVBE : 1; 284 /// 285 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT 286 /// instruction. 287 /// 288 UINT32 POPCNT : 1; 289 /// 290 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer 291 /// supports one-shot operation using a TSC deadline value. 292 /// 293 UINT32 TSC_Deadline : 1; 294 /// 295 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI 296 /// instruction extensions. 297 /// 298 UINT32 AESNI : 1; 299 /// 300 /// [Bit 26] A value of 1 indicates that the processor supports the 301 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV 302 /// instructions, and XCR0. 303 /// 304 UINT32 XSAVE : 1; 305 /// 306 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18] 307 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support 308 /// processor extended state management using XSAVE/XRSTOR. 309 /// 310 UINT32 OSXSAVE : 1; 311 /// 312 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction 313 /// extensions. 314 /// 315 UINT32 AVX : 1; 316 /// 317 /// [Bit 29] A value of 1 indicates that processor supports 16-bit 318 /// floating-point conversion instructions. 319 /// 320 UINT32 F16C : 1; 321 /// 322 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction. 323 /// 324 UINT32 RDRAND : 1; 325 /// 326 /// [Bit 31] A value of 1 indicates that processor is in Para-Virtualized. 327 /// 328 UINT32 ParaVirtualized : 1; 329 } Bits; 330 /// 331 /// All bit fields as a 32-bit value 332 /// 333 UINT32 Uint32; 334 } CPUID_VERSION_INFO_ECX; 335 336 /** 337 CPUID Version Information returned in EDX for CPUID leaf 338 #CPUID_VERSION_INFO. 339 **/ 340 typedef union { 341 /// 342 /// Individual bit fields 343 /// 344 struct { 345 /// 346 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU. 347 /// 348 UINT32 FPU : 1; 349 /// 350 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, 351 /// including CR4.VME for controlling the feature, CR4.PVI for protected 352 /// mode virtual interrupts, software interrupt indirection, expansion of 353 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and 354 /// EFLAGS.VIP flags. 355 /// 356 UINT32 VME : 1; 357 /// 358 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including 359 /// CR4.DE for controlling the feature, and optional trapping of accesses to 360 /// DR4 and DR5. 361 /// 362 UINT32 DE : 1; 363 /// 364 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported, 365 /// including CR4.PSE for controlling the feature, the defined dirty bit in 366 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3, 367 /// PDEs, and PTEs. 368 /// 369 UINT32 PSE : 1; 370 /// 371 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported, 372 /// including CR4.TSD for controlling privilege. 373 /// 374 UINT32 TSC : 1; 375 /// 376 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The 377 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are 378 /// implementation dependent. 379 /// 380 UINT32 MSR : 1; 381 /// 382 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32 383 /// bits are supported: extended page table entry formats, an extra level in 384 /// the page translation tables is defined, 2-MByte pages are supported 385 /// instead of 4 Mbyte pages if PAE bit is 1. 386 /// 387 UINT32 PAE : 1; 388 /// 389 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine 390 /// Checks, including CR4.MCE for controlling the feature. This feature does 391 /// not define the model-specific implementations of machine-check error 392 /// logging, reporting, and processor shutdowns. Machine Check exception 393 /// handlers may have to depend on processor version to do model specific 394 /// processing of the exception, or test for the presence of the Machine 395 /// Check feature. 396 /// 397 UINT32 MCE : 1; 398 /// 399 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits) 400 /// instruction is supported (implicitly locked and atomic). 401 /// 402 UINT32 CX8 : 1; 403 /// 404 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable 405 /// Interrupt Controller (APIC), responding to memory mapped commands in the 406 /// physical address range FFFE0000H to FFFE0FFFH (by default - some 407 /// processors permit the APIC to be relocated). 408 /// 409 UINT32 APIC : 1; 410 UINT32 Reserved1 : 1; 411 /// 412 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT 413 /// and associated MSRs are supported. 414 /// 415 UINT32 SEP : 1; 416 /// 417 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap 418 /// MSR contains feature bits that describe what memory types are supported, 419 /// how many variable MTRRs are supported, and whether fixed MTRRs are 420 /// supported. 421 /// 422 UINT32 MTRR : 1; 423 /// 424 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure 425 /// entries that map a page, indicating TLB entries that are common to 426 /// different processes and need not be flushed. The CR4.PGE bit controls 427 /// this feature. 428 /// 429 UINT32 PGE : 1; 430 /// 431 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine 432 /// Check Architecture of reporting machine errors is supported. The MCG_CAP 433 /// MSR contains feature bits describing how many banks of error reporting 434 /// MSRs are supported. 435 /// 436 UINT32 MCA : 1; 437 /// 438 /// [Bit 15] Conditional Move Instructions. The conditional move instruction 439 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the 440 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported. 441 /// 442 UINT32 CMOV : 1; 443 /// 444 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This 445 /// feature augments the Memory Type Range Registers (MTRRs), allowing an 446 /// operating system to specify attributes of memory accessed through a 447 /// linear address on a 4KB granularity. 448 /// 449 UINT32 PAT : 1; 450 /// 451 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical 452 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature 453 /// indicates that upper bits of the physical address of a 4-MByte page are 454 /// encoded in bits 20:13 of the page-directory entry. Such physical 455 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size. 456 /// 457 UINT32 PSE_36 : 1; 458 /// 459 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit 460 /// processor identification number feature and the feature is enabled. 461 /// 462 UINT32 PSN : 1; 463 /// 464 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported. 465 /// 466 UINT32 CLFSH : 1; 467 UINT32 Reserved2 : 1; 468 /// 469 /// [Bit 21] Debug Store. The processor supports the ability to write debug 470 /// information into a memory resident buffer. This feature is used by the 471 /// branch trace store (BTS) and precise event-based sampling (PEBS) 472 /// facilities. 473 /// 474 UINT32 DS : 1; 475 /// 476 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The 477 /// processor implements internal MSRs that allow processor temperature to 478 /// be monitored and processor performance to be modulated in predefined 479 /// duty cycles under software control. 480 /// 481 UINT32 ACPI : 1; 482 /// 483 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX 484 /// technology. 485 /// 486 UINT32 MMX : 1; 487 /// 488 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR 489 /// instructions are supported for fast save and restore of the floating 490 /// point context. Presence of this bit also indicates that CR4.OSFXSR is 491 /// available for an operating system to indicate that it supports the 492 /// FXSAVE and FXRSTOR instructions. 493 /// 494 UINT32 FXSR : 1; 495 /// 496 /// [Bit 25] SSE. The processor supports the SSE extensions. 497 /// 498 UINT32 SSE : 1; 499 /// 500 /// [Bit 26] SSE2. The processor supports the SSE2 extensions. 501 /// 502 UINT32 SSE2 : 1; 503 /// 504 /// [Bit 27] Self Snoop. The processor supports the management of 505 /// conflicting memory types by performing a snoop of its own cache 506 /// structure for transactions issued to the bus. 507 /// 508 UINT32 SS : 1; 509 /// 510 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT 511 /// indicates there is only a single logical processor in the package and 512 /// software should assume only a single APIC ID is reserved. A value of 1 513 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of 514 /// addressable IDs for logical processors in this package) is valid for the 515 /// package. 516 /// 517 UINT32 HTT : 1; 518 /// 519 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor 520 /// automatic thermal control circuitry (TCC). 521 /// 522 UINT32 TM : 1; 523 UINT32 Reserved3 : 1; 524 /// 525 /// [Bit 31] Pending Break Enable. The processor supports the use of the 526 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is 527 /// asserted) to signal the processor that an interrupt is pending and that 528 /// the processor should return to normal operation to handle the interrupt. 529 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. 530 /// 531 UINT32 PBE : 1; 532 } Bits; 533 /// 534 /// All bit fields as a 32-bit value 535 /// 536 UINT32 Uint32; 537 } CPUID_VERSION_INFO_EDX; 538 539 /** 540 CPUID Cache and TLB Information 541 542 @param EAX CPUID_CACHE_INFO (0x02) 543 544 @retval EAX Cache and TLB Information described by the type 545 CPUID_CACHE_INFO_CACHE_TLB. 546 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns 547 0x01 and must be ignored. Only valid if 548 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 549 @retval EBX Cache and TLB Information described by the type 550 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 551 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 552 @retval ECX Cache and TLB Information described by the type 553 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 554 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 555 @retval EDX Cache and TLB Information described by the type 556 CPUID_CACHE_INFO_CACHE_TLB. Only valid if 557 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. 558 559 <b>Example usage</b> 560 @code 561 CPUID_CACHE_INFO_CACHE_TLB Eax; 562 CPUID_CACHE_INFO_CACHE_TLB Ebx; 563 CPUID_CACHE_INFO_CACHE_TLB Ecx; 564 CPUID_CACHE_INFO_CACHE_TLB Edx; 565 566 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 567 @endcode 568 569 <b>Cache Descriptor values</b> 570 <table> 571 <tr><th>Value </th><th> Type </th><th> Description </th></tr> 572 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr> 573 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr> 574 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr> 575 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr> 576 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr> 577 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr> 578 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative, 579 32 byte line size</td></tr> 580 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative, 581 32 byte line size</td></tr> 582 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative, 583 64 byte line size</td></tr> 584 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr> 585 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr> 586 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr> 587 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr> 588 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr> 589 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr> 590 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr> 591 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 592 2 lines per sector</td></tr> 593 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 594 2 lines per sector</td></tr> 595 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr> 596 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 597 2 lines per sector</td></tr> 598 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 599 2 lines per sector</td></tr> 600 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative, 601 64 byte line size</td></tr> 602 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative, 603 64 byte line size</td></tr> 604 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache, 605 no 3rd-level cache</td></tr> 606 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr> 607 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr> 608 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr> 609 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr> 610 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr> 611 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr> 612 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr> 613 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr> 614 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size 615 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR> 616 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> 617 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr> 618 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr> 619 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr> 620 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr> 621 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr> 622 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr> 623 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr> 624 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr> 625 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr> 626 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr> 627 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr> 628 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr> 629 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr> 630 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr> 631 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr> 632 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr> 633 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr> 634 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr> 635 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr> 636 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 637 32 entries and a separate array with 1 GByte pages, 4-way set associative, 638 4 entries</td></tr> 639 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr> 640 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr> 641 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr> 642 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr> 643 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr> 644 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr> 645 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr> 646 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr> 647 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr> 648 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr> 649 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr> 650 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr> 651 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr> 652 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 653 2 lines per sector</td></tr> 654 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 655 2 lines per sector</td></tr> 656 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 657 2 lines per sector</td></tr> 658 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 659 2 lines per sector</td></tr> 660 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr> 661 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr> 662 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr> 663 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr> 664 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr> 665 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr> 666 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr> 667 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> 668 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> 669 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr> 670 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> 671 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr> 672 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr> 673 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr> 674 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr> 675 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr> 676 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 677 128 entries</td></tr> 678 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr> 679 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr> 680 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 681 1024 entries</td></tr> 682 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr> 683 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 684 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr> 685 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr> 686 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr> 687 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr> 688 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr> 689 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr> 690 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr> 691 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr> 692 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr> 693 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr> 694 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr> 695 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr> 696 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr> 697 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr> 698 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr> 699 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr> 700 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr> 701 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr> 702 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr> 703 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr> 704 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID 705 leaf 18H to query TLB and other address translation parameters.</td></tr> 706 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information, 707 use CPUID leaf 4 to query cache parameters</td></tr> 708 </table> 709 **/ 710 #define CPUID_CACHE_INFO 0x02 711 712 /** 713 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID 714 leaf #CPUID_CACHE_INFO. 715 **/ 716 typedef union { 717 /// 718 /// Individual bit fields 719 /// 720 struct { 721 UINT32 Reserved : 31; 722 /// 723 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid. 724 /// if 1, then none of the cache descriptor bytes in the register are valid. 725 /// 726 UINT32 NotValid : 1; 727 } Bits; 728 /// 729 /// Array of Cache and TLB descriptor bytes 730 /// 731 UINT8 CacheDescriptor[4]; 732 /// 733 /// All bit fields as a 32-bit value 734 /// 735 UINT32 Uint32; 736 } CPUID_CACHE_INFO_CACHE_TLB; 737 738 /** 739 CPUID Processor Serial Number 740 741 Processor serial number (PSN) is not supported in the Pentium 4 processor 742 or later. On all models, use the PSN flag (returned using CPUID) to check 743 for PSN support before accessing the feature. 744 745 @param EAX CPUID_SERIAL_NUMBER (0x03) 746 747 @retval EAX Reserved. 748 @retval EBX Reserved. 749 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in 750 Pentium III processor only; otherwise, the value in this 751 register is reserved.) 752 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in 753 Pentium III processor only; otherwise, the value in this 754 register is reserved.) 755 756 <b>Example usage</b> 757 @code 758 UINT32 Ecx; 759 UINT32 Edx; 760 761 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx); 762 @endcode 763 **/ 764 #define CPUID_SERIAL_NUMBER 0x03 765 766 /** 767 CPUID Cache Parameters 768 769 @param EAX CPUID_CACHE_PARAMS (0x04) 770 @param ECX Cache Level. Valid values start at 0. Software can enumerate 771 the deterministic cache parameters for each level of the cache 772 hierarchy starting with an index value of 0, until the 773 parameters report the value associated with the CacheType 774 field in CPUID_CACHE_PARAMS_EAX is 0. 775 776 @retval EAX Returns cache type information described by the type 777 CPUID_CACHE_PARAMS_EAX. 778 @retval EBX Returns cache line and associativity information described by 779 the type CPUID_CACHE_PARAMS_EBX. 780 @retval ECX Returns the number of sets in the cache. 781 @retval EDX Returns cache WINVD/INVD behavior described by the type 782 CPUID_CACHE_PARAMS_EDX. 783 784 <b>Example usage</b> 785 @code 786 UINT32 CacheLevel; 787 CPUID_CACHE_PARAMS_EAX Eax; 788 CPUID_CACHE_PARAMS_EBX Ebx; 789 UINT32 Ecx; 790 CPUID_CACHE_PARAMS_EDX Edx; 791 792 CacheLevel = 0; 793 do { 794 AsmCpuidEx ( 795 CPUID_CACHE_PARAMS, CacheLevel, 796 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 797 ); 798 CacheLevel++; 799 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); 800 @endcode 801 **/ 802 #define CPUID_CACHE_PARAMS 0x04 803 804 /** 805 CPUID Cache Parameters Information returned in EAX for CPUID leaf 806 #CPUID_CACHE_PARAMS. 807 **/ 808 typedef union { 809 /// 810 /// Individual bit fields 811 /// 812 struct { 813 /// 814 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, 815 /// then there is no information for the requested cache level. 816 /// 817 UINT32 CacheType : 5; 818 /// 819 /// [Bits 7:5] Cache level (Starts at 1). 820 /// 821 UINT32 CacheLevel : 3; 822 /// 823 /// [Bit 8] Self Initializing cache level (does not need SW initialization). 824 /// 825 UINT32 SelfInitializingCache : 1; 826 /// 827 /// [Bit 9] Fully Associative cache. 828 /// 829 UINT32 FullyAssociativeCache : 1; 830 /// 831 /// [Bits 13:10] Reserved. 832 /// 833 UINT32 Reserved : 4; 834 /// 835 /// [Bits 25:14] Maximum number of addressable IDs for logical processors 836 /// sharing this cache. 837 /// 838 /// Add one to the return value to get the result. 839 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) 840 /// is the number of unique initial APIC IDs reserved for addressing 841 /// different logical processors sharing this cache. 842 /// 843 UINT32 MaximumAddressableIdsForLogicalProcessors : 12; 844 /// 845 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in 846 /// the physical package. 847 /// 848 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) 849 /// is the number of unique Core_IDs reserved for addressing different 850 /// processor cores in a physical package. Core ID is a subset of bits of 851 /// the initial APIC ID. 852 /// The returned value is constant for valid initial values in ECX. Valid 853 /// ECX values start from 0. 854 /// 855 UINT32 MaximumAddressableIdsForProcessorCores : 6; 856 } Bits; 857 /// 858 /// All bit fields as a 32-bit value 859 /// 860 UINT32 Uint32; 861 } CPUID_CACHE_PARAMS_EAX; 862 863 /// 864 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType 865 /// 866 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00 867 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01 868 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02 869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03 870 /// 871 /// @} 872 /// 873 874 /** 875 CPUID Cache Parameters Information returned in EBX for CPUID leaf 876 #CPUID_CACHE_PARAMS. 877 **/ 878 typedef union { 879 /// 880 /// Individual bit fields 881 /// 882 struct { 883 /// 884 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to 885 /// get the result. 886 /// 887 UINT32 LineSize : 12; 888 /// 889 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to 890 /// get the result. 891 /// 892 UINT32 LinePartitions : 10; 893 /// 894 /// [Bits 31:22] Ways of associativity. Add one to the return value to get 895 /// the result. 896 /// 897 UINT32 Ways : 10; 898 } Bits; 899 /// 900 /// All bit fields as a 32-bit value 901 /// 902 UINT32 Uint32; 903 } CPUID_CACHE_PARAMS_EBX; 904 905 /** 906 CPUID Cache Parameters Information returned in EDX for CPUID leaf 907 #CPUID_CACHE_PARAMS. 908 **/ 909 typedef union { 910 /// 911 /// Individual bit fields 912 /// 913 struct { 914 /// 915 /// [Bit 0] Write-Back Invalidate/Invalidate. 916 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level 917 /// caches for threads sharing this cache. 918 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of 919 /// non-originating threads sharing this cache. 920 /// 921 UINT32 Invalidate : 1; 922 /// 923 /// [Bit 1] Cache Inclusiveness. 924 /// 0 = Cache is not inclusive of lower cache levels. 925 /// 1 = Cache is inclusive of lower cache levels. 926 /// 927 UINT32 CacheInclusiveness : 1; 928 /// 929 /// [Bit 2] Complex Cache Indexing. 930 /// 0 = Direct mapped cache. 931 /// 1 = A complex function is used to index the cache, potentially using all 932 /// address bits. 933 /// 934 UINT32 ComplexCacheIndexing : 1; 935 UINT32 Reserved : 29; 936 } Bits; 937 /// 938 /// All bit fields as a 32-bit value 939 /// 940 UINT32 Uint32; 941 } CPUID_CACHE_PARAMS_EDX; 942 943 /** 944 CPUID MONITOR/MWAIT Information 945 946 @param EAX CPUID_MONITOR_MWAIT (0x05) 947 948 @retval EAX Smallest monitor-line size in bytes described by the type 949 CPUID_MONITOR_MWAIT_EAX. 950 @retval EBX Largest monitor-line size in bytes described by the type 951 CPUID_MONITOR_MWAIT_EBX. 952 @retval ECX Enumeration of Monitor-Mwait extensions support described by 953 the type CPUID_MONITOR_MWAIT_ECX. 954 @retval EDX Sub C-states supported described by the type 955 CPUID_MONITOR_MWAIT_EDX. 956 957 <b>Example usage</b> 958 @code 959 CPUID_MONITOR_MWAIT_EAX Eax; 960 CPUID_MONITOR_MWAIT_EBX Ebx; 961 CPUID_MONITOR_MWAIT_ECX Ecx; 962 CPUID_MONITOR_MWAIT_EDX Edx; 963 964 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 965 @endcode 966 **/ 967 #define CPUID_MONITOR_MWAIT 0x05 968 969 /** 970 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf 971 #CPUID_MONITOR_MWAIT. 972 **/ 973 typedef union { 974 /// 975 /// Individual bit fields 976 /// 977 struct { 978 /// 979 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's 980 /// monitor granularity). 981 /// 982 UINT32 SmallestMonitorLineSize : 16; 983 UINT32 Reserved : 16; 984 } Bits; 985 /// 986 /// All bit fields as a 32-bit value 987 /// 988 UINT32 Uint32; 989 } CPUID_MONITOR_MWAIT_EAX; 990 991 /** 992 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf 993 #CPUID_MONITOR_MWAIT. 994 **/ 995 typedef union { 996 /// 997 /// Individual bit fields 998 /// 999 struct { 1000 /// 1001 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's 1002 /// monitor granularity). 1003 /// 1004 UINT32 LargestMonitorLineSize : 16; 1005 UINT32 Reserved : 16; 1006 } Bits; 1007 /// 1008 /// All bit fields as a 32-bit value 1009 /// 1010 UINT32 Uint32; 1011 } CPUID_MONITOR_MWAIT_EBX; 1012 1013 /** 1014 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf 1015 #CPUID_MONITOR_MWAIT. 1016 **/ 1017 typedef union { 1018 /// 1019 /// Individual bit fields 1020 /// 1021 struct { 1022 /// 1023 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX, 1024 /// and EDX are valid. 1025 /// 1026 UINT32 ExtensionsSupported : 1; 1027 /// 1028 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when 1029 /// interrupts disabled. 1030 /// 1031 UINT32 InterruptAsBreak : 1; 1032 UINT32 Reserved : 30; 1033 } Bits; 1034 /// 1035 /// All bit fields as a 32-bit value 1036 /// 1037 UINT32 Uint32; 1038 } CPUID_MONITOR_MWAIT_ECX; 1039 1040 /** 1041 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf 1042 #CPUID_MONITOR_MWAIT. 1043 1044 @note 1045 The definition of C0 through C7 states for MWAIT extension are 1046 processor-specific C-states, not ACPI C-states. 1047 **/ 1048 typedef union { 1049 /// 1050 /// Individual bit fields 1051 /// 1052 struct { 1053 /// 1054 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT. 1055 /// 1056 UINT32 C0States : 4; 1057 /// 1058 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT. 1059 /// 1060 UINT32 C1States : 4; 1061 /// 1062 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT. 1063 /// 1064 UINT32 C2States : 4; 1065 /// 1066 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT. 1067 /// 1068 UINT32 C3States : 4; 1069 /// 1070 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT. 1071 /// 1072 UINT32 C4States : 4; 1073 /// 1074 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT. 1075 /// 1076 UINT32 C5States : 4; 1077 /// 1078 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT. 1079 /// 1080 UINT32 C6States : 4; 1081 /// 1082 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT. 1083 /// 1084 UINT32 C7States : 4; 1085 } Bits; 1086 /// 1087 /// All bit fields as a 32-bit value 1088 /// 1089 UINT32 Uint32; 1090 } CPUID_MONITOR_MWAIT_EDX; 1091 1092 /** 1093 CPUID Thermal and Power Management 1094 1095 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06) 1096 1097 @retval EAX Thermal and power management features described by the type 1098 CPUID_THERMAL_POWER_MANAGEMENT_EAX. 1099 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor 1100 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX. 1101 @retval ECX Performance features described by the type 1102 CPUID_THERMAL_POWER_MANAGEMENT_ECX. 1103 @retval EDX Reserved. 1104 1105 <b>Example usage</b> 1106 @code 1107 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; 1108 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; 1109 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; 1110 1111 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); 1112 @endcode 1113 **/ 1114 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06 1115 1116 /** 1117 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf 1118 #CPUID_THERMAL_POWER_MANAGEMENT. 1119 **/ 1120 typedef union { 1121 /// 1122 /// Individual bit fields 1123 /// 1124 struct { 1125 /// 1126 /// [Bit 0] Digital temperature sensor is supported if set. 1127 /// 1128 UINT32 DigitalTemperatureSensor : 1; 1129 /// 1130 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]). 1131 /// 1132 UINT32 TurboBoostTechnology : 1; 1133 /// 1134 /// [Bit 2] APIC-Timer-always-running feature is supported if set. 1135 /// 1136 UINT32 ARAT : 1; 1137 UINT32 Reserved1 : 1; 1138 /// 1139 /// [Bit 4] Power limit notification controls are supported if set. 1140 /// 1141 UINT32 PLN : 1; 1142 /// 1143 /// [Bit 5] Clock modulation duty cycle extension is supported if set. 1144 /// 1145 UINT32 ECMD : 1; 1146 /// 1147 /// [Bit 6] Package thermal management is supported if set. 1148 /// 1149 UINT32 PTM : 1; 1150 /// 1151 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES, 1152 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. 1153 /// 1154 UINT32 HWP : 1; 1155 /// 1156 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set. 1157 /// 1158 UINT32 HWP_Notification : 1; 1159 /// 1160 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set. 1161 /// 1162 UINT32 HWP_Activity_Window : 1; 1163 /// 1164 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set. 1165 /// 1166 UINT32 HWP_Energy_Performance_Preference : 1; 1167 /// 1168 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set. 1169 /// 1170 UINT32 HWP_Package_Level_Request : 1; 1171 UINT32 Reserved2 : 1; 1172 /// 1173 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, 1174 /// IA32_THREAD_STALL MSRs are supported if set. 1175 /// 1176 UINT32 HDC : 1; 1177 /// 1178 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available. 1179 /// 1180 UINT32 TurboBoostMaxTechnology30 : 1; 1181 /// 1182 /// [Bit 15] HWP Capabilities. 1183 /// Highest Performance change is supported if set. 1184 /// 1185 UINT32 HWPCapabilities : 1; 1186 /// 1187 /// [Bit 16] HWP PECI override is supported if set. 1188 /// 1189 UINT32 HWPPECIOverride : 1; 1190 /// 1191 /// [Bit 17] Flexible HWP is supported if set. 1192 /// 1193 UINT32 FlexibleHWP : 1; 1194 /// 1195 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. 1196 /// 1197 UINT32 FastAccessMode : 1; 1198 UINT32 Reserved4 : 1; 1199 /// 1200 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set. 1201 /// 1202 UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1; 1203 UINT32 Reserved5 : 11; 1204 } Bits; 1205 /// 1206 /// All bit fields as a 32-bit value 1207 /// 1208 UINT32 Uint32; 1209 } CPUID_THERMAL_POWER_MANAGEMENT_EAX; 1210 1211 /** 1212 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf 1213 #CPUID_THERMAL_POWER_MANAGEMENT. 1214 **/ 1215 typedef union { 1216 /// 1217 /// Individual bit fields 1218 /// 1219 struct { 1220 /// 1221 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor. 1222 /// 1223 UINT32 InterruptThresholds : 4; 1224 UINT32 Reserved : 28; 1225 } Bits; 1226 /// 1227 /// All bit fields as a 32-bit value 1228 /// 1229 UINT32 Uint32; 1230 } CPUID_THERMAL_POWER_MANAGEMENT_EBX; 1231 1232 /** 1233 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf 1234 #CPUID_THERMAL_POWER_MANAGEMENT. 1235 **/ 1236 typedef union { 1237 /// 1238 /// Individual bit fields 1239 /// 1240 struct { 1241 /// 1242 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF 1243 /// and IA32_APERF). The capability to provide a measure of delivered 1244 /// processor performance (since last reset of the counters), as a percentage 1245 /// of the expected processor performance when running at the TSC frequency. 1246 /// 1247 UINT32 HardwareCoordinationFeedback : 1; 1248 UINT32 Reserved1 : 2; 1249 /// 1250 /// [Bit 3] If this bit is set, then the processor supports performance-energy 1251 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS 1252 /// (1B0H). 1253 /// 1254 UINT32 PerformanceEnergyBias : 1; 1255 UINT32 Reserved2 : 28; 1256 } Bits; 1257 /// 1258 /// All bit fields as a 32-bit value 1259 /// 1260 UINT32 Uint32; 1261 } CPUID_THERMAL_POWER_MANAGEMENT_ECX; 1262 1263 /** 1264 CPUID Structured Extended Feature Flags Enumeration 1265 1266 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) 1267 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00). 1268 1269 @note 1270 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 1271 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. 1272 1273 @retval EAX The maximum input value for ECX to retrieve sub-leaf information. 1274 @retval EBX Structured Extended Feature Flags described by the type 1275 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX. 1276 @retval ECX Structured Extended Feature Flags described by the type 1277 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX. 1278 @retval EDX Reserved. 1279 1280 <b>Example usage</b> 1281 @code 1282 UINT32 Eax; 1283 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; 1284 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; 1285 UINT32 SubLeaf; 1286 1287 AsmCpuidEx ( 1288 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 1289 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, 1290 &Eax, NULL, NULL, NULL 1291 ); 1292 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { 1293 AsmCpuidEx ( 1294 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 1295 SubLeaf, 1296 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL 1297 ); 1298 } 1299 @endcode 1300 **/ 1301 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 1302 1303 /// 1304 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf 1305 /// 1306 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00 1307 1308 /** 1309 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf 1310 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1311 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1312 **/ 1313 typedef union { 1314 /// 1315 /// Individual bit fields 1316 /// 1317 struct { 1318 /// 1319 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. 1320 /// 1321 UINT32 FSGSBASE : 1; 1322 /// 1323 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1. 1324 /// 1325 UINT32 IA32_TSC_ADJUST : 1; 1326 /// 1327 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT 1328 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS". 1329 /// 1330 UINT32 SGX : 1; 1331 /// 1332 /// [Bit 3] If 1 indicates the processor supports the first group of advanced 1333 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT) 1334 /// 1335 UINT32 BMI1 : 1; 1336 /// 1337 /// [Bit 4] Hardware Lock Elision 1338 /// 1339 UINT32 HLE : 1; 1340 /// 1341 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions. 1342 /// 1343 UINT32 AVX2 : 1; 1344 /// 1345 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1. 1346 /// 1347 UINT32 FDP_EXCPTN_ONLY : 1; 1348 /// 1349 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1. 1350 /// 1351 UINT32 SMEP : 1; 1352 /// 1353 /// [Bit 8] If 1 indicates the processor supports the second group of 1354 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, 1355 /// SARX, SHLX, SHRX) 1356 /// 1357 UINT32 BMI2 : 1; 1358 /// 1359 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1. 1360 /// 1361 UINT32 EnhancedRepMovsbStosb : 1; 1362 /// 1363 /// [Bit 10] If 1, supports INVPCID instruction for system software that 1364 /// manages process-context identifiers. 1365 /// 1366 UINT32 INVPCID : 1; 1367 /// 1368 /// [Bit 11] Restricted Transactional Memory 1369 /// 1370 UINT32 RTM : 1; 1371 /// 1372 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) 1373 /// Monitoring capability if 1. 1374 /// 1375 UINT32 RDT_M : 1; 1376 /// 1377 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1. 1378 /// 1379 UINT32 DeprecateFpuCsDs : 1; 1380 /// 1381 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1. 1382 /// 1383 UINT32 MPX : 1; 1384 /// 1385 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) 1386 /// Allocation capability if 1. 1387 /// 1388 UINT32 RDT_A : 1; 1389 /// 1390 /// [Bit 16] AVX512F. 1391 /// 1392 UINT32 AVX512F : 1; 1393 /// 1394 /// [Bit 17] AVX512DQ. 1395 /// 1396 UINT32 AVX512DQ : 1; 1397 /// 1398 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction. 1399 /// 1400 UINT32 RDSEED : 1; 1401 /// 1402 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX 1403 /// instructions. 1404 /// 1405 UINT32 ADX : 1; 1406 /// 1407 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC 1408 /// instructions) if 1. 1409 /// 1410 UINT32 SMAP : 1; 1411 /// 1412 /// [Bit 21] AVX512_IFMA. 1413 /// 1414 UINT32 AVX512_IFMA : 1; 1415 UINT32 Reserved6 : 1; 1416 /// 1417 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction. 1418 /// 1419 UINT32 CLFLUSHOPT : 1; 1420 /// 1421 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction. 1422 /// 1423 UINT32 CLWB : 1; 1424 /// 1425 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace 1426 /// extensions. 1427 /// 1428 UINT32 IntelProcessorTrace : 1; 1429 /// 1430 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.). 1431 /// 1432 UINT32 AVX512PF : 1; 1433 /// 1434 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.). 1435 /// 1436 UINT32 AVX512ER : 1; 1437 /// 1438 /// [Bit 28] AVX512CD. 1439 /// 1440 UINT32 AVX512CD : 1; 1441 /// 1442 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) 1443 /// SHA Extensions) if 1. 1444 /// 1445 UINT32 SHA : 1; 1446 /// 1447 /// [Bit 30] AVX512BW. 1448 /// 1449 UINT32 AVX512BW : 1; 1450 /// 1451 /// [Bit 31] AVX512VL. 1452 /// 1453 UINT32 AVX512VL : 1; 1454 } Bits; 1455 /// 1456 /// All bit fields as a 32-bit value 1457 /// 1458 UINT32 Uint32; 1459 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX; 1460 1461 /** 1462 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf 1463 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1464 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1465 **/ 1466 typedef union { 1467 /// 1468 /// Individual bit fields 1469 /// 1470 struct { 1471 /// 1472 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction. 1473 /// (Intel Xeon Phi only.) 1474 /// 1475 UINT32 PREFETCHWT1 : 1; 1476 /// 1477 /// [Bit 1] AVX512_VBMI. 1478 /// 1479 UINT32 AVX512_VBMI : 1; 1480 /// 1481 /// [Bit 2] Supports user-mode instruction prevention if 1. 1482 /// 1483 UINT32 UMIP : 1; 1484 /// 1485 /// [Bit 3] Supports protection keys for user-mode pages if 1. 1486 /// 1487 UINT32 PKU : 1; 1488 /// 1489 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the 1490 /// RDPKRU/WRPKRU instructions). 1491 /// 1492 UINT32 OSPKE : 1; 1493 UINT32 Reserved8 : 8; 1494 /// 1495 /// [Bit 13] If 1, the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, 1496 /// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. 1497 /// 1498 UINT32 TME_EN : 1; 1499 /// 1500 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). 1501 /// 1502 UINT32 AVX512_VPOPCNTDQ : 1; 1503 UINT32 Reserved7 : 1; 1504 /// 1505 /// [Bits 16] Supports 5-level paging if 1. 1506 /// 1507 UINT32 FiveLevelPage : 1; 1508 /// 1509 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions 1510 /// in 64-bit mode. 1511 /// 1512 UINT32 MAWAU : 5; 1513 /// 1514 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1. 1515 /// 1516 UINT32 RDPID : 1; 1517 UINT32 Reserved3 : 7; 1518 /// 1519 /// [Bit 30] Supports SGX Launch Configuration if 1. 1520 /// 1521 UINT32 SGX_LC : 1; 1522 UINT32 Reserved4 : 1; 1523 } Bits; 1524 /// 1525 /// All bit fields as a 32-bit value 1526 /// 1527 UINT32 Uint32; 1528 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX; 1529 1530 /** 1531 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf 1532 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf 1533 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. 1534 **/ 1535 typedef union { 1536 /// 1537 /// Individual bit fields 1538 /// 1539 struct { 1540 /// 1541 /// [Bit 1:0] Reserved. 1542 /// 1543 UINT32 Reserved1 : 2; 1544 /// 1545 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.) 1546 /// 1547 UINT32 AVX512_4VNNIW : 1; 1548 /// 1549 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.) 1550 /// 1551 UINT32 AVX512_4FMAPS : 1; 1552 /// 1553 /// [Bit 14:4] Reserved. 1554 /// 1555 UINT32 Reserved4 : 11; 1556 /// 1557 /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part. 1558 /// 1559 UINT32 Hybrid : 1; 1560 /// 1561 /// [Bit 25:16] Reserved. 1562 /// 1563 UINT32 Reserved5 : 10; 1564 /// 1565 /// [Bit 26] Enumerates support for indirect branch restricted speculation 1566 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors 1567 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD 1568 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and 1569 /// IA32_PRED_CMD[0] (IBPB). 1570 /// 1571 UINT32 EnumeratesSupportForIBRSAndIBPB : 1; 1572 /// 1573 /// [Bit 27] Enumerates support for single thread indirect branch 1574 /// predictors (STIBP). Processors that set this bit support the 1575 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] 1576 /// (STIBP). 1577 /// 1578 UINT32 EnumeratesSupportForSTIBP : 1; 1579 /// 1580 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit 1581 /// support the IA32_FLUSH_CMD MSR. They allow software to set 1582 /// IA32_FLUSH_CMD[0] (L1D_FLUSH). 1583 /// 1584 UINT32 EnumeratesSupportForL1D_FLUSH : 1; 1585 /// 1586 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR. 1587 /// 1588 UINT32 EnumeratesSupportForCapability : 1; 1589 /// 1590 /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR. 1591 /// 1592 UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1; 1593 /// 1594 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD). 1595 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow 1596 /// software to set IA32_SPEC_CTRL[2] (SSBD). 1597 /// 1598 UINT32 EnumeratesSupportForSSBD : 1; 1599 } Bits; 1600 /// 1601 /// All bit fields as a 32-bit value 1602 /// 1603 UINT32 Uint32; 1604 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX; 1605 1606 /** 1607 CPUID Direct Cache Access Information 1608 1609 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09) 1610 1611 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H). 1612 @retval EBX Reserved. 1613 @retval ECX Reserved. 1614 @retval EDX Reserved. 1615 1616 <b>Example usage</b> 1617 @code 1618 UINT32 Eax; 1619 1620 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL); 1621 @endcode 1622 **/ 1623 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09 1624 1625 /** 1626 CPUID Architectural Performance Monitoring 1627 1628 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A) 1629 1630 @retval EAX Architectural Performance Monitoring information described by 1631 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX. 1632 @retval EBX Architectural Performance Monitoring information described by 1633 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX. 1634 @retval ECX Reserved. 1635 @retval EDX Architectural Performance Monitoring information described by 1636 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX. 1637 1638 <b>Example usage</b> 1639 @code 1640 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax; 1641 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx; 1642 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx; 1643 1644 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32); 1645 @endcode 1646 **/ 1647 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A 1648 1649 /** 1650 CPUID Architectural Performance Monitoring EAX for CPUID leaf 1651 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1652 **/ 1653 typedef union { 1654 /// 1655 /// Individual bit fields 1656 /// 1657 struct { 1658 /// 1659 /// [Bit 7:0] Version ID of architectural performance monitoring. 1660 /// 1661 UINT32 ArchPerfMonVerID : 8; 1662 /// 1663 /// [Bits 15:8] Number of general-purpose performance monitoring counter 1664 /// per logical processor. 1665 /// 1666 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous 1667 /// block of MSR address space. Each performance event select register is 1668 /// paired with a corresponding performance counter in the 0C1H address 1669 /// block. 1670 /// 1671 UINT32 PerformanceMonitorCounters : 8; 1672 /// 1673 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter. 1674 /// 1675 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for 1676 /// read operation. On write operations, the lower-order 32 bits of the MSR 1677 /// may be written with any value, and the high-order bits are sign-extended 1678 /// from the value of bit 31. 1679 /// 1680 UINT32 PerformanceMonitorCounterWidth : 8; 1681 /// 1682 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural 1683 /// performance monitoring events. 1684 /// 1685 UINT32 EbxBitVectorLength : 8; 1686 } Bits; 1687 /// 1688 /// All bit fields as a 32-bit value 1689 /// 1690 UINT32 Uint32; 1691 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX; 1692 1693 /** 1694 CPUID Architectural Performance Monitoring EBX for CPUID leaf 1695 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1696 **/ 1697 typedef union { 1698 /// 1699 /// Individual bit fields 1700 /// 1701 struct { 1702 /// 1703 /// [Bit 0] Core cycle event not available if 1. 1704 /// 1705 UINT32 UnhaltedCoreCycles : 1; 1706 /// 1707 /// [Bit 1] Instruction retired event not available if 1. 1708 /// 1709 UINT32 InstructionsRetired : 1; 1710 /// 1711 /// [Bit 2] Reference cycles event not available if 1. 1712 /// 1713 UINT32 UnhaltedReferenceCycles : 1; 1714 /// 1715 /// [Bit 3] Last-level cache reference event not available if 1. 1716 /// 1717 UINT32 LastLevelCacheReferences : 1; 1718 /// 1719 /// [Bit 4] Last-level cache misses event not available if 1. 1720 /// 1721 UINT32 LastLevelCacheMisses : 1; 1722 /// 1723 /// [Bit 5] Branch instruction retired event not available if 1. 1724 /// 1725 UINT32 BranchInstructionsRetired : 1; 1726 /// 1727 /// [Bit 6] Branch mispredict retired event not available if 1. 1728 /// 1729 UINT32 AllBranchMispredictRetired : 1; 1730 UINT32 Reserved : 25; 1731 } Bits; 1732 /// 1733 /// All bit fields as a 32-bit value 1734 /// 1735 UINT32 Uint32; 1736 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX; 1737 1738 /** 1739 CPUID Architectural Performance Monitoring EDX for CPUID leaf 1740 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. 1741 **/ 1742 typedef union { 1743 /// 1744 /// Individual bit fields 1745 /// 1746 struct { 1747 /// 1748 /// [Bits 4:0] Number of fixed-function performance counters 1749 /// (if Version ID > 1). 1750 /// 1751 UINT32 FixedFunctionPerformanceCounters : 5; 1752 /// 1753 /// [Bits 12:5] Bit width of fixed-function performance counters 1754 /// (if Version ID > 1). 1755 /// 1756 UINT32 FixedFunctionPerformanceCounterWidth : 8; 1757 UINT32 Reserved1 : 2; 1758 /// 1759 /// [Bits 15] AnyThread deprecation. 1760 /// 1761 UINT32 AnyThreadDeprecation : 1; 1762 UINT32 Reserved2 : 16; 1763 } Bits; 1764 /// 1765 /// All bit fields as a 32-bit value 1766 /// 1767 UINT32 Uint32; 1768 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX; 1769 1770 /** 1771 CPUID Extended Topology Information 1772 1773 @note 1774 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first 1775 checking for the existence of Leaf 1FH before using leaf 0BH. 1776 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output 1777 of leaf 0BH is always valid and does not vary with input value in ECX. Output 1778 value in ECX[7:0] always equals input value in ECX[7:0]. 1779 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index 1780 enumerates a higher-level topological entity in hierarchical order. 1781 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and 1782 EBX will return 0. 1783 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], 1784 other input values with ECX > n also return 0 in ECX[15:8]. 1785 1786 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B) 1787 @param ECX Level number 1788 1789 @retval EAX Extended topology information described by the type 1790 CPUID_EXTENDED_TOPOLOGY_EAX. 1791 @retval EBX Extended topology information described by the type 1792 CPUID_EXTENDED_TOPOLOGY_EBX. 1793 @retval ECX Extended topology information described by the type 1794 CPUID_EXTENDED_TOPOLOGY_ECX. 1795 @retval EDX x2APIC ID the current logical processor. 1796 1797 <b>Example usage</b> 1798 @code 1799 CPUID_EXTENDED_TOPOLOGY_EAX Eax; 1800 CPUID_EXTENDED_TOPOLOGY_EBX Ebx; 1801 CPUID_EXTENDED_TOPOLOGY_ECX Ecx; 1802 UINT32 Edx; 1803 UINT32 LevelNumber; 1804 1805 LevelNumber = 0; 1806 do { 1807 AsmCpuidEx ( 1808 CPUID_EXTENDED_TOPOLOGY, LevelNumber, 1809 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx 1810 ); 1811 LevelNumber++; 1812 } while (Eax.Bits.ApicIdShift != 0); 1813 @endcode 1814 **/ 1815 #define CPUID_EXTENDED_TOPOLOGY 0x0B 1816 1817 /** 1818 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1819 **/ 1820 typedef union { 1821 /// 1822 /// Individual bit fields 1823 /// 1824 struct { 1825 /// 1826 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique 1827 /// topology ID of the next level type. All logical processors with the 1828 /// same next level ID share current level. 1829 /// 1830 /// @note 1831 /// Software should use this field (EAX[4:0]) to enumerate processor 1832 /// topology of the system. 1833 /// 1834 UINT32 ApicIdShift : 5; 1835 UINT32 Reserved : 27; 1836 } Bits; 1837 /// 1838 /// All bit fields as a 32-bit value 1839 /// 1840 UINT32 Uint32; 1841 } CPUID_EXTENDED_TOPOLOGY_EAX; 1842 1843 /** 1844 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1845 **/ 1846 typedef union { 1847 /// 1848 /// Individual bit fields 1849 /// 1850 struct { 1851 /// 1852 /// [Bits 15:0] Number of logical processors at this level type. The number 1853 /// reflects configuration as shipped by Intel. 1854 /// 1855 /// @note 1856 /// Software must not use EBX[15:0] to enumerate processor topology of the 1857 /// system. This value in this field (EBX[15:0]) is only intended for 1858 /// display/diagnostic purposes. The actual number of logical processors 1859 /// available to BIOS/OS/Applications may be different from the value of 1860 /// EBX[15:0], depending on software and platform hardware configurations. 1861 /// 1862 UINT32 LogicalProcessors : 16; 1863 UINT32 Reserved : 16; 1864 } Bits; 1865 /// 1866 /// All bit fields as a 32-bit value 1867 /// 1868 UINT32 Uint32; 1869 } CPUID_EXTENDED_TOPOLOGY_EBX; 1870 1871 /** 1872 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. 1873 **/ 1874 typedef union { 1875 /// 1876 /// Individual bit fields 1877 /// 1878 struct { 1879 /// 1880 /// [Bits 7:0] Level number. Same value in ECX input. 1881 /// 1882 UINT32 LevelNumber : 8; 1883 /// 1884 /// [Bits 15:8] Level type. 1885 /// 1886 /// @note 1887 /// The value of the "level type" field is not related to level numbers in 1888 /// any way, higher "level type" values do not mean higher levels. 1889 /// 1890 UINT32 LevelType : 8; 1891 UINT32 Reserved : 16; 1892 } Bits; 1893 /// 1894 /// All bit fields as a 32-bit value 1895 /// 1896 UINT32 Uint32; 1897 } CPUID_EXTENDED_TOPOLOGY_ECX; 1898 1899 /// 1900 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType 1901 /// 1902 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00 1903 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01 1904 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02 1905 /// 1906 /// @} 1907 /// 1908 1909 /** 1910 CPUID Extended State Information 1911 1912 @param EAX CPUID_EXTENDED_STATE (0x0D) 1913 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00). 1914 CPUID_EXTENDED_STATE_SUB_LEAF (0x01). 1915 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). 1916 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR. 1917 **/ 1918 #define CPUID_EXTENDED_STATE 0x0D 1919 1920 /** 1921 CPUID Extended State Information Main Leaf 1922 1923 @param EAX CPUID_EXTENDED_STATE (0x0D) 1924 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) 1925 1926 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] 1927 can be set to 1 only if EAX[n] is 1. The format of the extended 1928 state main leaf is described by the type 1929 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX. 1930 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save 1931 area) required by enabled features in XCR0. May be different than 1932 ECX if some features at the end of the XSAVE save area are not 1933 enabled. 1934 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save 1935 area) of the XSAVE/XRSTOR save area required by all supported 1936 features in the processor, i.e., all the valid bit fields in XCR0. 1937 @retval EDX Reports the supported bits of the upper 32 bits of XCR0. 1938 XCR0[n+32] can be set to 1 only if EDX[n] is 1. 1939 1940 <b>Example usage</b> 1941 @code 1942 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; 1943 UINT32 Ebx; 1944 UINT32 Ecx; 1945 UINT32 Edx; 1946 1947 AsmCpuidEx ( 1948 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, 1949 &Eax.Uint32, &Ebx, &Ecx, &Edx 1950 ); 1951 @endcode 1952 **/ 1953 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00 1954 1955 /** 1956 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, 1957 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF. 1958 **/ 1959 typedef union { 1960 /// 1961 /// Individual bit fields 1962 /// 1963 struct { 1964 /// 1965 /// [Bit 0] x87 state. 1966 /// 1967 UINT32 x87 : 1; 1968 /// 1969 /// [Bit 1] SSE state. 1970 /// 1971 UINT32 SSE : 1; 1972 /// 1973 /// [Bit 2] AVX state. 1974 /// 1975 UINT32 AVX : 1; 1976 /// 1977 /// [Bits 4:3] MPX state. 1978 /// 1979 UINT32 MPX : 2; 1980 /// 1981 /// [Bits 7:5] AVX-512 state. 1982 /// 1983 UINT32 AVX_512 : 3; 1984 /// 1985 /// [Bit 8] Used for IA32_XSS. 1986 /// 1987 UINT32 IA32_XSS : 1; 1988 /// 1989 /// [Bit 9] PKRU state. 1990 /// 1991 UINT32 PKRU : 1; 1992 UINT32 Reserved1 : 3; 1993 /// 1994 /// [Bit 13] Used for IA32_XSS, part 2. 1995 /// 1996 UINT32 IA32_XSS_2 : 1; 1997 UINT32 Reserved2 : 18; 1998 } Bits; 1999 /// 2000 /// All bit fields as a 32-bit value 2001 /// 2002 UINT32 Uint32; 2003 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX; 2004 2005 /** 2006 CPUID Extended State Information Sub Leaf 2007 2008 @param EAX CPUID_EXTENDED_STATE (0x0D) 2009 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01) 2010 2011 @retval EAX The format of the extended state sub-leaf is described by the 2012 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX. 2013 @retval EBX The size in bytes of the XSAVE area containing all states 2014 enabled by XCRO | IA32_XSS. 2015 @retval ECX The format of the extended state sub-leaf is described by the 2016 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX. 2017 @retval EDX Reports the supported bits of the upper 32 bits of the 2018 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1. 2019 2020 <b>Example usage</b> 2021 @code 2022 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; 2023 UINT32 Ebx; 2024 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; 2025 UINT32 Edx; 2026 2027 AsmCpuidEx ( 2028 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, 2029 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx 2030 ); 2031 @endcode 2032 **/ 2033 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01 2034 2035 /** 2036 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, 2037 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. 2038 **/ 2039 typedef union { 2040 /// 2041 /// Individual bit fields 2042 /// 2043 struct { 2044 /// 2045 /// [Bit 0] XSAVEOPT is available. 2046 /// 2047 UINT32 XSAVEOPT : 1; 2048 /// 2049 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set. 2050 /// 2051 UINT32 XSAVEC : 1; 2052 /// 2053 /// [Bit 2] Supports XGETBV with ECX = 1 if set. 2054 /// 2055 UINT32 XGETBV : 1; 2056 /// 2057 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set. 2058 /// 2059 UINT32 XSAVES : 1; 2060 UINT32 Reserved : 28; 2061 } Bits; 2062 /// 2063 /// All bit fields as a 32-bit value 2064 /// 2065 UINT32 Uint32; 2066 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX; 2067 2068 /** 2069 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, 2070 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. 2071 **/ 2072 typedef union { 2073 /// 2074 /// Individual bit fields 2075 /// 2076 struct { 2077 /// 2078 /// [Bits 7:0] Used for XCR0. 2079 /// 2080 UINT32 XCR0 : 1; 2081 /// 2082 /// [Bit 8] PT STate. 2083 /// 2084 UINT32 PT : 1; 2085 /// 2086 /// [Bit 9] Used for XCR0. 2087 /// 2088 UINT32 XCR0_1 : 1; 2089 UINT32 Reserved1 : 3; 2090 /// 2091 /// [Bit 13] HWP state. 2092 /// 2093 UINT32 HWPState : 1; 2094 UINT32 Reserved8 : 18; 2095 } Bits; 2096 /// 2097 /// All bit fields as a 32-bit value 2098 /// 2099 UINT32 Uint32; 2100 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX; 2101 2102 /** 2103 CPUID Extended State Information Size and Offset Sub Leaf 2104 2105 @note 2106 Leaf 0DH output depends on the initial value in ECX. 2107 Each sub-leaf index (starting at position 2) is supported if it corresponds to 2108 a supported bit in either the XCR0 register or the IA32_XSS MSR. 2109 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 2110 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 2111 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0 2112 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. 2113 2114 @param EAX CPUID_EXTENDED_STATE (0x0D) 2115 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based 2116 on supported bits in XCR0 or IA32_XSS_MSR. 2117 2118 @retval EAX The size in bytes (from the offset specified in EBX) of the save 2119 area for an extended state feature associated with a valid 2120 sub-leaf index, n. 2121 @retval EBX The offset in bytes of this extended state component's save area 2122 from the beginning of the XSAVE/XRSTOR area. This field reports 2123 0 if the sub-leaf index, n, does not map to a valid bit in the 2124 XCR0 register. 2125 @retval ECX The format of the extended state components's save area as 2126 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX. 2127 This field reports 0 if the sub-leaf index, n, is invalid. 2128 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid; 2129 otherwise it is reserved. 2130 2131 <b>Example usage</b> 2132 @code 2133 UINT32 Eax; 2134 UINT32 Ebx; 2135 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx; 2136 UINT32 Edx; 2137 UINTN SubLeaf; 2138 2139 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { 2140 AsmCpuidEx ( 2141 CPUID_EXTENDED_STATE, SubLeaf, 2142 &Eax, &Ebx, &Ecx.Uint32, &Edx 2143 ); 2144 } 2145 @endcode 2146 **/ 2147 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02 2148 2149 /** 2150 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, 2151 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET. 2152 **/ 2153 typedef union { 2154 /// 2155 /// Individual bit fields 2156 /// 2157 struct { 2158 /// 2159 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is 2160 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported 2161 /// in XCR0. 2162 /// 2163 UINT32 XSS : 1; 2164 /// 2165 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used, 2166 /// this extended state component located on the next 64-byte boundary 2167 /// following the preceding state component (otherwise, it is located 2168 /// immediately following the preceding state component). 2169 /// 2170 UINT32 Compacted : 1; 2171 UINT32 Reserved : 30; 2172 } Bits; 2173 /// 2174 /// All bit fields as a 32-bit value 2175 /// 2176 UINT32 Uint32; 2177 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX; 2178 2179 /** 2180 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information 2181 2182 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2183 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). 2184 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01). 2185 2186 **/ 2187 #define CPUID_INTEL_RDT_MONITORING 0x0F 2188 2189 /** 2190 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information 2191 Enumeration Sub-leaf 2192 2193 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2194 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00) 2195 2196 @retval EAX Reserved. 2197 @retval EBX Maximum range (zero-based) of RMID within this physical 2198 processor of all types. 2199 @retval ECX Reserved. 2200 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by 2201 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX. 2202 2203 <b>Example usage</b> 2204 @code 2205 UINT32 Ebx; 2206 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; 2207 2208 AsmCpuidEx ( 2209 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, 2210 NULL, &Ebx, NULL, &Edx.Uint32 2211 ); 2212 @endcode 2213 **/ 2214 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00 2215 2216 /** 2217 CPUID Intel RDT Monitoring Information EDX for CPUID leaf 2218 #CPUID_INTEL_RDT_MONITORING, sub-leaf 2219 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF. 2220 **/ 2221 typedef union { 2222 /// 2223 /// Individual bit fields 2224 /// 2225 struct { 2226 UINT32 Reserved1 : 1; 2227 /// 2228 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1. 2229 /// 2230 UINT32 L3CacheRDT_M : 1; 2231 UINT32 Reserved2 : 30; 2232 } Bits; 2233 /// 2234 /// All bit fields as a 32-bit value 2235 /// 2236 UINT32 Uint32; 2237 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX; 2238 2239 /** 2240 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf 2241 2242 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) 2243 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01) 2244 2245 @retval EAX Reserved. 2246 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). 2247 @retval ECX Maximum range (zero-based) of RMID of this resource type. 2248 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the 2249 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX. 2250 2251 <b>Example usage</b> 2252 @code 2253 UINT32 Ebx; 2254 UINT32 Ecx; 2255 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; 2256 2257 AsmCpuidEx ( 2258 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, 2259 NULL, &Ebx, &Ecx, &Edx.Uint32 2260 ); 2261 @endcode 2262 **/ 2263 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01 2264 2265 /** 2266 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf 2267 #CPUID_INTEL_RDT_MONITORING, sub-leaf 2268 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF. 2269 **/ 2270 typedef union { 2271 /// 2272 /// Individual bit fields 2273 /// 2274 struct { 2275 /// 2276 /// [Bit 0] Supports L3 occupancy monitoring if 1. 2277 /// 2278 UINT32 L3CacheOccupancyMonitoring : 1; 2279 /// 2280 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1. 2281 /// 2282 UINT32 L3CacheTotalBandwidthMonitoring : 1; 2283 /// 2284 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1. 2285 /// 2286 UINT32 L3CacheLocalBandwidthMonitoring : 1; 2287 UINT32 Reserved : 29; 2288 } Bits; 2289 /// 2290 /// All bit fields as a 32-bit value 2291 /// 2292 UINT32 Uint32; 2293 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX; 2294 2295 /** 2296 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information 2297 2298 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10). 2299 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). 2300 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). 2301 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02). 2302 **/ 2303 #define CPUID_INTEL_RDT_ALLOCATION 0x10 2304 2305 /** 2306 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf 2307 2308 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2309 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). 2310 2311 @retval EAX Reserved. 2312 @retval EBX L3 and L2 Cache Allocation Technology information described by 2313 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX. 2314 @retval ECX Reserved. 2315 @retval EDX Reserved. 2316 2317 <b>Example usage</b> 2318 @code 2319 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; 2320 2321 AsmCpuidEx ( 2322 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, 2323 NULL, &Ebx.Uint32, NULL, NULL 2324 ); 2325 @endcode 2326 **/ 2327 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00 2328 2329 /** 2330 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf 2331 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2332 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF. 2333 **/ 2334 typedef union { 2335 /// 2336 /// Individual bit fields 2337 /// 2338 struct { 2339 UINT32 Reserved1 : 1; 2340 /// 2341 /// [Bit 1] Supports L3 Cache Allocation Technology if 1. 2342 /// 2343 UINT32 L3CacheAllocation : 1; 2344 /// 2345 /// [Bit 2] Supports L2 Cache Allocation Technology if 1. 2346 /// 2347 UINT32 L2CacheAllocation : 1; 2348 /// 2349 /// [Bit 3] Supports Memory Bandwidth Allocation if 1. 2350 /// 2351 UINT32 MemoryBandwidth : 1; 2352 UINT32 Reserved3 : 28; 2353 } Bits; 2354 /// 2355 /// All bit fields as a 32-bit value 2356 /// 2357 UINT32 Uint32; 2358 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX; 2359 2360 /** 2361 L3 Cache Allocation Technology Enumeration Sub-leaf 2362 2363 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2364 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01) 2365 2366 @retval EAX RESID L3 Cache Allocation Technology information described by 2367 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX. 2368 @retval EBX Bit-granular map of isolation/contention of allocation units. 2369 @retval ECX RESID L3 Cache Allocation Technology information described by 2370 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX. 2371 @retval EDX RESID L3 Cache Allocation Technology information described by 2372 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX. 2373 2374 <b>Example usage</b> 2375 @code 2376 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; 2377 UINT32 Ebx; 2378 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; 2379 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; 2380 2381 AsmCpuidEx ( 2382 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, 2383 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 2384 ); 2385 @endcode 2386 **/ 2387 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 2388 2389 /** 2390 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf 2391 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2392 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2393 **/ 2394 typedef union { 2395 /// 2396 /// Individual bit fields 2397 /// 2398 struct { 2399 /// 2400 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID 2401 /// using minus-one notation. 2402 /// 2403 UINT32 CapacityLength : 5; 2404 UINT32 Reserved : 27; 2405 } Bits; 2406 /// 2407 /// All bit fields as a 32-bit value 2408 /// 2409 UINT32 Uint32; 2410 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX; 2411 2412 /** 2413 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf 2414 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2415 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2416 **/ 2417 typedef union { 2418 /// 2419 /// Individual bit fields 2420 /// 2421 struct { 2422 UINT32 Reserved3 : 2; 2423 /// 2424 /// [Bit 2] Code and Data Prioritization Technology supported if 1. 2425 /// 2426 UINT32 CodeDataPrioritization : 1; 2427 UINT32 Reserved2 : 29; 2428 } Bits; 2429 /// 2430 /// All bit fields as a 32-bit value 2431 /// 2432 UINT32 Uint32; 2433 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX; 2434 2435 /** 2436 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf 2437 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2438 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. 2439 **/ 2440 typedef union { 2441 /// 2442 /// Individual bit fields 2443 /// 2444 struct { 2445 /// 2446 /// [Bits 15:0] Highest COS number supported for this ResID. 2447 /// 2448 UINT32 HighestCosNumber : 16; 2449 UINT32 Reserved : 16; 2450 } Bits; 2451 /// 2452 /// All bit fields as a 32-bit value 2453 /// 2454 UINT32 Uint32; 2455 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX; 2456 2457 /** 2458 L2 Cache Allocation Technology Enumeration Sub-leaf 2459 2460 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2461 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02) 2462 2463 @retval EAX RESID L2 Cache Allocation Technology information described by 2464 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX. 2465 @retval EBX Bit-granular map of isolation/contention of allocation units. 2466 @retval ECX Reserved. 2467 @retval EDX RESID L2 Cache Allocation Technology information described by 2468 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX. 2469 2470 <b>Example usage</b> 2471 @code 2472 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; 2473 UINT32 Ebx; 2474 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; 2475 2476 AsmCpuidEx ( 2477 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, 2478 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2479 ); 2480 @endcode 2481 **/ 2482 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02 2483 2484 /** 2485 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf 2486 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2487 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. 2488 **/ 2489 typedef union { 2490 /// 2491 /// Individual bit fields 2492 /// 2493 struct { 2494 /// 2495 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID 2496 /// using minus-one notation. 2497 /// 2498 UINT32 CapacityLength : 5; 2499 UINT32 Reserved : 27; 2500 } Bits; 2501 /// 2502 /// All bit fields as a 32-bit value 2503 /// 2504 UINT32 Uint32; 2505 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX; 2506 2507 /** 2508 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf 2509 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2510 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. 2511 **/ 2512 typedef union { 2513 /// 2514 /// Individual bit fields 2515 /// 2516 struct { 2517 /// 2518 /// [Bits 15:0] Highest COS number supported for this ResID. 2519 /// 2520 UINT32 HighestCosNumber : 16; 2521 UINT32 Reserved : 16; 2522 } Bits; 2523 /// 2524 /// All bit fields as a 32-bit value 2525 /// 2526 UINT32 Uint32; 2527 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX; 2528 2529 /** 2530 Memory Bandwidth Allocation Enumeration Sub-leaf 2531 2532 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) 2533 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03) 2534 2535 @retval EAX RESID memory bandwidth Allocation Technology information 2536 described by the type 2537 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX. 2538 @retval EBX Reserved. 2539 @retval ECX RESID memory bandwidth Allocation Technology information 2540 described by the type 2541 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX. 2542 @retval EDX RESID memory bandwidth Allocation Technology information 2543 described by the type 2544 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX. 2545 2546 <b>Example usage</b> 2547 @code 2548 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax; 2549 UINT32 Ebx; 2550 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx; 2551 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; 2552 2553 2554 AsmCpuidEx ( 2555 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, 2556 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2557 ); 2558 @endcode 2559 **/ 2560 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 2561 2562 /** 2563 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf 2564 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2565 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2566 **/ 2567 typedef union { 2568 /// 2569 /// Individual bit fields 2570 /// 2571 struct { 2572 /// 2573 /// [Bits 11:0] Reports the maximum MBA throttling value supported for 2574 /// the corresponding ResID using minus-one notation. 2575 /// 2576 UINT32 MaximumMBAThrottling : 12; 2577 UINT32 Reserved : 20; 2578 } Bits; 2579 /// 2580 /// All bit fields as a 32-bit value 2581 /// 2582 UINT32 Uint32; 2583 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX; 2584 2585 /** 2586 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf 2587 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2588 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2589 **/ 2590 typedef union { 2591 /// 2592 /// Individual bit fields 2593 /// 2594 struct { 2595 /// 2596 /// [Bits 1:0] Reserved. 2597 /// 2598 UINT32 Reserved1 : 2; 2599 /// 2600 /// [Bits 3] Reports whether the response of the delay values is linear. 2601 /// 2602 UINT32 Liner : 1; 2603 UINT32 Reserved2 : 29; 2604 } Bits; 2605 /// 2606 /// All bit fields as a 32-bit value 2607 /// 2608 UINT32 Uint32; 2609 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX; 2610 2611 /** 2612 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf 2613 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf 2614 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. 2615 **/ 2616 typedef union { 2617 /// 2618 /// Individual bit fields 2619 /// 2620 struct { 2621 /// 2622 /// [Bits 15:0] Highest COS number supported for this ResID. 2623 /// 2624 UINT32 HighestCosNumber : 16; 2625 UINT32 Reserved : 16; 2626 } Bits; 2627 /// 2628 /// All bit fields as a 32-bit value 2629 /// 2630 UINT32 Uint32; 2631 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX; 2632 2633 /** 2634 Intel SGX resource capability and configuration. 2635 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves". 2636 2637 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying 2638 CPUID with EAX=12H on Intel SGX resource capability and configuration. 2639 2640 @param EAX CPUID_INTEL_SGX (0x12) 2641 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00). 2642 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01). 2643 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02). 2644 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0]) 2645 until the sub-leaf type is invalid. 2646 2647 **/ 2648 #define CPUID_INTEL_SGX 0x12 2649 2650 /** 2651 Sub-Leaf 0 Enumeration of Intel SGX Capabilities. 2652 Enumerates Intel SGX capability, including enclave instruction opcode support. 2653 2654 @param EAX CPUID_INTEL_SGX (0x12) 2655 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00) 2656 2657 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is 2658 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX. 2659 @retval EBX MISCSELECT: Reports the bit vector of supported extended features 2660 that can be written to the MISC region of the SSA. 2661 @retval ECX Reserved. 2662 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is 2663 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX. 2664 2665 <b>Example usage</b> 2666 @code 2667 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax; 2668 UINT32 Ebx; 2669 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; 2670 2671 AsmCpuidEx ( 2672 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, 2673 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 2674 ); 2675 @endcode 2676 **/ 2677 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00 2678 2679 /** 2680 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX, 2681 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. 2682 **/ 2683 typedef union { 2684 /// 2685 /// Individual bit fields 2686 /// 2687 struct { 2688 /// 2689 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported. 2690 /// 2691 UINT32 SGX1 : 1; 2692 /// 2693 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported. 2694 /// 2695 UINT32 SGX2 : 1; 2696 UINT32 Reserved1 : 3; 2697 /// 2698 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves 2699 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT. 2700 /// 2701 UINT32 ENCLV : 1; 2702 /// 2703 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC, 2704 /// ERDINFO, ELDBC, and ELDUC. 2705 /// 2706 UINT32 ENCLS : 1; 2707 UINT32 Reserved2 : 25; 2708 } Bits; 2709 /// 2710 /// All bit fields as a 32-bit value 2711 /// 2712 UINT32 Uint32; 2713 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX; 2714 2715 /** 2716 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX, 2717 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. 2718 **/ 2719 typedef union { 2720 /// 2721 /// Individual bit fields 2722 /// 2723 struct { 2724 /// 2725 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes 2726 /// when not in 64-bit mode. 2727 /// 2728 UINT32 MaxEnclaveSize_Not64 : 8; 2729 /// 2730 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes 2731 /// when operating in 64-bit mode. 2732 /// 2733 UINT32 MaxEnclaveSize_64 : 8; 2734 UINT32 Reserved : 16; 2735 } Bits; 2736 /// 2737 /// All bit fields as a 32-bit value 2738 /// 2739 UINT32 Uint32; 2740 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX; 2741 2742 /** 2743 Sub-Leaf 1 Enumeration of Intel SGX Capabilities. 2744 Enumerates Intel SGX capability of processor state configuration and enclave 2745 configuration in the SECS structure. 2746 2747 @param EAX CPUID_INTEL_SGX (0x12) 2748 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01) 2749 2750 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can 2751 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE 2752 only if EAX[n] is 1, where n < 32. 2753 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can 2754 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE 2755 only if EBX[n] is 1, where n < 32. 2756 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can 2757 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE 2758 only if ECX[n] is 1, where n < 32. 2759 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can 2760 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE 2761 only if EDX[n] is 1, where n < 32. 2762 2763 <b>Example usage</b> 2764 @code 2765 UINT32 Eax; 2766 UINT32 Ebx; 2767 UINT32 Ecx; 2768 UINT32 Edx; 2769 2770 AsmCpuidEx ( 2771 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, 2772 &Eax, &Ebx, &Ecx, &Edx 2773 ); 2774 @endcode 2775 **/ 2776 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01 2777 2778 /** 2779 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources. 2780 Enumerates available EPC resources. 2781 2782 @param EAX CPUID_INTEL_SGX (0x12) 2783 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02) 2784 2785 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2786 Resources is described by the type 2787 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX. 2788 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2789 Resources is described by the type 2790 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX. 2791 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2792 Resources is described by the type 2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX. 2794 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX 2795 Resources is described by the type 2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX. 2797 2798 <b>Example usage</b> 2799 @code 2800 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax; 2801 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx; 2802 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx; 2803 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx; 2804 2805 AsmCpuidEx ( 2806 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF, 2807 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 2808 ); 2809 @endcode 2810 **/ 2811 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02 2812 2813 /** 2814 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID 2815 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2816 **/ 2817 typedef union { 2818 /// 2819 /// Individual bit fields 2820 /// 2821 struct { 2822 /// 2823 /// [Bit 3:0] Sub-leaf-type encoding. 2824 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0. 2825 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC) 2826 /// in EBX:EAX and EDX:ECX. 2827 /// All other encoding are reserved. 2828 /// 2829 UINT32 SubLeafType : 4; 2830 UINT32 Reserved : 8; 2831 /// 2832 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of 2833 /// the base of the EPC section. 2834 /// 2835 UINT32 LowAddressOfEpcSection : 20; 2836 } Bits; 2837 /// 2838 /// All bit fields as a 32-bit value 2839 /// 2840 UINT32 Uint32; 2841 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX; 2842 2843 /** 2844 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID 2845 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2846 **/ 2847 typedef union { 2848 /// 2849 /// Individual bit fields 2850 /// 2851 struct { 2852 /// 2853 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of 2854 /// the base of the EPC section. 2855 /// 2856 UINT32 HighAddressOfEpcSection : 20; 2857 UINT32 Reserved : 12; 2858 } Bits; 2859 /// 2860 /// All bit fields as a 32-bit value 2861 /// 2862 UINT32 Uint32; 2863 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX; 2864 2865 /** 2866 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID 2867 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2868 **/ 2869 typedef union { 2870 /// 2871 /// Individual bit fields 2872 /// 2873 struct { 2874 /// 2875 /// [Bit 3:0] The EPC section encoding. 2876 /// 0000b: Not valid. 2877 /// 0001b: The EPC section is confidentiality, integrity and replay protected. 2878 /// All other encoding are reserved. 2879 /// 2880 UINT32 EpcSection : 4; 2881 UINT32 Reserved : 8; 2882 /// 2883 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the 2884 /// corresponding EPC section within the Processor Reserved Memory. 2885 /// 2886 UINT32 LowSizeOfEpcSection : 20; 2887 } Bits; 2888 /// 2889 /// All bit fields as a 32-bit value 2890 /// 2891 UINT32 Uint32; 2892 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX; 2893 2894 /** 2895 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID 2896 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. 2897 **/ 2898 typedef union { 2899 /// 2900 /// Individual bit fields 2901 /// 2902 struct { 2903 /// 2904 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the 2905 /// corresponding EPC section within the Processor Reserved Memory. 2906 /// 2907 UINT32 HighSizeOfEpcSection : 20; 2908 UINT32 Reserved : 12; 2909 } Bits; 2910 /// 2911 /// All bit fields as a 32-bit value 2912 /// 2913 UINT32 Uint32; 2914 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX; 2915 2916 /** 2917 CPUID Intel Processor Trace Information 2918 2919 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14) 2920 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00). 2921 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01). 2922 2923 **/ 2924 #define CPUID_INTEL_PROCESSOR_TRACE 0x14 2925 2926 /** 2927 CPUID Intel Processor Trace Information Main Leaf 2928 2929 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) 2930 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00) 2931 2932 @retval EAX Reports the maximum sub-leaf supported in leaf 14H. 2933 @retval EBX Returns Intel processor trace information described by the 2934 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX. 2935 @retval ECX Returns Intel processor trace information described by the 2936 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX. 2937 @retval EDX Reserved. 2938 2939 <b>Example usage</b> 2940 @code 2941 UINT32 Eax; 2942 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx; 2943 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; 2944 2945 AsmCpuidEx ( 2946 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, 2947 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL 2948 ); 2949 @endcode 2950 **/ 2951 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00 2952 2953 /** 2954 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 2955 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. 2956 **/ 2957 typedef union { 2958 /// 2959 /// Individual bit fields 2960 /// 2961 struct { 2962 /// 2963 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, 2964 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed. 2965 /// 2966 UINT32 Cr3Filter : 1; 2967 /// 2968 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate 2969 /// Mode. 2970 /// 2971 UINT32 ConfigurablePsb : 1; 2972 /// 2973 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, 2974 /// and preservation of Intel PT MSRs across warm reset. 2975 /// 2976 UINT32 IpTraceStopFiltering : 1; 2977 /// 2978 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of 2979 /// COFI-based packets. 2980 /// 2981 UINT32 Mtc : 1; 2982 /// 2983 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set 2984 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE 2985 /// can generate packets. 2986 /// 2987 UINT32 PTWrite : 1; 2988 /// 2989 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set 2990 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet 2991 /// generation. 2992 /// 2993 UINT32 PowerEventTrace : 1; 2994 UINT32 Reserved : 26; 2995 } Bits; 2996 /// 2997 /// All bit fields as a 32-bit value 2998 /// 2999 UINT32 Uint32; 3000 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX; 3001 3002 /** 3003 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3004 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. 3005 **/ 3006 typedef union { 3007 /// 3008 /// Individual bit fields 3009 /// 3010 struct { 3011 /// 3012 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence 3013 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and 3014 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed. 3015 /// 3016 UINT32 RTIT : 1; 3017 /// 3018 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to 3019 /// the maximum allowed by the MaskOrTableOffset field of 3020 /// IA32_RTIT_OUTPUT_MASK_PTRS. 3021 /// 3022 UINT32 ToPA : 1; 3023 /// 3024 /// [Bit 2] If 1, indicates support of Single-Range Output scheme. 3025 /// 3026 UINT32 SingleRangeOutput : 1; 3027 /// 3028 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem. 3029 /// 3030 UINT32 TraceTransportSubsystem : 1; 3031 UINT32 Reserved : 27; 3032 /// 3033 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP 3034 /// values, which include the CS base component. 3035 /// 3036 UINT32 LIP : 1; 3037 } Bits; 3038 /// 3039 /// All bit fields as a 32-bit value 3040 /// 3041 UINT32 Uint32; 3042 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX; 3043 3044 /** 3045 CPUID Intel Processor Trace Information Sub-leaf 3046 3047 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) 3048 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01) 3049 3050 @retval EAX Returns Intel processor trace information described by the 3051 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX. 3052 @retval EBX Returns Intel processor trace information described by the 3053 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX. 3054 @retval ECX Reserved. 3055 @retval EDX Reserved. 3056 3057 <b>Example usage</b> 3058 @code 3059 UINT32 MaximumSubLeaf; 3060 UINT32 SubLeaf; 3061 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax; 3062 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx; 3063 3064 AsmCpuidEx ( 3065 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, 3066 &MaximumSubLeaf, NULL, NULL, NULL 3067 ); 3068 3069 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { 3070 AsmCpuidEx ( 3071 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, 3072 &Eax.Uint32, &Ebx.Uint32, NULL, NULL 3073 ); 3074 } 3075 @endcode 3076 **/ 3077 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01 3078 3079 /** 3080 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3081 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. 3082 **/ 3083 typedef union { 3084 /// 3085 /// Individual bit fields 3086 /// 3087 struct { 3088 /// 3089 /// [Bits 2:0] Number of configurable Address Ranges for filtering. 3090 /// 3091 UINT32 ConfigurableAddressRanges : 3; 3092 UINT32 Reserved : 13; 3093 /// 3094 /// [Bits 31:16] Bitmap of supported MTC period encodings 3095 /// 3096 UINT32 MtcPeriodEncodings : 16; 3097 } Bits; 3098 /// 3099 /// All bit fields as a 32-bit value 3100 /// 3101 UINT32 Uint32; 3102 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX; 3103 3104 /** 3105 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, 3106 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. 3107 **/ 3108 typedef union { 3109 /// 3110 /// Individual bit fields 3111 /// 3112 struct { 3113 /// 3114 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings. 3115 /// 3116 UINT32 CycleThresholdEncodings : 16; 3117 /// 3118 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings. 3119 /// 3120 UINT32 PsbFrequencyEncodings : 16; 3121 } Bits; 3122 /// 3123 /// All bit fields as a 32-bit value 3124 /// 3125 UINT32 Uint32; 3126 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX; 3127 3128 /** 3129 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information 3130 3131 @note 3132 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. 3133 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core 3134 crystal clock frequency. 3135 If ECX is 0, the nominal core crystal clock frequency is not enumerated. 3136 "TSC frequency" = "core crystal clock frequency" * EBX/EAX. 3137 The core crystal clock may differ from the reference clock, bus clock, or core 3138 clock frequencies. 3139 3140 @param EAX CPUID_TIME_STAMP_COUNTER (0x15) 3141 3142 @retval EAX An unsigned integer which is the denominator of the 3143 TSC/"core crystal clock" ratio 3144 @retval EBX An unsigned integer which is the numerator of the 3145 TSC/"core crystal clock" ratio. 3146 @retval ECX An unsigned integer which is the nominal frequency 3147 of the core crystal clock in Hz. 3148 @retval EDX Reserved. 3149 3150 <b>Example usage</b> 3151 @code 3152 UINT32 Eax; 3153 UINT32 Ebx; 3154 UINT32 Ecx; 3155 3156 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); 3157 @endcode 3158 **/ 3159 #define CPUID_TIME_STAMP_COUNTER 0x15 3160 3161 /** 3162 CPUID Processor Frequency Information 3163 3164 @note 3165 Data is returned from this interface in accordance with the processor's 3166 specification and does not reflect actual values. Suitable use of this data 3167 includes the display of processor information in like manner to the processor 3168 brand string and for determining the appropriate range to use when displaying 3169 processor information e.g. frequency history graphs. The returned information 3170 should not be used for any other purpose as the returned information does not 3171 accurately correlate to information / counters returned by other processor 3172 interfaces. While a processor may support the Processor Frequency Information 3173 leaf, fields that return a value of zero are not supported. 3174 3175 @param EAX CPUID_TIME_STAMP_COUNTER (0x16) 3176 3177 @retval EAX Returns processor base frequency information described by the 3178 type CPUID_PROCESSOR_FREQUENCY_EAX. 3179 @retval EBX Returns maximum frequency information described by the type 3180 CPUID_PROCESSOR_FREQUENCY_EBX. 3181 @retval ECX Returns bus frequency information described by the type 3182 CPUID_PROCESSOR_FREQUENCY_ECX. 3183 @retval EDX Reserved. 3184 3185 <b>Example usage</b> 3186 @code 3187 CPUID_PROCESSOR_FREQUENCY_EAX Eax; 3188 CPUID_PROCESSOR_FREQUENCY_EBX Ebx; 3189 CPUID_PROCESSOR_FREQUENCY_ECX Ecx; 3190 3191 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); 3192 @endcode 3193 **/ 3194 #define CPUID_PROCESSOR_FREQUENCY 0x16 3195 3196 /** 3197 CPUID Processor Frequency Information EAX for CPUID leaf 3198 #CPUID_PROCESSOR_FREQUENCY. 3199 **/ 3200 typedef union { 3201 /// 3202 /// Individual bit fields 3203 /// 3204 struct { 3205 /// 3206 /// [Bits 15:0] Processor Base Frequency (in MHz). 3207 /// 3208 UINT32 ProcessorBaseFrequency : 16; 3209 UINT32 Reserved : 16; 3210 } Bits; 3211 /// 3212 /// All bit fields as a 32-bit value 3213 /// 3214 UINT32 Uint32; 3215 } CPUID_PROCESSOR_FREQUENCY_EAX; 3216 3217 /** 3218 CPUID Processor Frequency Information EBX for CPUID leaf 3219 #CPUID_PROCESSOR_FREQUENCY. 3220 **/ 3221 typedef union { 3222 /// 3223 /// Individual bit fields 3224 /// 3225 struct { 3226 /// 3227 /// [Bits 15:0] Maximum Frequency (in MHz). 3228 /// 3229 UINT32 MaximumFrequency : 16; 3230 UINT32 Reserved : 16; 3231 } Bits; 3232 /// 3233 /// All bit fields as a 32-bit value 3234 /// 3235 UINT32 Uint32; 3236 } CPUID_PROCESSOR_FREQUENCY_EBX; 3237 3238 /** 3239 CPUID Processor Frequency Information ECX for CPUID leaf 3240 #CPUID_PROCESSOR_FREQUENCY. 3241 **/ 3242 typedef union { 3243 /// 3244 /// Individual bit fields 3245 /// 3246 struct { 3247 /// 3248 /// [Bits 15:0] Bus (Reference) Frequency (in MHz). 3249 /// 3250 UINT32 BusFrequency : 16; 3251 UINT32 Reserved : 16; 3252 } Bits; 3253 /// 3254 /// All bit fields as a 32-bit value 3255 /// 3256 UINT32 Uint32; 3257 } CPUID_PROCESSOR_FREQUENCY_ECX; 3258 3259 /** 3260 CPUID SoC Vendor Information 3261 3262 @param EAX CPUID_SOC_VENDOR (0x17) 3263 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) 3264 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) 3265 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02) 3266 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03) 3267 3268 @note 3269 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String 3270 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC 3271 Vendor Brand String is constructed by concatenating in ascending order of 3272 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3. 3273 3274 **/ 3275 #define CPUID_SOC_VENDOR 0x17 3276 3277 /** 3278 CPUID SoC Vendor Information 3279 3280 @param EAX CPUID_SOC_VENDOR (0x17) 3281 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) 3282 3283 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported 3284 sub-leaf in leaf 17H. 3285 @retval EBX Returns SoC Vendor information described by the type 3286 CPUID_SOC_VENDOR_MAIN_LEAF_EBX. 3287 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC 3288 projects. 3289 @retval EDX Stepping ID. A unique number within an SOC project that an SOC 3290 vendor assigns. 3291 3292 <b>Example usage</b> 3293 @code 3294 UINT32 Eax; 3295 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx; 3296 UINT32 Ecx; 3297 UINT32 Edx; 3298 3299 AsmCpuidEx ( 3300 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, 3301 &Eax, &Ebx.Uint32, &Ecx, &Edx 3302 ); 3303 @endcode 3304 **/ 3305 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00 3306 3307 /** 3308 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf 3309 #CPUID_SOC_VENDOR_MAIN_LEAF. 3310 **/ 3311 typedef union { 3312 /// 3313 /// Individual bit fields 3314 /// 3315 struct { 3316 /// 3317 /// [Bits 15:0] SOC Vendor ID. 3318 /// 3319 UINT32 SocVendorId : 16; 3320 /// 3321 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry 3322 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is 3323 /// assigned by Intel. 3324 /// 3325 UINT32 IsVendorScheme : 1; 3326 UINT32 Reserved : 15; 3327 } Bits; 3328 /// 3329 /// All bit fields as a 32-bit value 3330 /// 3331 UINT32 Uint32; 3332 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX; 3333 3334 /** 3335 CPUID SoC Vendor Information 3336 3337 @param EAX CPUID_SOC_VENDOR (0x17) 3338 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) 3339 3340 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3341 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3342 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3343 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3344 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3345 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3346 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3347 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3348 3349 <b>Example usage</b> 3350 @code 3351 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3352 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3353 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3354 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3355 3356 AsmCpuidEx ( 3357 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, 3358 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3359 ); 3360 @endcode 3361 **/ 3362 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01 3363 3364 /** 3365 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1, 3366 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3. 3367 **/ 3368 typedef union { 3369 /// 3370 /// 4 UTF-8 characters of Soc Vendor Brand String 3371 /// 3372 CHAR8 BrandString[4]; 3373 /// 3374 /// All fields as a 32-bit value 3375 /// 3376 UINT32 Uint32; 3377 } CPUID_SOC_VENDOR_BRAND_STRING_DATA; 3378 3379 /** 3380 CPUID SoC Vendor Information 3381 3382 @param EAX CPUID_SOC_VENDOR (0x17) 3383 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02) 3384 3385 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3386 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3387 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3388 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3389 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3390 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3391 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3392 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3393 3394 <b>Example usage</b> 3395 @code 3396 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3397 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3398 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3399 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3400 3401 AsmCpuidEx ( 3402 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, 3403 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3404 ); 3405 @endcode 3406 **/ 3407 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02 3408 3409 /** 3410 CPUID SoC Vendor Information 3411 3412 @param EAX CPUID_SOC_VENDOR (0x17) 3413 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03) 3414 3415 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type 3416 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3417 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type 3418 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3419 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type 3420 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3421 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type 3422 CPUID_SOC_VENDOR_BRAND_STRING_DATA. 3423 3424 <b>Example usage</b> 3425 @code 3426 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; 3427 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; 3428 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; 3429 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; 3430 3431 AsmCpuidEx ( 3432 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, 3433 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 3434 ); 3435 @endcode 3436 **/ 3437 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03 3438 3439 /** 3440 CPUID Deterministic Address Translation Parameters 3441 3442 @note 3443 Each sub-leaf enumerates a different address translation structure. 3444 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf 3445 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A 3446 sub-leaf index is also invalid if EDX[4:0] returns 0. 3447 Valid sub-leaves do not need to be contiguous or in any particular order. A 3448 valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or 3449 than a valid sub-leaf of a higher or lower-level structure. 3450 * Some unified TLBs will allow a single TLB entry to satisfy data read/write 3451 and instruction fetches. Others will require separate entries (e.g., one 3452 loaded on data read/write and another loaded on an instruction fetch). 3453 Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual 3454 for details of a particular product. 3455 ** Add one to the return value to get the result. 3456 3457 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) 3458 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) 3459 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*) 3460 3461 **/ 3462 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 3463 3464 /** 3465 CPUID Deterministic Address Translation Parameters 3466 3467 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) 3468 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) 3469 3470 @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H. 3471 @retval EBX Returns Deterministic Address Translation Parameters described by 3472 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX. 3473 @retval ECX Number of Sets. 3474 @retval EDX Returns Deterministic Address Translation Parameters described by 3475 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX. 3476 3477 <b>Example usage</b> 3478 @code 3479 UINT32 Eax; 3480 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx; 3481 UINT32 Ecx; 3482 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx; 3483 3484 AsmCpuidEx ( 3485 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, 3486 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, 3487 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 3488 ); 3489 @endcode 3490 **/ 3491 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00 3492 3493 /** 3494 CPUID Deterministic Address Translation Parameters EBX for CPUID leafs. 3495 **/ 3496 typedef union { 3497 /// 3498 /// Individual bit fields 3499 /// 3500 struct { 3501 /// 3502 /// [Bits 0] 4K page size entries supported by this structure. 3503 /// 3504 UINT32 Page4K : 1; 3505 /// 3506 /// [Bits 1] 2MB page size entries supported by this structure. 3507 /// 3508 UINT32 Page2M : 1; 3509 /// 3510 /// [Bits 2] 4MB page size entries supported by this structure. 3511 /// 3512 UINT32 Page4M : 1; 3513 /// 3514 /// [Bits 3] 1 GB page size entries supported by this structure. 3515 /// 3516 UINT32 Page1G : 1; 3517 /// 3518 /// [Bits 7:4] Reserved. 3519 /// 3520 UINT32 Reserved1 : 4; 3521 /// 3522 /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical 3523 /// processors sharing this structure) 3524 /// 3525 UINT32 Partitioning : 3; 3526 /// 3527 /// [Bits 15:11] Reserved. 3528 /// 3529 UINT32 Reserved2 : 5; 3530 /// 3531 /// [Bits 31:16] W = Ways of associativity. 3532 /// 3533 UINT32 Way : 16; 3534 } Bits; 3535 /// 3536 /// All bit fields as a 32-bit value 3537 /// 3538 UINT32 Uint32; 3539 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX; 3540 3541 /** 3542 CPUID Deterministic Address Translation Parameters EDX for CPUID leafs. 3543 **/ 3544 typedef union { 3545 /// 3546 /// Individual bit fields 3547 /// 3548 struct { 3549 /// 3550 /// [Bits 4:0] Translation cache type field. 3551 /// 3552 UINT32 TranslationCacheType : 5; 3553 /// 3554 /// [Bits 7:5] Translation cache level (starts at 1). 3555 /// 3556 UINT32 TranslationCacheLevel : 3; 3557 /// 3558 /// [Bits 8] Fully associative structure. 3559 /// 3560 UINT32 FullyAssociative : 1; 3561 /// 3562 /// [Bits 13:9] Reserved. 3563 /// 3564 UINT32 Reserved1 : 5; 3565 /// 3566 /// [Bits 25:14] Maximum number of addressable IDs for logical 3567 /// processors sharing this translation cache. 3568 /// 3569 UINT32 MaximumNum : 12; 3570 /// 3571 /// [Bits 31:26] Reserved. 3572 /// 3573 UINT32 Reserved2 : 6; 3574 } Bits; 3575 /// 3576 /// All bit fields as a 32-bit value 3577 /// 3578 UINT32 Uint32; 3579 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX; 3580 3581 /// 3582 /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType 3583 /// 3584 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00 3585 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01 3586 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02 3587 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03 3588 /// 3589 /// @} 3590 /// 3591 3592 /** 3593 CPUID Hybrid Information Enumeration Leaf 3594 3595 @param EAX CPUID_HYBRID_INFORMATION (0x1A) 3596 @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00). 3597 3598 @retval EAX Enumerates the native model ID and core type described 3599 by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX 3600 @retval EBX Reserved. 3601 @retval ECX Reserved. 3602 @retval EDX Reserved. 3603 3604 <b>Example usage</b> 3605 @code 3606 CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax; 3607 3608 AsmCpuidEx ( 3609 CPUID_HYBRID_INFORMATION, 3610 CPUID_HYBRID_INFORMATION_MAIN_LEAF, 3611 &Eax, NULL, NULL, NULL 3612 ); 3613 @endcode 3614 3615 **/ 3616 #define CPUID_HYBRID_INFORMATION 0x1A 3617 3618 /// 3619 /// CPUID Hybrid Information Enumeration main leaf 3620 /// 3621 #define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00 3622 3623 /** 3624 CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION, 3625 main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF. 3626 **/ 3627 typedef union { 3628 /// 3629 /// Individual bit fields 3630 /// 3631 struct { 3632 /// 3633 /// [Bit 23:0] Native model ID of the core. 3634 /// 3635 /// The core-type and native mode ID can be used to uniquely identify 3636 /// the microarchitecture of the core.This native model ID is not unique 3637 /// across core types, and not related to the model ID reported in CPUID 3638 /// leaf 01H, and does not identify the SOC. 3639 /// 3640 UINT32 NativeModelId : 24; 3641 /// 3642 /// [Bit 31:24] Core type 3643 /// 3644 UINT32 CoreType : 8; 3645 } Bits; 3646 /// 3647 /// All bit fields as a 32-bit value 3648 /// 3649 UINT32 Uint32; 3650 } CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX; 3651 3652 /// 3653 /// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType 3654 /// 3655 #define CPUID_CORE_TYPE_INTEL_ATOM 0x20 3656 #define CPUID_CORE_TYPE_INTEL_CORE 0x40 3657 /// 3658 /// @} 3659 /// 3660 3661 /** 3662 CPUID V2 Extended Topology Enumeration Leaf 3663 3664 @note 3665 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking 3666 for the existence of Leaf 1FH and using this if available. 3667 Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf 3668 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] 3669 always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each 3670 subsequent higher sub-leaf index enumerates a higher-level topological entity in 3671 hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; 3672 EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of 3673 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8]. 3674 3675 Software should use this field (EAX[4:0]) to enumerate processor topology of the system. 3676 Software must not use EBX[15:0] to enumerate processor topology of the system. This value 3677 in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual 3678 number of logical processors available to BIOS/OS/Applications may be different from the 3679 value of EBX[15:0], depending on software and platform hardware configurations. 3680 3681 @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F) 3682 @param ECX Level number 3683 3684 **/ 3685 #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F 3686 3687 /// 3688 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType 3689 /// The value of the "level type" field is not related to level numbers in 3690 /// any way, higher "level type" values do not mean higher levels. 3691 /// 3692 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03 3693 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04 3694 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05 3695 /// 3696 /// @} 3697 /// 3698 3699 /** 3700 CPUID Guest TD Run Time Environment Enumeration Leaf 3701 3702 @note 3703 Guest software can be designed to run either as a TD, as a legacy virtual machine, 3704 or directly on the CPU, based on enumeration of its run-time environment. 3705 CPUID leaf 21H emulation is done by the Intel TDX module. Sub-leaf 0 returns the values 3706 shown below. Other sub-leaves return 0 in EAX/EBX/ECX/EDX. 3707 EAX: 0x00000000 3708 EBX: 0x65746E49 "Inte" 3709 ECX: 0x20202020 " " 3710 EDX: 0x5844546C "lTDX" 3711 3712 @param EAX CPUID_GUESTTD_RUNTIME_ENVIRONMENT (0x21) 3713 @param ECX Level number 3714 3715 **/ 3716 #define CPUID_GUESTTD_RUNTIME_ENVIRONMENT 0x21 3717 3718 /// 3719 /// @{ CPUID Guest TD signature values returned by Intel processors 3720 /// 3721 #define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('I', 'n', 't', 'e') 3722 #define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 (' ', ' ', ' ', ' ') 3723 #define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('l', 'T', 'D', 'X') 3724 /// 3725 /// @} 3726 /// 3727 3728 /** 3729 CPUID Extended Function 3730 3731 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000) 3732 3733 @retval EAX Maximum Input Value for Extended Function CPUID Information. 3734 @retval EBX Reserved. 3735 @retval ECX Reserved. 3736 @retval EDX Reserved. 3737 3738 <b>Example usage</b> 3739 @code 3740 UINT32 Eax; 3741 3742 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); 3743 @endcode 3744 **/ 3745 #define CPUID_EXTENDED_FUNCTION 0x80000000 3746 3747 /** 3748 CPUID Extended Processor Signature and Feature Bits 3749 3750 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) 3751 3752 @retval EAX CPUID_EXTENDED_CPU_SIG. 3753 @retval EBX Reserved. 3754 @retval ECX Extended Processor Signature and Feature Bits information 3755 described by the type CPUID_EXTENDED_CPU_SIG_ECX. 3756 @retval EDX Extended Processor Signature and Feature Bits information 3757 described by the type CPUID_EXTENDED_CPU_SIG_EDX. 3758 3759 <b>Example usage</b> 3760 @code 3761 UINT32 Eax; 3762 CPUID_EXTENDED_CPU_SIG_ECX Ecx; 3763 CPUID_EXTENDED_CPU_SIG_EDX Edx; 3764 3765 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32); 3766 @endcode 3767 **/ 3768 #define CPUID_EXTENDED_CPU_SIG 0x80000001 3769 3770 /** 3771 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf 3772 #CPUID_EXTENDED_CPU_SIG. 3773 **/ 3774 typedef union { 3775 /// 3776 /// Individual bit fields 3777 /// 3778 struct { 3779 /// 3780 /// [Bit 0] LAHF/SAHF available in 64-bit mode. 3781 /// 3782 UINT32 LAHF_SAHF : 1; 3783 UINT32 Reserved1 : 4; 3784 /// 3785 /// [Bit 5] LZCNT. 3786 /// 3787 UINT32 LZCNT : 1; 3788 UINT32 Reserved2 : 2; 3789 /// 3790 /// [Bit 8] PREFETCHW. 3791 /// 3792 UINT32 PREFETCHW : 1; 3793 UINT32 Reserved3 : 23; 3794 } Bits; 3795 /// 3796 /// All bit fields as a 32-bit value 3797 /// 3798 UINT32 Uint32; 3799 } CPUID_EXTENDED_CPU_SIG_ECX; 3800 3801 /** 3802 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf 3803 #CPUID_EXTENDED_CPU_SIG. 3804 **/ 3805 typedef union { 3806 /// 3807 /// Individual bit fields 3808 /// 3809 struct { 3810 UINT32 Reserved1 : 11; 3811 /// 3812 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode. 3813 /// 3814 UINT32 SYSCALL_SYSRET : 1; 3815 UINT32 Reserved2 : 8; 3816 /// 3817 /// [Bit 20] Execute Disable Bit available. 3818 /// 3819 UINT32 NX : 1; 3820 UINT32 Reserved3 : 5; 3821 /// 3822 /// [Bit 26] 1-GByte pages are available if 1. 3823 /// 3824 UINT32 Page1GB : 1; 3825 /// 3826 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1. 3827 /// 3828 UINT32 RDTSCP : 1; 3829 UINT32 Reserved4 : 1; 3830 /// 3831 /// [Bit 29] Intel(R) 64 Architecture available if 1. 3832 /// 3833 UINT32 LM : 1; 3834 UINT32 Reserved5 : 2; 3835 } Bits; 3836 /// 3837 /// All bit fields as a 32-bit value 3838 /// 3839 UINT32 Uint32; 3840 } CPUID_EXTENDED_CPU_SIG_EDX; 3841 3842 /** 3843 CPUID Processor Brand String 3844 3845 @param EAX CPUID_BRAND_STRING1 (0x80000002) 3846 3847 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA. 3848 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3849 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3850 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3851 3852 <b>Example usage</b> 3853 @code 3854 CPUID_BRAND_STRING_DATA Eax; 3855 CPUID_BRAND_STRING_DATA Ebx; 3856 CPUID_BRAND_STRING_DATA Ecx; 3857 CPUID_BRAND_STRING_DATA Edx; 3858 3859 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3860 @endcode 3861 **/ 3862 #define CPUID_BRAND_STRING1 0x80000002 3863 3864 /** 3865 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1, 3866 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3. 3867 **/ 3868 typedef union { 3869 /// 3870 /// 4 ASCII characters of Processor Brand String 3871 /// 3872 CHAR8 BrandString[4]; 3873 /// 3874 /// All fields as a 32-bit value 3875 /// 3876 UINT32 Uint32; 3877 } CPUID_BRAND_STRING_DATA; 3878 3879 /** 3880 CPUID Processor Brand String 3881 3882 @param EAX CPUID_BRAND_STRING2 (0x80000003) 3883 3884 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3885 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3886 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3887 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3888 3889 <b>Example usage</b> 3890 @code 3891 CPUID_BRAND_STRING_DATA Eax; 3892 CPUID_BRAND_STRING_DATA Ebx; 3893 CPUID_BRAND_STRING_DATA Ecx; 3894 CPUID_BRAND_STRING_DATA Edx; 3895 3896 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3897 @endcode 3898 **/ 3899 #define CPUID_BRAND_STRING2 0x80000003 3900 3901 /** 3902 CPUID Processor Brand String 3903 3904 @param EAX CPUID_BRAND_STRING3 (0x80000004) 3905 3906 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3907 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3908 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3909 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. 3910 3911 <b>Example usage</b> 3912 @code 3913 CPUID_BRAND_STRING_DATA Eax; 3914 CPUID_BRAND_STRING_DATA Ebx; 3915 CPUID_BRAND_STRING_DATA Ecx; 3916 CPUID_BRAND_STRING_DATA Edx; 3917 3918 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); 3919 @endcode 3920 **/ 3921 #define CPUID_BRAND_STRING3 0x80000004 3922 3923 /** 3924 CPUID Extended Cache information 3925 3926 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006) 3927 3928 @retval EAX Reserved. 3929 @retval EBX Reserved. 3930 @retval ECX Extended cache information described by the type 3931 CPUID_EXTENDED_CACHE_INFO_ECX. 3932 @retval EDX Reserved. 3933 3934 <b>Example usage</b> 3935 @code 3936 CPUID_EXTENDED_CACHE_INFO_ECX Ecx; 3937 3938 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL); 3939 @endcode 3940 **/ 3941 #define CPUID_EXTENDED_CACHE_INFO 0x80000006 3942 3943 /** 3944 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO. 3945 **/ 3946 typedef union { 3947 /// 3948 /// Individual bit fields 3949 /// 3950 struct { 3951 /// 3952 /// [Bits 7:0] Cache line size in bytes. 3953 /// 3954 UINT32 CacheLineSize : 8; 3955 UINT32 Reserved : 4; 3956 /// 3957 /// [Bits 15:12] L2 Associativity field. Supported values are in the range 3958 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to 3959 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 3960 /// 3961 UINT32 L2Associativity : 4; 3962 /// 3963 /// [Bits 31:16] Cache size in 1K units. 3964 /// 3965 UINT32 CacheSize : 16; 3966 } Bits; 3967 /// 3968 /// All bit fields as a 32-bit value 3969 /// 3970 UINT32 Uint32; 3971 } CPUID_EXTENDED_CACHE_INFO_ECX; 3972 3973 /// 3974 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity 3975 /// 3976 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00 3977 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01 3978 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02 3979 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04 3980 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06 3981 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08 3982 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A 3983 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B 3984 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C 3985 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D 3986 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E 3987 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F 3988 /// 3989 /// @} 3990 /// 3991 3992 /** 3993 CPUID Extended Time Stamp Counter information 3994 3995 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007) 3996 3997 @retval EAX Reserved. 3998 @retval EBX Reserved. 3999 @retval ECX Reserved. 4000 @retval EDX Extended time stamp counter (TSC) information described by the 4001 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX. 4002 4003 <b>Example usage</b> 4004 @code 4005 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx; 4006 4007 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32); 4008 @endcode 4009 **/ 4010 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007 4011 4012 /** 4013 CPUID Extended Time Stamp Counter information EDX for CPUID leaf 4014 #CPUID_EXTENDED_TIME_STAMP_COUNTER. 4015 **/ 4016 typedef union { 4017 /// 4018 /// Individual bit fields 4019 /// 4020 struct { 4021 UINT32 Reserved1 : 8; 4022 /// 4023 /// [Bit 8] Invariant TSC available if 1. 4024 /// 4025 UINT32 InvariantTsc : 1; 4026 UINT32 Reserved2 : 23; 4027 } Bits; 4028 /// 4029 /// All bit fields as a 32-bit value 4030 /// 4031 UINT32 Uint32; 4032 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX; 4033 4034 /** 4035 CPUID Linear Physical Address Size 4036 4037 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) 4038 4039 @retval EAX Linear/Physical Address Size described by the type 4040 CPUID_VIR_PHY_ADDRESS_SIZE_EAX. 4041 @retval EBX Reserved. 4042 @retval ECX Reserved. 4043 @retval EDX Reserved. 4044 4045 <b>Example usage</b> 4046 @code 4047 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax; 4048 4049 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL); 4050 @endcode 4051 **/ 4052 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 4053 4054 /** 4055 CPUID Linear Physical Address Size EAX for CPUID leaf 4056 #CPUID_VIR_PHY_ADDRESS_SIZE. 4057 **/ 4058 typedef union { 4059 /// 4060 /// Individual bit fields 4061 /// 4062 struct { 4063 /// 4064 /// [Bits 7:0] Number of physical address bits. 4065 /// 4066 /// @note 4067 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address 4068 /// number supported should come from this field. 4069 /// 4070 UINT32 PhysicalAddressBits : 8; 4071 /// 4072 /// [Bits 15:8] Number of linear address bits. 4073 /// 4074 UINT32 LinearAddressBits : 8; 4075 UINT32 Reserved : 16; 4076 } Bits; 4077 /// 4078 /// All bit fields as a 32-bit value 4079 /// 4080 UINT32 Uint32; 4081 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX; 4082 4083 #endif 4084