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Searched defs:AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT (Results 1 – 6 of 6) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h13398 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_11_0_sh_mask.h13404 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_11_2_sh_mask.h14020 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
H A Ddce_12_0_sh_mask.h6992 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
H A Ddce_8_0_sh_mask.h12140 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h8127 #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro