1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo1 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /****************************************************************************** 8 * 9 * 1. Copyright Notice 10 * 11 * Some or all of this work - Copyright (c) 1999 - 2023, Intel Corp. 12 * All rights reserved. 13 * 14 * 2. License 15 * 16 * 2.1. This is your license from Intel Corp. under its intellectual property 17 * rights. You may have additional license terms from the party that provided 18 * you this software, covering your right to use that party's intellectual 19 * property rights. 20 * 21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 22 * copy of the source code appearing in this file ("Covered Code") an 23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 24 * base code distributed originally by Intel ("Original Intel Code") to copy, 25 * make derivatives, distribute, use and display any portion of the Covered 26 * Code in any form, with the right to sublicense such rights; and 27 * 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 29 * license (with the right to sublicense), under only those claims of Intel 30 * patents that are infringed by the Original Intel Code, to make, use, sell, 31 * offer to sell, and import the Covered Code and derivative works thereof 32 * solely to the minimum extent necessary to exercise the above copyright 33 * license, and in no event shall the patent license extend to any additions 34 * to or modifications of the Original Intel Code. No other license or right 35 * is granted directly or by implication, estoppel or otherwise; 36 * 37 * The above copyright and patent license is granted only if the following 38 * conditions are met: 39 * 40 * 3. Conditions 41 * 42 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 43 * Redistribution of source code of any substantial portion of the Covered 44 * Code or modification with rights to further distribute source must include 45 * the above Copyright Notice, the above License, this list of Conditions, 46 * and the following Disclaimer and Export Compliance provision. In addition, 47 * Licensee must cause all Covered Code to which Licensee contributes to 48 * contain a file documenting the changes Licensee made to create that Covered 49 * Code and the date of any change. Licensee must include in that file the 50 * documentation of any changes made by any predecessor Licensee. Licensee 51 * must include a prominent statement that the modification is derived, 52 * directly or indirectly, from Original Intel Code. 53 * 54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 55 * Redistribution of source code of any substantial portion of the Covered 56 * Code or modification without rights to further distribute source must 57 * include the following Disclaimer and Export Compliance provision in the 58 * documentation and/or other materials provided with distribution. In 59 * addition, Licensee may not authorize further sublicense of source of any 60 * portion of the Covered Code, and must include terms to the effect that the 61 * license from Licensee to its licensee is limited to the intellectual 62 * property embodied in the software Licensee provides to its licensee, and 63 * not to intellectual property embodied in modifications its licensee may 64 * make. 65 * 66 * 3.3. Redistribution of Executable. Redistribution in executable form of any 67 * substantial portion of the Covered Code or modification must reproduce the 68 * above Copyright Notice, and the following Disclaimer and Export Compliance 69 * provision in the documentation and/or other materials provided with the 70 * distribution. 71 * 72 * 3.4. Intel retains all right, title, and interest in and to the Original 73 * Intel Code. 74 * 75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 76 * Intel shall be used in advertising or otherwise to promote the sale, use or 77 * other dealings in products derived from or relating to the Covered Code 78 * without prior written authorization from Intel. 79 * 80 * 4. Disclaimer and Export Compliance 81 * 82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 88 * PARTICULAR PURPOSE. 89 * 90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 97 * LIMITED REMEDY. 98 * 99 * 4.3. Licensee shall not export, either directly or indirectly, any of this 100 * software or system incorporating such software without first obtaining any 101 * required license or other approval from the U. S. Department of Commerce or 102 * any other agency or department of the United States Government. In the 103 * event Licensee exports any such software from the United States or 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 106 * compliance with all laws, regulations, orders, or other restrictions of the 107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 108 * any of its subsidiaries will export/re-export any technical data, process, 109 * software, or service, directly or indirectly, to any country for which the 110 * United States government or any agency thereof requires an export license, 111 * other governmental approval, or letter of assurance, without first obtaining 112 * such license, approval or letter. 113 * 114 ***************************************************************************** 115 * 116 * Alternatively, you may choose to be licensed under the terms of the 117 * following license: 118 * 119 * Redistribution and use in source and binary forms, with or without 120 * modification, are permitted provided that the following conditions 121 * are met: 122 * 1. Redistributions of source code must retain the above copyright 123 * notice, this list of conditions, and the following disclaimer, 124 * without modification. 125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 126 * substantially similar to the "NO WARRANTY" disclaimer below 127 * ("Disclaimer") and any redistribution must be conditioned upon 128 * including a substantially similar Disclaimer requirement for further 129 * binary redistribution. 130 * 3. Neither the names of the above-listed copyright holders nor the names 131 * of any contributors may be used to endorse or promote products derived 132 * from this software without specific prior written permission. 133 * 134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 145 * 146 * Alternatively, you may choose to be licensed under the terms of the 147 * GNU General Public License ("GPL") version 2 as published by the Free 148 * Software Foundation. 149 * 150 *****************************************************************************/ 151 152 #include <contrib/dev/acpica/include/acpi.h> 153 #include <contrib/dev/acpica/include/accommon.h> 154 #include <contrib/dev/acpica/include/acdisasm.h> 155 #include <contrib/dev/acpica/include/actbinfo.h> 156 157 /* This module used for application-level code only */ 158 159 #define _COMPONENT ACPI_CA_DISASSEMBLER 160 ACPI_MODULE_NAME ("dmtbinfo1") 161 162 /* 163 * How to add a new table: 164 * 165 * - Add the C table definition to the actbl1.h or actbl2.h header. 166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 167 * - Define the table in this file (for the disassembler). If any 168 * new data types are required (ACPI_DMT_*), see below. 169 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 170 * in acdisam.h 171 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 172 * If a simple table (with no subtables), no disassembly code is needed. 173 * Otherwise, create the AcpiDmDump* function for to disassemble the table 174 * and add it to the dmtbdump.c file. 175 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 176 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 177 * - Create a template for the new table 178 * - Add data table compiler support 179 * 180 * How to add a new data type (ACPI_DMT_*): 181 * 182 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 183 * - Add length and implementation cases in dmtable.c (disassembler) 184 * - Add type and length cases in dtutils.c (DT compiler) 185 */ 186 187 /* 188 * ACPI Table Information, used to dump formatted ACPI tables 189 * 190 * Each entry is of the form: <Field Type, Field Offset, Field Name> 191 */ 192 193 194 /******************************************************************************* 195 * 196 * AEST - ARM Error Source table. Conforms to: 197 * ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document Sep 2020 198 * 199 ******************************************************************************/ 200 201 /* Common Subtable header (one per Subtable) */ 202 203 ACPI_DMTABLE_INFO AcpiDmTableInfoAestHdr[] = 204 { 205 {ACPI_DMT_AEST, ACPI_AESTH_OFFSET (Type), "Subtable Type", 0}, 206 {ACPI_DMT_UINT16, ACPI_AESTH_OFFSET (Length), "Length", DT_LENGTH}, 207 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0}, 208 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeSpecificOffset), "Node Specific Offset", 0}, 209 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterfaceOffset), "Node Interface Offset", 0}, 210 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptOffset), "Node Interrupt Array Offset", 0}, 211 {ACPI_DMT_UINT32, ACPI_AESTH_OFFSET (NodeInterruptCount), "Node Interrupt Array Count", 0}, 212 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (TimestampRate), "Timestamp Rate", 0}, 213 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0}, 214 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (ErrorInjectionRate), "Error Injection Rate", 0}, 215 ACPI_DMT_TERMINATOR 216 }; 217 218 /* 219 * AEST subtables (nodes) 220 */ 221 222 /* 0: Processor Error */ 223 224 ACPI_DMTABLE_INFO AcpiDmTableInfoAestProcError[] = 225 { 226 {ACPI_DMT_UINT32, ACPI_AEST0_OFFSET (ProcessorId), "Processor ID", 0}, 227 {ACPI_DMT_AEST_RES, ACPI_AEST0_OFFSET (ResourceType), "Resource Type", 0}, 228 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0}, 229 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Flags), "Flags (decoded Below)", 0}, 230 {ACPI_DMT_FLAG0, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Global", 0}, 231 {ACPI_DMT_FLAG1, ACPI_AEST0_FLAG_OFFSET (Flags, 0), "Shared", 0}, 232 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Revision), "Revision", 0}, 233 {ACPI_DMT_UINT64, ACPI_AEST0_OFFSET (ProcessorAffinity), "Processor Affinity Structure", 0}, 234 ACPI_DMT_TERMINATOR 235 }; 236 237 /* 0RT: Processor Cache Resource */ 238 239 ACPI_DMTABLE_INFO AcpiDmTableInfoAestCacheRsrc[] = 240 { 241 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (CacheReference), "Cache Reference", 0}, 242 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0}, 243 ACPI_DMT_TERMINATOR 244 }; 245 246 /* 1RT: ProcessorTLB Resource */ 247 248 ACPI_DMTABLE_INFO AcpiDmTableInfoAestTlbRsrc[] = 249 { 250 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (TlbLevel), "TLB Level", 0}, 251 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}, 252 ACPI_DMT_TERMINATOR 253 }; 254 255 /* 2RT: Processor Generic Resource */ 256 257 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGenRsrc[] = 258 { 259 {ACPI_DMT_RAW_BUFFER, 0, "Resource", 0}, 260 ACPI_DMT_TERMINATOR 261 }; 262 263 /* 1: Memory Error */ 264 265 ACPI_DMTABLE_INFO AcpiDmTableInfoAestMemError[] = 266 { 267 {ACPI_DMT_UINT32, ACPI_AEST1_OFFSET (SratProximityDomain), "Srat Proximity Domain", 0}, 268 ACPI_DMT_TERMINATOR 269 }; 270 271 /* 2: Smmu Error */ 272 273 ACPI_DMTABLE_INFO AcpiDmTableInfoAestSmmuError[] = 274 { 275 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (IortNodeReference), "Iort Node Reference", 0}, 276 {ACPI_DMT_UINT32, ACPI_AEST2_OFFSET (SubcomponentReference), "Subcomponent Reference", 0}, 277 ACPI_DMT_TERMINATOR 278 }; 279 280 /* 3: Vendor Defined */ 281 282 ACPI_DMTABLE_INFO AcpiDmTableInfoAestVendorError[] = 283 { 284 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiHid), "ACPI HID", 0}, 285 {ACPI_DMT_UINT32, ACPI_AEST3_OFFSET (AcpiUid), "ACPI UID", 0}, 286 {ACPI_DMT_BUF16, ACPI_AEST3_OFFSET (VendorSpecificData), "Vendor Specific Data", 0}, 287 ACPI_DMT_TERMINATOR 288 }; 289 290 /* 4: Gic Error */ 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoAestGicError[] = 293 { 294 {ACPI_DMT_AEST_GIC, ACPI_AEST4_OFFSET (InterfaceType), "GIC Interface Type", 0}, 295 {ACPI_DMT_UINT32, ACPI_AEST4_OFFSET (InstanceId), "Instance ID", 0}, 296 ACPI_DMT_TERMINATOR 297 }; 298 299 /* AestXface: Node Interface Structure */ 300 301 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXface[] = 302 { 303 {ACPI_DMT_AEST_XFACE, ACPI_AEST0D_OFFSET (Type), "Interface Type", 0}, 304 {ACPI_DMT_UINT24, ACPI_AEST0D_OFFSET (Reserved[0]), "Reserved", 0}, 305 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (Flags), "Flags (decoded below)", 0}, 306 {ACPI_DMT_FLAG0, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Shared Interface", 0}, 307 {ACPI_DMT_FLAG1, ACPI_AEST0D_FLAG_OFFSET (Flags, 0), "Clear MISCx Registers", 0}, 308 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (Address), "Address", 0}, 309 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordIndex), "Error Record Index", 0}, 310 {ACPI_DMT_UINT32, ACPI_AEST0D_OFFSET (ErrorRecordCount), "Error Record Count", 0}, 311 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorRecordImplemented),"Error Record Implemented", 0}, 312 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (ErrorStatusReporting), "Error Status Reporting", 0}, 313 {ACPI_DMT_UINT64, ACPI_AEST0D_OFFSET (AddressingMode), "Addressing Mode", 0}, 314 ACPI_DMT_TERMINATOR 315 }; 316 317 /* AestXrupt: Node Interrupt Structure */ 318 319 ACPI_DMTABLE_INFO AcpiDmTableInfoAestXrupt[] = 320 { 321 {ACPI_DMT_AEST_XRUPT, ACPI_AEST0E_OFFSET (Type), "Interrupt Type", 0}, 322 {ACPI_DMT_UINT16, ACPI_AEST0E_OFFSET (Reserved), "Reserved", 0}, 323 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (Flags), "Flags (decoded below)", 0}, 324 {ACPI_DMT_FLAG0, ACPI_AEST0E_FLAG_OFFSET (Flags, 0), "Level Triggered", 0}, 325 {ACPI_DMT_UINT32, ACPI_AEST0E_OFFSET (Gsiv), "Gsiv", 0}, 326 {ACPI_DMT_UINT8, ACPI_AEST0E_OFFSET (IortId), "IortId", 0}, 327 {ACPI_DMT_UINT24, ACPI_AEST0E_OFFSET (Reserved1[0]), "Reserved", 0}, 328 ACPI_DMT_TERMINATOR 329 }; 330 331 332 /******************************************************************************* 333 * 334 * ASF - Alert Standard Format table (Signature "ASF!") 335 * 336 ******************************************************************************/ 337 338 /* Common Subtable header (one per Subtable) */ 339 340 ACPI_DMTABLE_INFO AcpiDmTableInfoAsfHdr[] = 341 { 342 {ACPI_DMT_ASF, ACPI_ASF0_OFFSET (Header.Type), "Subtable Type", 0}, 343 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Header.Reserved), "Reserved", 0}, 344 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (Header.Length), "Length", DT_LENGTH}, 345 ACPI_DMT_TERMINATOR 346 }; 347 348 /* 0: ASF Information */ 349 350 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf0[] = 351 { 352 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinResetValue), "Minimum Reset Value", 0}, 353 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (MinPollInterval), "Minimum Polling Interval", 0}, 354 {ACPI_DMT_UINT16, ACPI_ASF0_OFFSET (SystemId), "System ID", 0}, 355 {ACPI_DMT_UINT32, ACPI_ASF0_OFFSET (MfgId), "Manufacturer ID", 0}, 356 {ACPI_DMT_UINT8, ACPI_ASF0_OFFSET (Flags), "Flags", 0}, 357 {ACPI_DMT_UINT24, ACPI_ASF0_OFFSET (Reserved2[0]), "Reserved", 0}, 358 ACPI_DMT_TERMINATOR 359 }; 360 361 /* 1: ASF Alerts */ 362 363 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1[] = 364 { 365 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (AssertMask), "AssertMask", 0}, 366 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DeassertMask), "DeassertMask", 0}, 367 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (Alerts), "Alert Count", 0}, 368 {ACPI_DMT_UINT8, ACPI_ASF1_OFFSET (DataLength), "Alert Data Length", 0}, 369 ACPI_DMT_TERMINATOR 370 }; 371 372 /* 1a: ASF Alert data */ 373 374 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf1a[] = 375 { 376 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Address), "Address", 0}, 377 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Command), "Command", 0}, 378 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Mask), "Mask", 0}, 379 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Value), "Value", 0}, 380 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorType), "SensorType", 0}, 381 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Type), "Type", 0}, 382 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Offset), "Offset", 0}, 383 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SourceType), "SourceType", 0}, 384 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Severity), "Severity", 0}, 385 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (SensorNumber), "SensorNumber", 0}, 386 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Entity), "Entity", 0}, 387 {ACPI_DMT_UINT8, ACPI_ASF1a_OFFSET (Instance), "Instance", 0}, 388 ACPI_DMT_TERMINATOR 389 }; 390 391 /* 2: ASF Remote Control */ 392 393 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2[] = 394 { 395 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (Controls), "Control Count", 0}, 396 {ACPI_DMT_UINT8, ACPI_ASF2_OFFSET (DataLength), "Control Data Length", 0}, 397 {ACPI_DMT_UINT16, ACPI_ASF2_OFFSET (Reserved2), "Reserved", 0}, 398 ACPI_DMT_TERMINATOR 399 }; 400 401 /* 2a: ASF Control data */ 402 403 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf2a[] = 404 { 405 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Function), "Function", 0}, 406 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Address), "Address", 0}, 407 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Command), "Command", 0}, 408 {ACPI_DMT_UINT8, ACPI_ASF2a_OFFSET (Value), "Value", 0}, 409 ACPI_DMT_TERMINATOR 410 }; 411 412 /* 3: ASF RMCP Boot Options */ 413 414 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf3[] = 415 { 416 {ACPI_DMT_BUF7, ACPI_ASF3_OFFSET (Capabilities[0]), "Capabilities", 0}, 417 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (CompletionCode), "Completion Code", 0}, 418 {ACPI_DMT_UINT32, ACPI_ASF3_OFFSET (EnterpriseId), "Enterprise ID", 0}, 419 {ACPI_DMT_UINT8, ACPI_ASF3_OFFSET (Command), "Command", 0}, 420 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (Parameter), "Parameter", 0}, 421 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (BootOptions), "Boot Options", 0}, 422 {ACPI_DMT_UINT16, ACPI_ASF3_OFFSET (OemParameters), "Oem Parameters", 0}, 423 ACPI_DMT_TERMINATOR 424 }; 425 426 /* 4: ASF Address */ 427 428 ACPI_DMTABLE_INFO AcpiDmTableInfoAsf4[] = 429 { 430 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (EpromAddress), "Eprom Address", 0}, 431 {ACPI_DMT_UINT8, ACPI_ASF4_OFFSET (Devices), "Device Count", DT_COUNT}, 432 ACPI_DMT_TERMINATOR 433 }; 434 435 436 /******************************************************************************* 437 * 438 * ASPT - AMD Secure Processor table (Signature "ASPT") 439 * 440 ******************************************************************************/ 441 442 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt[] = 443 { 444 {ACPI_DMT_UINT32, ACPI_ASPT_OFFSET(NumEntries), "Number of Subtables", 0}, 445 ACPI_DMT_TERMINATOR 446 }; 447 448 /* Common Subtable header (one per Subtable) */ 449 ACPI_DMTABLE_INFO AcpiDmTableInfoAsptHdr[] = 450 { 451 {ACPI_DMT_ASPT, ACPI_ASPTH_OFFSET(Type), "Type", 0}, 452 {ACPI_DMT_UINT16, ACPI_ASPTH_OFFSET(Length), "Length", 0}, 453 ACPI_DMT_TERMINATOR 454 }; 455 456 /* 0: ASPT Global Registers */ 457 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt0[] = 458 { 459 {ACPI_DMT_UINT32, ACPI_ASPT0_OFFSET(Reserved), "Reserved", 0}, 460 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(FeatureRegAddr), "Feature Register Address", 0}, 461 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqEnRegAddr), "Interrupt Enable Register Address", 0}, 462 {ACPI_DMT_UINT64, ACPI_ASPT0_OFFSET(IrqStRegAddr), "Interrupt Status Register Address", 0}, 463 ACPI_DMT_TERMINATOR 464 }; 465 466 /* 1: ASPT SEV Mailbox Registers */ 467 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt1[] = 468 { 469 {ACPI_DMT_UINT8, ACPI_ASPT1_OFFSET(MboxIrqId), "Mailbox Interrupt ID", 0}, 470 {ACPI_DMT_UINT24, ACPI_ASPT1_OFFSET(Reserved[0]), "Reserved", 0}, 471 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 472 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufLoRegAddr), "CmdBufAddr_Lo Register Address", 0}, 473 {ACPI_DMT_UINT64, ACPI_ASPT1_OFFSET(CmdBufHiRegAddr), "CmdBufAddr_Hi Register Address", 0}, 474 ACPI_DMT_TERMINATOR 475 }; 476 477 /* 2: ASPT ACPI Maiblox Registers */ 478 ACPI_DMTABLE_INFO AcpiDmTableInfoAspt2[] = 479 { 480 {ACPI_DMT_UINT32, ACPI_ASPT2_OFFSET(Reserved1), "Reserved", 0}, 481 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(CmdRespRegAddr), "CmdResp Register Address", 0}, 482 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[0]), "Reserved", 0}, 483 {ACPI_DMT_UINT64, ACPI_ASPT2_OFFSET(Reserved2[1]), "Reserved", 0}, 484 ACPI_DMT_TERMINATOR 485 }; 486 487 /******************************************************************************* 488 * 489 * BDAT - BIOS Data ACPI Table 490 * 491 ******************************************************************************/ 492 493 ACPI_DMTABLE_INFO AcpiDmTableInfoBdat[] = 494 { 495 {ACPI_DMT_GAS, ACPI_BDAT_OFFSET (Gas), "BDAT Generic Address", 0}, 496 ACPI_DMT_TERMINATOR 497 }; 498 499 500 /******************************************************************************* 501 * 502 * BERT - Boot Error Record table 503 * 504 ******************************************************************************/ 505 506 ACPI_DMTABLE_INFO AcpiDmTableInfoBert[] = 507 { 508 {ACPI_DMT_UINT32, ACPI_BERT_OFFSET (RegionLength), "Boot Error Region Length", 0}, 509 {ACPI_DMT_UINT64, ACPI_BERT_OFFSET (Address), "Boot Error Region Address", 0}, 510 ACPI_DMT_TERMINATOR 511 }; 512 513 514 /******************************************************************************* 515 * 516 * BGRT - Boot Graphics Resource Table (ACPI 5.0) 517 * 518 ******************************************************************************/ 519 520 ACPI_DMTABLE_INFO AcpiDmTableInfoBgrt[] = 521 { 522 {ACPI_DMT_UINT16, ACPI_BGRT_OFFSET (Version), "Version", 0}, 523 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (Status), "Status (decoded below)", DT_FLAG}, 524 {ACPI_DMT_FLAG0, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Displayed", 0}, 525 {ACPI_DMT_FLAGS1, ACPI_BGRT_FLAG_OFFSET (Status, 0), "Orientation Offset", 0}, 526 527 {ACPI_DMT_UINT8, ACPI_BGRT_OFFSET (ImageType), "Image Type", 0}, 528 {ACPI_DMT_UINT64, ACPI_BGRT_OFFSET (ImageAddress), "Image Address", 0}, 529 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetX), "Image OffsetX", 0}, 530 {ACPI_DMT_UINT32, ACPI_BGRT_OFFSET (ImageOffsetY), "Image OffsetY", 0}, 531 ACPI_DMT_TERMINATOR 532 }; 533 534 535 /******************************************************************************* 536 * 537 * BOOT - Simple Boot Flag Table 538 * 539 ******************************************************************************/ 540 541 ACPI_DMTABLE_INFO AcpiDmTableInfoBoot[] = 542 { 543 {ACPI_DMT_UINT8, ACPI_BOOT_OFFSET (CmosIndex), "Boot Register Index", 0}, 544 {ACPI_DMT_UINT24, ACPI_BOOT_OFFSET (Reserved[0]), "Reserved", 0}, 545 ACPI_DMT_TERMINATOR 546 }; 547 548 /******************************************************************************* 549 * 550 * CDAT - Coherent Device Attribute Table 551 * 552 ******************************************************************************/ 553 554 /* Table header (not ACPI-compliant) */ 555 556 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatTableHdr[] = 557 { 558 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Length), "CDAT Table Length", DT_LENGTH}, 559 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Revision), "Revision", 0}, 560 {ACPI_DMT_UINT8, ACPI_CDAT_OFFSET (Checksum), "Checksum", 0}, 561 {ACPI_DMT_UINT48, ACPI_CDAT_OFFSET (Reserved), "Reserved", 0}, 562 {ACPI_DMT_UINT32, ACPI_CDAT_OFFSET (Sequence), "Sequence", 0}, 563 ACPI_DMT_TERMINATOR 564 }; 565 566 /* Common subtable header */ 567 568 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatHeader[] = 569 { 570 {ACPI_DMT_CDAT, ACPI_CDATH_OFFSET (Type), "Subtable Type", 0}, 571 {ACPI_DMT_UINT8, ACPI_CDATH_OFFSET (Reserved), "Reserved", 0}, 572 {ACPI_DMT_UINT16, ACPI_CDATH_OFFSET (Length), "Length", DT_LENGTH}, 573 ACPI_DMT_TERMINATOR 574 }; 575 576 /* Subtable 0: Device Scoped Memory Affinity Structure (DSMAS) */ 577 578 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat0[] = 579 { 580 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (DsmadHandle), "DSMAD Handle", 0}, 581 {ACPI_DMT_UINT8, ACPI_CDAT0_OFFSET (Flags), "Flags", 0}, 582 {ACPI_DMT_UINT16, ACPI_CDAT0_OFFSET (Reserved), "Reserved", 0}, 583 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaBaseAddress), "DPA Base Address", 0}, 584 {ACPI_DMT_UINT64, ACPI_CDAT0_OFFSET (DpaLength), "DPA Length", 0}, 585 ACPI_DMT_TERMINATOR 586 }; 587 588 /* Subtable 1: Device scoped Latency and Bandwidth Information Structure (DSLBIS) */ 589 590 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat1[] = 591 { 592 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Handle), "Handle", 0}, 593 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Flags), "Flags", 0}, 594 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (DataType), "Data Type", 0}, 595 {ACPI_DMT_UINT8, ACPI_CDAT1_OFFSET (Reserved), "Reserved", 0}, 596 {ACPI_DMT_UINT64, ACPI_CDAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 597 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[0]), "Entry0", 0}, 598 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[1]), "Entry1", 0}, 599 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Entry[2]), "Entry2", 0}, 600 {ACPI_DMT_UINT16, ACPI_CDAT1_OFFSET (Reserved2), "Reserved", 0}, 601 ACPI_DMT_TERMINATOR 602 }; 603 604 /* Subtable 2: Device Scoped Memory Side Cache Information Structure (DSMSCIS) */ 605 606 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat2[] = 607 { 608 {ACPI_DMT_UINT8, ACPI_CDAT2_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 609 {ACPI_DMT_UINT24, ACPI_CDAT2_OFFSET (Reserved[3]), "Reserved", 0}, 610 {ACPI_DMT_UINT64, ACPI_CDAT2_OFFSET (SideCacheSize), "Side Cache Size", 0}, 611 {ACPI_DMT_UINT32, ACPI_CDAT2_OFFSET (CacheAttributes), "Cache Attributes", 0}, 612 ACPI_DMT_TERMINATOR 613 }; 614 615 /* Subtable 3: Device Scoped Initiator Structure (DSIS) */ 616 617 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat3[] = 618 { 619 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Flags), "Flags", 0}, 620 {ACPI_DMT_UINT8, ACPI_CDAT3_OFFSET (Handle), "Handle", 0}, 621 {ACPI_DMT_UINT16, ACPI_CDAT3_OFFSET (Reserved), "Reserved", 0}, 622 ACPI_DMT_TERMINATOR 623 }; 624 625 /* Subtable 4: Device Scoped EFI Memory Type Structure (DSEMTS) */ 626 627 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat4[] = 628 { 629 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (DsmasHandle), "DSMAS Handle", 0}, 630 {ACPI_DMT_UINT8, ACPI_CDAT4_OFFSET (MemoryType), "Memory Type", 0}, 631 {ACPI_DMT_UINT16, ACPI_CDAT4_OFFSET (Reserved), "Reserved", 0}, 632 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (DpaOffset), "DPA Offset", 0}, 633 {ACPI_DMT_UINT64, ACPI_CDAT4_OFFSET (RangeLength), "DPA Range Length", 0}, 634 ACPI_DMT_TERMINATOR 635 }; 636 637 /* Subtable 5: Switch Scoped Latency and Bandwidth Information Structure (SSLBIS) */ 638 639 ACPI_DMTABLE_INFO AcpiDmTableInfoCdat5[] = 640 { 641 {ACPI_DMT_UINT8, ACPI_CDAT5_OFFSET (DataType), "Data Type", 0}, 642 {ACPI_DMT_UINT24, ACPI_CDAT5_OFFSET (Reserved), "Reserved", 0}, 643 {ACPI_DMT_UINT64, ACPI_CDAT5_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 644 ACPI_DMT_TERMINATOR 645 }; 646 647 /* Switch Scoped Latency and Bandwidth Entry (SSLBE) (For subtable 5 above) */ 648 649 ACPI_DMTABLE_INFO AcpiDmTableInfoCdatEntries[] = 650 { 651 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortxId), "Port X Id", 0}, 652 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (PortyId), "Port Y Id", 0}, 653 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (LatencyOrBandwidth), "Latency or Bandwidth", 0}, 654 {ACPI_DMT_UINT16, ACPI_CDATE_OFFSET (Reserved), "Reserved", 0}, 655 ACPI_DMT_TERMINATOR 656 }; 657 658 659 /******************************************************************************* 660 * 661 * CEDT - CXL Early Discovery Table 662 * 663 ******************************************************************************/ 664 665 ACPI_DMTABLE_INFO AcpiDmTableInfoCedtHdr[] = 666 { 667 {ACPI_DMT_CEDT, ACPI_CEDT_OFFSET (Type), "Subtable Type", 0}, 668 {ACPI_DMT_UINT8, ACPI_CEDT_OFFSET (Reserved), "Reserved", 0}, 669 {ACPI_DMT_UINT16, ACPI_CEDT_OFFSET (Length), "Length", DT_LENGTH}, 670 ACPI_DMT_TERMINATOR 671 }; 672 673 /* 0: CXL Host Bridge Structure */ 674 675 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt0[] = 676 { 677 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Uid), "Associated host bridge", 0}, 678 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (CxlVersion), "Specification version", 0}, 679 {ACPI_DMT_UINT32, ACPI_CEDT0_OFFSET (Reserved), "Reserved", 0}, 680 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Base), "Register base", 0}, 681 {ACPI_DMT_UINT64, ACPI_CEDT0_OFFSET (Length), "Register length", 0}, 682 ACPI_DMT_TERMINATOR 683 }; 684 685 /* 1: CXL Fixed Memory Window Structure */ 686 687 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1[] = 688 { 689 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Reserved1), "Reserved", 0}, 690 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (BaseHpa), "Window base address", 0}, 691 {ACPI_DMT_UINT64, ACPI_CEDT1_OFFSET (WindowSize), "Window size", 0}, 692 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveWays), "Interleave Members (2^n)", 0}, 693 {ACPI_DMT_UINT8, ACPI_CEDT1_OFFSET (InterleaveArithmetic), "Interleave Arithmetic", 0}, 694 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Reserved2), "Reserved", 0}, 695 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (Granularity), "Granularity", 0}, 696 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (Restrictions), "Restrictions", 0}, 697 {ACPI_DMT_UINT16, ACPI_CEDT1_OFFSET (QtgId), "QtgId", 0}, 698 {ACPI_DMT_UINT32, ACPI_CEDT1_OFFSET (InterleaveTargets), "First Target", 0}, 699 ACPI_DMT_TERMINATOR 700 }; 701 702 ACPI_DMTABLE_INFO AcpiDmTableInfoCedt1_te[] = 703 { 704 {ACPI_DMT_UINT32, ACPI_CEDT1_TE_OFFSET (InterleaveTarget), "Next Target", 0}, 705 ACPI_DMT_TERMINATOR 706 }; 707 708 /******************************************************************************* 709 * 710 * CPEP - Corrected Platform Error Polling table 711 * 712 ******************************************************************************/ 713 714 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep[] = 715 { 716 {ACPI_DMT_UINT64, ACPI_CPEP_OFFSET (Reserved), "Reserved", 0}, 717 ACPI_DMT_TERMINATOR 718 }; 719 720 ACPI_DMTABLE_INFO AcpiDmTableInfoCpep0[] = 721 { 722 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Type), "Subtable Type", 0}, 723 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Header.Length), "Length", DT_LENGTH}, 724 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Id), "Processor ID", 0}, 725 {ACPI_DMT_UINT8, ACPI_CPEP0_OFFSET (Eid), "Processor EID", 0}, 726 {ACPI_DMT_UINT32, ACPI_CPEP0_OFFSET (Interval), "Polling Interval", 0}, 727 ACPI_DMT_TERMINATOR 728 }; 729 730 731 /******************************************************************************* 732 * 733 * CSRT - Core System Resource Table 734 * 735 ******************************************************************************/ 736 737 /* Main table consists only of the standard ACPI table header */ 738 739 /* Resource Group subtable */ 740 741 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt0[] = 742 { 743 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (Length), "Length", DT_LENGTH}, 744 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (VendorId), "Vendor ID", 0}, 745 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SubvendorId), "Subvendor ID", 0}, 746 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (DeviceId), "Device ID", 0}, 747 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (SubdeviceId), "Subdevice ID", 0}, 748 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Revision), "Revision", 0}, 749 {ACPI_DMT_UINT16, ACPI_CSRT0_OFFSET (Reserved), "Reserved", 0}, 750 {ACPI_DMT_UINT32, ACPI_CSRT0_OFFSET (SharedInfoLength), "Shared Info Length", 0}, 751 ACPI_DMT_TERMINATOR 752 }; 753 754 /* Shared Info subtable */ 755 756 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt1[] = 757 { 758 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MajorVersion), "Major Version", 0}, 759 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (MinorVersion), "Minor Version", 0}, 760 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseLow), "MMIO Base Address Low", 0}, 761 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MmioBaseHigh), "MMIO Base Address High", 0}, 762 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (GsiInterrupt), "GSI Interrupt", 0}, 763 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptPolarity), "Interrupt Polarity", 0}, 764 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (InterruptMode), "Interrupt Mode", 0}, 765 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (NumChannels), "Num Channels", 0}, 766 {ACPI_DMT_UINT8, ACPI_CSRT1_OFFSET (DmaAddressWidth), "DMA Address Width", 0}, 767 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (BaseRequestLine), "Base Request Line", 0}, 768 {ACPI_DMT_UINT16, ACPI_CSRT1_OFFSET (NumHandshakeSignals), "Num Handshake Signals", 0}, 769 {ACPI_DMT_UINT32, ACPI_CSRT1_OFFSET (MaxBlockSize), "Max Block Size", 0}, 770 ACPI_DMT_TERMINATOR 771 }; 772 773 /* Resource Descriptor subtable */ 774 775 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2[] = 776 { 777 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Length), "Length", DT_LENGTH}, 778 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Type), "Type", 0}, 779 {ACPI_DMT_UINT16, ACPI_CSRT2_OFFSET (Subtype), "Subtype", 0}, 780 {ACPI_DMT_UINT32, ACPI_CSRT2_OFFSET (Uid), "UID", 0}, 781 ACPI_DMT_TERMINATOR 782 }; 783 784 ACPI_DMTABLE_INFO AcpiDmTableInfoCsrt2a[] = 785 { 786 {ACPI_DMT_RAW_BUFFER, 0, "ResourceInfo", DT_OPTIONAL}, 787 ACPI_DMT_TERMINATOR 788 }; 789 790 791 /******************************************************************************* 792 * 793 * DBG2 - Debug Port Table 2 794 * 795 ******************************************************************************/ 796 797 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2[] = 798 { 799 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoOffset), "Info Offset", 0}, 800 {ACPI_DMT_UINT32, ACPI_DBG2_OFFSET (InfoCount), "Info Count", 0}, 801 ACPI_DMT_TERMINATOR 802 }; 803 804 /* Debug Device Information Subtable */ 805 806 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Device[] = 807 { 808 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (Revision), "Revision", 0}, 809 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Length), "Length", DT_LENGTH}, 810 {ACPI_DMT_UINT8, ACPI_DBG20_OFFSET (RegisterCount), "Register Count", 0}, 811 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathLength), "Namepath Length", 0}, 812 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (NamepathOffset), "Namepath Offset", 0}, 813 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataLength), "OEM Data Length", DT_DESCRIBES_OPTIONAL}, 814 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (OemDataOffset), "OEM Data Offset", DT_DESCRIBES_OPTIONAL}, 815 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortType), "Port Type", 0}, 816 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (PortSubtype), "Port Subtype", 0}, 817 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (Reserved), "Reserved", 0}, 818 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (BaseAddressOffset), "Base Address Offset", 0}, 819 {ACPI_DMT_UINT16, ACPI_DBG20_OFFSET (AddressSizeOffset), "Address Size Offset", 0}, 820 ACPI_DMT_TERMINATOR 821 }; 822 823 /* Variable-length data for the subtable */ 824 825 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Addr[] = 826 { 827 {ACPI_DMT_GAS, 0, "Base Address Register", 0}, 828 ACPI_DMT_TERMINATOR 829 }; 830 831 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Size[] = 832 { 833 {ACPI_DMT_UINT32, 0, "Address Size", 0}, 834 ACPI_DMT_TERMINATOR 835 }; 836 837 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2Name[] = 838 { 839 {ACPI_DMT_STRING, 0, "Namepath", 0}, 840 ACPI_DMT_TERMINATOR 841 }; 842 843 ACPI_DMTABLE_INFO AcpiDmTableInfoDbg2OemData[] = 844 { 845 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", DT_OPTIONAL}, 846 ACPI_DMT_TERMINATOR 847 }; 848 849 850 /******************************************************************************* 851 * 852 * DBGP - Debug Port 853 * 854 ******************************************************************************/ 855 856 ACPI_DMTABLE_INFO AcpiDmTableInfoDbgp[] = 857 { 858 {ACPI_DMT_UINT8, ACPI_DBGP_OFFSET (Type), "Interface Type", 0}, 859 {ACPI_DMT_UINT24, ACPI_DBGP_OFFSET (Reserved[0]), "Reserved", 0}, 860 {ACPI_DMT_GAS, ACPI_DBGP_OFFSET (DebugPort), "Debug Port Register", 0}, 861 ACPI_DMT_TERMINATOR 862 }; 863 864 865 /******************************************************************************* 866 * 867 * DMAR - DMA Remapping table 868 * 869 ******************************************************************************/ 870 871 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar[] = 872 { 873 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Width), "Host Address Width", 0}, 874 {ACPI_DMT_UINT8, ACPI_DMAR_OFFSET (Flags), "Flags", 0}, 875 {ACPI_DMT_BUF10, ACPI_DMAR_OFFSET (Reserved[0]), "Reserved", 0}, 876 ACPI_DMT_TERMINATOR 877 }; 878 879 /* Common Subtable header (one per Subtable) */ 880 881 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarHdr[] = 882 { 883 {ACPI_DMT_DMAR, ACPI_DMAR0_OFFSET (Header.Type), "Subtable Type", 0}, 884 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Header.Length), "Length", DT_LENGTH}, 885 ACPI_DMT_TERMINATOR 886 }; 887 888 /* Common device scope entry */ 889 890 ACPI_DMTABLE_INFO AcpiDmTableInfoDmarScope[] = 891 { 892 {ACPI_DMT_DMAR_SCOPE, ACPI_DMARS_OFFSET (EntryType), "Device Scope Type", 0}, 893 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Length), "Entry Length", DT_LENGTH}, 894 {ACPI_DMT_UINT16, ACPI_DMARS_OFFSET (Reserved), "Reserved", 0}, 895 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (EnumerationId), "Enumeration ID", 0}, 896 {ACPI_DMT_UINT8, ACPI_DMARS_OFFSET (Bus), "PCI Bus Number", 0}, 897 ACPI_DMT_TERMINATOR 898 }; 899 900 /* DMAR Subtables */ 901 902 /* 0: Hardware Unit Definition */ 903 904 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar0[] = 905 { 906 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Flags), "Flags", 0}, 907 {ACPI_DMT_UINT8, ACPI_DMAR0_OFFSET (Reserved), "Reserved", 0}, 908 {ACPI_DMT_UINT16, ACPI_DMAR0_OFFSET (Segment), "PCI Segment Number", 0}, 909 {ACPI_DMT_UINT64, ACPI_DMAR0_OFFSET (Address), "Register Base Address", 0}, 910 ACPI_DMT_TERMINATOR 911 }; 912 913 /* 1: Reserved Memory Definition */ 914 915 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar1[] = 916 { 917 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Reserved), "Reserved", 0}, 918 {ACPI_DMT_UINT16, ACPI_DMAR1_OFFSET (Segment), "PCI Segment Number", 0}, 919 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (BaseAddress), "Base Address", 0}, 920 {ACPI_DMT_UINT64, ACPI_DMAR1_OFFSET (EndAddress), "End Address (limit)", 0}, 921 ACPI_DMT_TERMINATOR 922 }; 923 924 /* 2: Root Port ATS Capability Definition */ 925 926 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar2[] = 927 { 928 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Flags), "Flags", 0}, 929 {ACPI_DMT_UINT8, ACPI_DMAR2_OFFSET (Reserved), "Reserved", 0}, 930 {ACPI_DMT_UINT16, ACPI_DMAR2_OFFSET (Segment), "PCI Segment Number", 0}, 931 ACPI_DMT_TERMINATOR 932 }; 933 934 /* 3: Remapping Hardware Static Affinity Structure */ 935 936 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar3[] = 937 { 938 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (Reserved), "Reserved", 0}, 939 {ACPI_DMT_UINT64, ACPI_DMAR3_OFFSET (BaseAddress), "Base Address", 0}, 940 {ACPI_DMT_UINT32, ACPI_DMAR3_OFFSET (ProximityDomain), "Proximity Domain", 0}, 941 ACPI_DMT_TERMINATOR 942 }; 943 944 /* 4: ACPI Namespace Device Declaration Structure */ 945 946 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar4[] = 947 { 948 {ACPI_DMT_UINT24, ACPI_DMAR4_OFFSET (Reserved[0]), "Reserved", 0}, 949 {ACPI_DMT_UINT8, ACPI_DMAR4_OFFSET (DeviceNumber), "Device Number", 0}, 950 {ACPI_DMT_STRING, ACPI_DMAR4_OFFSET (DeviceName[0]), "Device Name", 0}, 951 ACPI_DMT_TERMINATOR 952 }; 953 954 /* 5: Hardware Unit Definition */ 955 956 ACPI_DMTABLE_INFO AcpiDmTableInfoDmar5[] = 957 { 958 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Flags), "Flags", 0}, 959 {ACPI_DMT_UINT8, ACPI_DMAR5_OFFSET (Reserved), "Reserved", 0}, 960 {ACPI_DMT_UINT16, ACPI_DMAR5_OFFSET (Segment), "PCI Segment Number", 0}, 961 ACPI_DMT_TERMINATOR 962 }; 963 964 /******************************************************************************* 965 * 966 * DRTM - Dynamic Root of Trust for Measurement table 967 * 968 ******************************************************************************/ 969 970 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm[] = 971 { 972 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryBaseAddress), "Entry Base Address", 0}, 973 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryLength), "Entry Length", 0}, 974 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (EntryAddress32), "Entry 32", 0}, 975 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (EntryAddress64), "Entry 64", 0}, 976 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ExitAddress), "Exit Address", 0}, 977 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (LogAreaAddress), "Log Area Start", 0}, 978 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (LogAreaLength), "Log Area Length", 0}, 979 {ACPI_DMT_UINT64, ACPI_DRTM_OFFSET (ArchDependentAddress), "Arch Dependent Address", 0}, 980 {ACPI_DMT_UINT32, ACPI_DRTM_OFFSET (Flags), "Flags (decoded below)", 0}, 981 {ACPI_DMT_FLAG0, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Namespace in TCB", 0}, 982 {ACPI_DMT_FLAG1, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on S3 Resume", 0}, 983 {ACPI_DMT_FLAG2, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "Gap Code on DLME_Exit", 0}, 984 {ACPI_DMT_FLAG3, ACPI_DRTM_FLAG_OFFSET (Flags, 0), "PCR_Authorities Changed", 0}, 985 ACPI_DMT_TERMINATOR 986 }; 987 988 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0[] = 989 { 990 {ACPI_DMT_UINT32, ACPI_DRTM0_OFFSET (ValidatedTableCount), "Validated Table Count", DT_COUNT}, 991 ACPI_DMT_TERMINATOR 992 }; 993 994 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm0a[] = 995 { 996 {ACPI_DMT_UINT64, 0, "Table Address", DT_OPTIONAL}, 997 ACPI_DMT_TERMINATOR 998 }; 999 1000 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1[] = 1001 { 1002 {ACPI_DMT_UINT32, ACPI_DRTM1_OFFSET (ResourceCount), "Resource Count", DT_COUNT}, 1003 ACPI_DMT_TERMINATOR 1004 }; 1005 1006 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm1a[] = 1007 { 1008 {ACPI_DMT_UINT56, ACPI_DRTM1a_OFFSET (Size[0]), "Size", DT_OPTIONAL}, 1009 {ACPI_DMT_UINT8, ACPI_DRTM1a_OFFSET (Type), "Type", 0}, 1010 {ACPI_DMT_FLAG0, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Resource Type", 0}, 1011 {ACPI_DMT_FLAG7, ACPI_DRTM1a_FLAG_OFFSET (Type, 0), "Protections", 0}, 1012 {ACPI_DMT_UINT64, ACPI_DRTM1a_OFFSET (Address), "Address", 0}, 1013 ACPI_DMT_TERMINATOR 1014 }; 1015 1016 ACPI_DMTABLE_INFO AcpiDmTableInfoDrtm2[] = 1017 { 1018 {ACPI_DMT_UINT32, ACPI_DRTM2_OFFSET (DpsIdLength), "DLME Platform Id Length", DT_COUNT}, 1019 {ACPI_DMT_BUF16, ACPI_DRTM2_OFFSET (DpsId), "DLME Platform Id", DT_COUNT}, 1020 ACPI_DMT_TERMINATOR 1021 }; 1022 1023 1024 /******************************************************************************* 1025 * 1026 * ECDT - Embedded Controller Boot Resources Table 1027 * 1028 ******************************************************************************/ 1029 1030 ACPI_DMTABLE_INFO AcpiDmTableInfoEcdt[] = 1031 { 1032 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Control), "Command/Status Register", 0}, 1033 {ACPI_DMT_GAS, ACPI_ECDT_OFFSET (Data), "Data Register", 0}, 1034 {ACPI_DMT_UINT32, ACPI_ECDT_OFFSET (Uid), "UID", 0}, 1035 {ACPI_DMT_UINT8, ACPI_ECDT_OFFSET (Gpe), "GPE Number", 0}, 1036 {ACPI_DMT_STRING, ACPI_ECDT_OFFSET (Id[0]), "Namepath", 0}, 1037 ACPI_DMT_TERMINATOR 1038 }; 1039 1040 1041 /******************************************************************************* 1042 * 1043 * EINJ - Error Injection table 1044 * 1045 ******************************************************************************/ 1046 1047 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj[] = 1048 { 1049 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (HeaderLength), "Injection Header Length", 0}, 1050 {ACPI_DMT_UINT8, ACPI_EINJ_OFFSET (Flags), "Flags", 0}, 1051 {ACPI_DMT_UINT24, ACPI_EINJ_OFFSET (Reserved[0]), "Reserved", 0}, 1052 {ACPI_DMT_UINT32, ACPI_EINJ_OFFSET (Entries), "Injection Entry Count", 0}, 1053 ACPI_DMT_TERMINATOR 1054 }; 1055 1056 ACPI_DMTABLE_INFO AcpiDmTableInfoEinj0[] = 1057 { 1058 {ACPI_DMT_EINJACT, ACPI_EINJ0_OFFSET (Action), "Action", 0}, 1059 {ACPI_DMT_EINJINST, ACPI_EINJ0_OFFSET (Instruction), "Instruction", 0}, 1060 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1061 {ACPI_DMT_FLAG0, ACPI_EINJ0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1062 1063 {ACPI_DMT_UINT8, ACPI_EINJ0_OFFSET (Reserved), "Reserved", 0}, 1064 {ACPI_DMT_GAS, ACPI_EINJ0_OFFSET (RegisterRegion), "Register Region", 0}, 1065 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Value), "Value", 0}, 1066 {ACPI_DMT_UINT64, ACPI_EINJ0_OFFSET (Mask), "Mask", 0}, 1067 ACPI_DMT_TERMINATOR 1068 }; 1069 1070 1071 /******************************************************************************* 1072 * 1073 * ERST - Error Record Serialization table 1074 * 1075 ******************************************************************************/ 1076 1077 ACPI_DMTABLE_INFO AcpiDmTableInfoErst[] = 1078 { 1079 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (HeaderLength), "Serialization Header Length", 0}, 1080 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Reserved), "Reserved", 0}, 1081 {ACPI_DMT_UINT32, ACPI_ERST_OFFSET (Entries), "Instruction Entry Count", 0}, 1082 ACPI_DMT_TERMINATOR 1083 }; 1084 1085 ACPI_DMTABLE_INFO AcpiDmTableInfoErst0[] = 1086 { 1087 {ACPI_DMT_ERSTACT, ACPI_ERST0_OFFSET (Action), "Action", 0}, 1088 {ACPI_DMT_ERSTINST, ACPI_ERST0_OFFSET (Instruction), "Instruction", 0}, 1089 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1090 {ACPI_DMT_FLAG0, ACPI_ERST0_FLAG_OFFSET (Flags,0), "Preserve Register Bits", 0}, 1091 1092 {ACPI_DMT_UINT8, ACPI_ERST0_OFFSET (Reserved), "Reserved", 0}, 1093 {ACPI_DMT_GAS, ACPI_ERST0_OFFSET (RegisterRegion), "Register Region", 0}, 1094 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Value), "Value", 0}, 1095 {ACPI_DMT_UINT64, ACPI_ERST0_OFFSET (Mask), "Mask", 0}, 1096 ACPI_DMT_TERMINATOR 1097 }; 1098 1099 1100 /******************************************************************************* 1101 * 1102 * FPDT - Firmware Performance Data Table (ACPI 5.0) 1103 * 1104 ******************************************************************************/ 1105 1106 /* Main table consists of only the standard ACPI header - subtables follow */ 1107 1108 /* FPDT subtable header */ 1109 1110 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdtHdr[] = 1111 { 1112 {ACPI_DMT_UINT16, ACPI_FPDTH_OFFSET (Type), "Subtable Type", 0}, 1113 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Length), "Length", DT_LENGTH}, 1114 {ACPI_DMT_UINT8, ACPI_FPDTH_OFFSET (Revision), "Revision", 0}, 1115 ACPI_DMT_TERMINATOR 1116 }; 1117 1118 /* 0: Firmware Basic Boot Performance Record */ 1119 1120 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt0[] = 1121 { 1122 {ACPI_DMT_UINT32, ACPI_FPDT0_OFFSET (Reserved), "Reserved", 0}, 1123 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "FPDT Boot Record Address", 0}, 1124 ACPI_DMT_TERMINATOR 1125 }; 1126 1127 /* 1: S3 Performance Table Pointer Record */ 1128 1129 ACPI_DMTABLE_INFO AcpiDmTableInfoFpdt1[] = 1130 { 1131 {ACPI_DMT_UINT32, ACPI_FPDT1_OFFSET (Reserved), "Reserved", 0}, 1132 {ACPI_DMT_UINT64, ACPI_FPDT1_OFFSET (Address), "S3PT Record Address", 0}, 1133 ACPI_DMT_TERMINATOR 1134 }; 1135 1136 #if 0 1137 /* Boot Performance Record, not supported at this time. */ 1138 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ResetEnd), "Reset End", 0}, 1139 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (LoadStart), "Load Image Start", 0}, 1140 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (StartupStart), "Start Image Start", 0}, 1141 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesEntry), "Exit Services Entry", 0}, 1142 {ACPI_DMT_UINT64, ACPI_FPDT0_OFFSET (ExitServicesExit), "Exit Services Exit", 0}, 1143 #endif 1144 1145 1146 /******************************************************************************* 1147 * 1148 * GTDT - Generic Timer Description Table 1149 * 1150 ******************************************************************************/ 1151 1152 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt[] = 1153 { 1154 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterBlockAddresss), "Counter Block Address", 0}, 1155 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (Reserved), "Reserved", 0}, 1156 ACPI_DMT_NEW_LINE, 1157 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Interrupt), "Secure EL1 Interrupt", 0}, 1158 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (SecureEl1Flags), "EL1 Flags (decoded below)", DT_FLAG}, 1159 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Trigger Mode", 0}, 1160 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Polarity", 0}, 1161 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (SecureEl1Flags,0), "Always On", 0}, 1162 ACPI_DMT_NEW_LINE, 1163 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Interrupt), "Non-Secure EL1 Interrupt", 0}, 1164 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl1Flags), "NEL1 Flags (decoded below)", DT_FLAG}, 1165 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Trigger Mode", 0}, 1166 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Polarity", 0}, 1167 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl1Flags,0),"Always On", 0}, 1168 ACPI_DMT_NEW_LINE, 1169 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1170 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (VirtualTimerFlags), "VT Flags (decoded below)", DT_FLAG}, 1171 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Trigger Mode", 0}, 1172 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Polarity", 0}, 1173 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (VirtualTimerFlags,0),"Always On", 0}, 1174 ACPI_DMT_NEW_LINE, 1175 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Interrupt), "Non-Secure EL2 Interrupt", 0}, 1176 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (NonSecureEl2Flags), "NEL2 Flags (decoded below)", DT_FLAG}, 1177 {ACPI_DMT_FLAG0, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Trigger Mode", 0}, 1178 {ACPI_DMT_FLAG1, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Polarity", 0}, 1179 {ACPI_DMT_FLAG2, ACPI_GTDT_FLAG_OFFSET (NonSecureEl2Flags,0),"Always On", 0}, 1180 {ACPI_DMT_UINT64, ACPI_GTDT_OFFSET (CounterReadBlockAddress), "Counter Read Block Address", 0}, 1181 ACPI_DMT_NEW_LINE, 1182 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerCount), "Platform Timer Count", 0}, 1183 {ACPI_DMT_UINT32, ACPI_GTDT_OFFSET (PlatformTimerOffset), "Platform Timer Offset", 0}, 1184 ACPI_DMT_TERMINATOR 1185 }; 1186 1187 /* GDTD EL2 timer info. This table is appended to AcpiDmTableInfoGtdt for rev 3 and later */ 1188 1189 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtEl2[] = 1190 { 1191 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerGsiv), "Virtual EL2 Timer GSIV", 0}, 1192 {ACPI_DMT_UINT32, ACPI_GTDT_EL2_OFFSET (VirtualEL2TimerFlags), "Virtual EL2 Timer Flags", 0}, 1193 ACPI_DMT_TERMINATOR 1194 }; 1195 1196 /* GTDT Subtable header (one per Subtable) */ 1197 1198 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdtHdr[] = 1199 { 1200 {ACPI_DMT_GTDT, ACPI_GTDTH_OFFSET (Type), "Subtable Type", 0}, 1201 {ACPI_DMT_UINT16, ACPI_GTDTH_OFFSET (Length), "Length", DT_LENGTH}, 1202 ACPI_DMT_TERMINATOR 1203 }; 1204 1205 /* GTDT Subtables */ 1206 1207 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0[] = 1208 { 1209 {ACPI_DMT_UINT8, ACPI_GTDT0_OFFSET (Reserved), "Reserved", 0}, 1210 {ACPI_DMT_UINT64, ACPI_GTDT0_OFFSET (BlockAddress), "Block Address", 0}, 1211 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerCount), "Timer Count", 0}, 1212 {ACPI_DMT_UINT32, ACPI_GTDT0_OFFSET (TimerOffset), "Timer Offset", 0}, 1213 ACPI_DMT_TERMINATOR 1214 }; 1215 1216 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt0a[] = 1217 { 1218 {ACPI_DMT_UINT8 , ACPI_GTDT0a_OFFSET (FrameNumber), "Frame Number", 0}, 1219 {ACPI_DMT_UINT24, ACPI_GTDT0a_OFFSET (Reserved[0]), "Reserved", 0}, 1220 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (BaseAddress), "Base Address", 0}, 1221 {ACPI_DMT_UINT64, ACPI_GTDT0a_OFFSET (El0BaseAddress), "EL0 Base Address", 0}, 1222 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1223 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (TimerFlags), "Timer Flags (decoded below)", 0}, 1224 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1225 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1226 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerInterrupt), "Virtual Timer Interrupt", 0}, 1227 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (VirtualTimerFlags), "Virtual Timer Flags (decoded below)", 0}, 1228 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Trigger Mode", 0}, 1229 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (VirtualTimerFlags,0), "Polarity", 0}, 1230 {ACPI_DMT_UINT32, ACPI_GTDT0a_OFFSET (CommonFlags), "Common Flags (decoded below)", 0}, 1231 {ACPI_DMT_FLAG0, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Secure", 0}, 1232 {ACPI_DMT_FLAG1, ACPI_GTDT0a_FLAG_OFFSET (CommonFlags,0), "Always On", 0}, 1233 ACPI_DMT_TERMINATOR 1234 }; 1235 1236 ACPI_DMTABLE_INFO AcpiDmTableInfoGtdt1[] = 1237 { 1238 {ACPI_DMT_UINT8, ACPI_GTDT1_OFFSET (Reserved), "Reserved", 0}, 1239 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (RefreshFrameAddress), "Refresh Frame Address", 0}, 1240 {ACPI_DMT_UINT64, ACPI_GTDT1_OFFSET (ControlFrameAddress), "Control Frame Address", 0}, 1241 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerInterrupt), "Timer Interrupt", 0}, 1242 {ACPI_DMT_UINT32, ACPI_GTDT1_OFFSET (TimerFlags), "Timer Flags (decoded below)", DT_FLAG}, 1243 {ACPI_DMT_FLAG0, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Trigger Mode", 0}, 1244 {ACPI_DMT_FLAG1, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Polarity", 0}, 1245 {ACPI_DMT_FLAG2, ACPI_GTDT1_FLAG_OFFSET (TimerFlags,0), "Security", 0}, 1246 ACPI_DMT_TERMINATOR 1247 }; 1248 1249 1250 /******************************************************************************* 1251 * 1252 * HEST - Hardware Error Source table 1253 * 1254 ******************************************************************************/ 1255 1256 ACPI_DMTABLE_INFO AcpiDmTableInfoHest[] = 1257 { 1258 {ACPI_DMT_UINT32, ACPI_HEST_OFFSET (ErrorSourceCount), "Error Source Count", 0}, 1259 ACPI_DMT_TERMINATOR 1260 }; 1261 1262 /* Common HEST structures for subtables */ 1263 1264 #define ACPI_DM_HEST_HEADER \ 1265 {ACPI_DMT_HEST, ACPI_HEST0_OFFSET (Header.Type), "Subtable Type", 0}, \ 1266 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Header.SourceId), "Source Id", 0} 1267 1268 #define ACPI_DM_HEST_AER \ 1269 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved1), "Reserved", 0}, \ 1270 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Flags), "Flags (decoded below)", DT_FLAG}, \ 1271 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Firmware First", 0}, \ 1272 {ACPI_DMT_FLAG0, ACPI_HEST6_FLAG_OFFSET (Aer.Flags,0), "Global", 0}, \ 1273 {ACPI_DMT_UINT8, ACPI_HEST6_OFFSET (Aer.Enabled), "Enabled", 0}, \ 1274 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.RecordsToPreallocate), "Records To Preallocate", 0}, \ 1275 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.MaxSectionsPerRecord), "Max Sections Per Record", 0}, \ 1276 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.Bus), "Bus", 0}, \ 1277 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Device), "Device", 0}, \ 1278 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Function), "Function", 0}, \ 1279 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.DeviceControl), "DeviceControl", 0}, \ 1280 {ACPI_DMT_UINT16, ACPI_HEST6_OFFSET (Aer.Reserved2), "Reserved", 0}, \ 1281 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableMask), "Uncorrectable Mask", 0}, \ 1282 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.UncorrectableSeverity), "Uncorrectable Severity", 0}, \ 1283 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.CorrectableMask), "Correctable Mask", 0}, \ 1284 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (Aer.AdvancedCapabilities), "Advanced Capabilities", 0} 1285 1286 1287 /* HEST Subtables */ 1288 1289 /* 0: IA32 Machine Check Exception */ 1290 1291 ACPI_DMTABLE_INFO AcpiDmTableInfoHest0[] = 1292 { 1293 ACPI_DM_HEST_HEADER, 1294 {ACPI_DMT_UINT16, ACPI_HEST0_OFFSET (Reserved1), "Reserved1", 0}, 1295 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1296 {ACPI_DMT_FLAG0, ACPI_HEST0_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1297 {ACPI_DMT_FLAG2, ACPI_HEST0_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1298 1299 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (Enabled), "Enabled", 0}, 1300 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1301 {ACPI_DMT_UINT32, ACPI_HEST0_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1302 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalCapabilityData), "Global Capability Data", 0}, 1303 {ACPI_DMT_UINT64, ACPI_HEST0_OFFSET (GlobalControlData), "Global Control Data", 0}, 1304 {ACPI_DMT_UINT8, ACPI_HEST0_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1305 {ACPI_DMT_UINT56, ACPI_HEST0_OFFSET (Reserved3[0]), "Reserved2", 0}, 1306 ACPI_DMT_TERMINATOR 1307 }; 1308 1309 /* 1: IA32 Corrected Machine Check */ 1310 1311 ACPI_DMTABLE_INFO AcpiDmTableInfoHest1[] = 1312 { 1313 ACPI_DM_HEST_HEADER, 1314 {ACPI_DMT_UINT16, ACPI_HEST1_OFFSET (Reserved1), "Reserved1", 0}, 1315 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1316 {ACPI_DMT_FLAG0, ACPI_HEST1_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1317 {ACPI_DMT_FLAG2, ACPI_HEST1_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1318 1319 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (Enabled), "Enabled", 0}, 1320 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1321 {ACPI_DMT_UINT32, ACPI_HEST1_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1322 {ACPI_DMT_HESTNTFY, ACPI_HEST1_OFFSET (Notify), "Notify", 0}, 1323 {ACPI_DMT_UINT8, ACPI_HEST1_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1324 {ACPI_DMT_UINT24, ACPI_HEST1_OFFSET (Reserved2[0]), "Reserved2", 0}, 1325 ACPI_DMT_TERMINATOR 1326 }; 1327 1328 /* 2: IA32 Non-Maskable Interrupt */ 1329 1330 ACPI_DMTABLE_INFO AcpiDmTableInfoHest2[] = 1331 { 1332 ACPI_DM_HEST_HEADER, 1333 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (Reserved), "Reserved", 0}, 1334 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1335 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1336 {ACPI_DMT_UINT32, ACPI_HEST2_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1337 ACPI_DMT_TERMINATOR 1338 }; 1339 1340 /* 6: PCI Express Root Port AER */ 1341 1342 ACPI_DMTABLE_INFO AcpiDmTableInfoHest6[] = 1343 { 1344 ACPI_DM_HEST_HEADER, 1345 ACPI_DM_HEST_AER, 1346 {ACPI_DMT_UINT32, ACPI_HEST6_OFFSET (RootErrorCommand), "Root Error Command", 0}, 1347 ACPI_DMT_TERMINATOR 1348 }; 1349 1350 /* 7: PCI Express AER (AER Endpoint) */ 1351 1352 ACPI_DMTABLE_INFO AcpiDmTableInfoHest7[] = 1353 { 1354 ACPI_DM_HEST_HEADER, 1355 ACPI_DM_HEST_AER, 1356 ACPI_DMT_TERMINATOR 1357 }; 1358 1359 /* 8: PCI Express/PCI-X Bridge AER */ 1360 1361 ACPI_DMTABLE_INFO AcpiDmTableInfoHest8[] = 1362 { 1363 ACPI_DM_HEST_HEADER, 1364 ACPI_DM_HEST_AER, 1365 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableMask2), "2nd Uncorrectable Mask", 0}, 1366 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (UncorrectableSeverity2), "2nd Uncorrectable Severity", 0}, 1367 {ACPI_DMT_UINT32, ACPI_HEST8_OFFSET (AdvancedCapabilities2), "2nd Advanced Capabilities", 0}, 1368 ACPI_DMT_TERMINATOR 1369 }; 1370 1371 /* 9: Generic Hardware Error Source */ 1372 1373 ACPI_DMTABLE_INFO AcpiDmTableInfoHest9[] = 1374 { 1375 ACPI_DM_HEST_HEADER, 1376 {ACPI_DMT_UINT16, ACPI_HEST9_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1377 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Reserved), "Reserved", 0}, 1378 {ACPI_DMT_UINT8, ACPI_HEST9_OFFSET (Enabled), "Enabled", 0}, 1379 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1380 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1381 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1382 {ACPI_DMT_GAS, ACPI_HEST9_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1383 {ACPI_DMT_HESTNTFY, ACPI_HEST9_OFFSET (Notify), "Notify", 0}, 1384 {ACPI_DMT_UINT32, ACPI_HEST9_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1385 ACPI_DMT_TERMINATOR 1386 }; 1387 1388 /* 10: Generic Hardware Error Source - Version 2 */ 1389 1390 ACPI_DMTABLE_INFO AcpiDmTableInfoHest10[] = 1391 { 1392 ACPI_DM_HEST_HEADER, 1393 {ACPI_DMT_UINT16, ACPI_HEST10_OFFSET (RelatedSourceId), "Related Source Id", 0}, 1394 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Reserved), "Reserved", 0}, 1395 {ACPI_DMT_UINT8, ACPI_HEST10_OFFSET (Enabled), "Enabled", 0}, 1396 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1397 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1398 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (MaxRawDataLength), "Max Raw Data Length", 0}, 1399 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ErrorStatusAddress), "Error Status Address", 0}, 1400 {ACPI_DMT_HESTNTFY, ACPI_HEST10_OFFSET (Notify), "Notify", 0}, 1401 {ACPI_DMT_UINT32, ACPI_HEST10_OFFSET (ErrorBlockLength), "Error Status Block Length", 0}, 1402 {ACPI_DMT_GAS, ACPI_HEST10_OFFSET (ReadAckRegister), "Read Ack Register", 0}, 1403 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckPreserve), "Read Ack Preserve", 0}, 1404 {ACPI_DMT_UINT64, ACPI_HEST10_OFFSET (ReadAckWrite), "Read Ack Write", 0}, 1405 ACPI_DMT_TERMINATOR 1406 }; 1407 1408 /* 11: IA32 Deferred Machine Check */ 1409 1410 ACPI_DMTABLE_INFO AcpiDmTableInfoHest11[] = 1411 { 1412 ACPI_DM_HEST_HEADER, 1413 {ACPI_DMT_UINT16, ACPI_HEST11_OFFSET (Reserved1), "Reserved1", 0}, 1414 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1415 {ACPI_DMT_FLAG0, ACPI_HEST11_FLAG_OFFSET (Flags,0), "Firmware First", 0}, 1416 {ACPI_DMT_FLAG2, ACPI_HEST11_FLAG_OFFSET (Flags,0), "GHES Assist", 0}, 1417 1418 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (Enabled), "Enabled", 0}, 1419 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (RecordsToPreallocate), "Records To Preallocate", 0}, 1420 {ACPI_DMT_UINT32, ACPI_HEST11_OFFSET (MaxSectionsPerRecord), "Max Sections Per Record", 0}, 1421 {ACPI_DMT_HESTNTFY, ACPI_HEST11_OFFSET (Notify), "Notify", 0}, 1422 {ACPI_DMT_UINT8, ACPI_HEST11_OFFSET (NumHardwareBanks), "Num Hardware Banks", 0}, 1423 {ACPI_DMT_UINT24, ACPI_HEST11_OFFSET (Reserved2[0]), "Reserved2", 0}, 1424 ACPI_DMT_TERMINATOR 1425 }; 1426 1427 /* Notification Structure */ 1428 1429 ACPI_DMTABLE_INFO AcpiDmTableInfoHestNotify[] = 1430 { 1431 {ACPI_DMT_HESTNTYP, ACPI_HESTN_OFFSET (Type), "Notify Type", 0}, 1432 {ACPI_DMT_UINT8, ACPI_HESTN_OFFSET (Length), "Notify Length", DT_LENGTH}, 1433 {ACPI_DMT_UINT16, ACPI_HESTN_OFFSET (ConfigWriteEnable), "Configuration Write Enable", 0}, 1434 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollInterval), "PollInterval", 0}, 1435 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (Vector), "Vector", 0}, 1436 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdValue), "Polling Threshold Value", 0}, 1437 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (PollingThresholdWindow), "Polling Threshold Window", 0}, 1438 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdValue), "Error Threshold Value", 0}, 1439 {ACPI_DMT_UINT32, ACPI_HESTN_OFFSET (ErrorThresholdWindow), "Error Threshold Window", 0}, 1440 ACPI_DMT_TERMINATOR 1441 }; 1442 1443 1444 /* 1445 * IA32 Error Bank(s) - Follows the ACPI_HEST_IA_MACHINE_CHECK and 1446 * ACPI_HEST_IA_CORRECTED structures. 1447 */ 1448 ACPI_DMTABLE_INFO AcpiDmTableInfoHestBank[] = 1449 { 1450 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (BankNumber), "Bank Number", 0}, 1451 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (ClearStatusOnInit), "Clear Status On Init", 0}, 1452 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (StatusFormat), "Status Format", 0}, 1453 {ACPI_DMT_UINT8, ACPI_HESTB_OFFSET (Reserved), "Reserved", 0}, 1454 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (ControlRegister), "Control Register", 0}, 1455 {ACPI_DMT_UINT64, ACPI_HESTB_OFFSET (ControlData), "Control Data", 0}, 1456 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (StatusRegister), "Status Register", 0}, 1457 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (AddressRegister), "Address Register", 0}, 1458 {ACPI_DMT_UINT32, ACPI_HESTB_OFFSET (MiscRegister), "Misc Register", 0}, 1459 ACPI_DMT_TERMINATOR 1460 }; 1461 1462 1463 /******************************************************************************* 1464 * 1465 * HMAT - Heterogeneous Memory Attributes Table 1466 * 1467 ******************************************************************************/ 1468 1469 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat[] = 1470 { 1471 {ACPI_DMT_UINT32, ACPI_HMAT_OFFSET (Reserved), "Reserved", 0}, 1472 ACPI_DMT_TERMINATOR 1473 }; 1474 1475 /* Common HMAT structure header (one per Subtable) */ 1476 1477 ACPI_DMTABLE_INFO AcpiDmTableInfoHmatHdr[] = 1478 { 1479 {ACPI_DMT_HMAT, ACPI_HMATH_OFFSET (Type), "Structure Type", 0}, 1480 {ACPI_DMT_UINT16, ACPI_HMATH_OFFSET (Reserved), "Reserved", 0}, 1481 {ACPI_DMT_UINT32, ACPI_HMATH_OFFSET (Length), "Length", 0}, 1482 ACPI_DMT_TERMINATOR 1483 }; 1484 1485 /* HMAT subtables */ 1486 1487 /* 0x00: Memory proximity domain attributes */ 1488 1489 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat0[] = 1490 { 1491 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1492 {ACPI_DMT_FLAG0, ACPI_HMAT0_FLAG_OFFSET (Flags,0), "Processor Proximity Domain Valid", 0}, 1493 {ACPI_DMT_UINT16, ACPI_HMAT0_OFFSET (Reserved1), "Reserved1", 0}, 1494 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (InitiatorPD), "Attached Initiator Proximity Domain", 0}, 1495 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1496 {ACPI_DMT_UINT32, ACPI_HMAT0_OFFSET (Reserved2), "Reserved2", 0}, 1497 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved3), "Reserved3", 0}, 1498 {ACPI_DMT_UINT64, ACPI_HMAT0_OFFSET (Reserved4), "Reserved4", 0}, 1499 ACPI_DMT_TERMINATOR 1500 }; 1501 1502 /* 0x01: System Locality Latency and Bandwidth Information */ 1503 1504 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1[] = 1505 { 1506 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1507 {ACPI_DMT_FLAGS4_0, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Memory Hierarchy", 0}, /* First 4 bits */ 1508 {ACPI_DMT_FLAG4, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Use Minimum Transfer Size", 0}, 1509 {ACPI_DMT_FLAG5, ACPI_HMAT1_FLAG_OFFSET (Flags,0), "Non-sequential Transfers", 0}, 1510 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (DataType), "Data Type", 0}, 1511 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (MinTransferSize), "Minimum Transfer Size", 0}, 1512 {ACPI_DMT_UINT8, ACPI_HMAT1_OFFSET (Reserved1), "Reserved1", 0}, 1513 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfInitiatorPDs), "Initiator Proximity Domains #", 0}, 1514 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (NumberOfTargetPDs), "Target Proximity Domains #", 0}, 1515 {ACPI_DMT_UINT32, ACPI_HMAT1_OFFSET (Reserved2), "Reserved2", 0}, 1516 {ACPI_DMT_UINT64, ACPI_HMAT1_OFFSET (EntryBaseUnit), "Entry Base Unit", 0}, 1517 ACPI_DMT_TERMINATOR 1518 }; 1519 1520 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1a[] = 1521 { 1522 {ACPI_DMT_UINT32, 0, "Initiator Proximity Domain List", DT_OPTIONAL}, 1523 ACPI_DMT_TERMINATOR 1524 }; 1525 1526 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1b[] = 1527 { 1528 {ACPI_DMT_UINT32, 0, "Target Proximity Domain List", DT_OPTIONAL}, 1529 ACPI_DMT_TERMINATOR 1530 }; 1531 1532 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat1c[] = 1533 { 1534 {ACPI_DMT_UINT16, 0, "Entry", DT_OPTIONAL}, 1535 ACPI_DMT_TERMINATOR 1536 }; 1537 1538 /* 0x02: Memory Side Cache Information */ 1539 1540 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2[] = 1541 { 1542 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (MemoryPD), "Memory Proximity Domain", 0}, 1543 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (Reserved1), "Reserved1", 0}, 1544 {ACPI_DMT_UINT64, ACPI_HMAT2_OFFSET (CacheSize), "Memory Side Cache Size", 0}, 1545 {ACPI_DMT_UINT32, ACPI_HMAT2_OFFSET (CacheAttributes), "Cache Attributes (decoded below)", 0}, 1546 {ACPI_DMT_FLAGS4_0, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Total Cache Levels", 0}, 1547 {ACPI_DMT_FLAGS4_4, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Level", 0}, 1548 {ACPI_DMT_FLAGS4_8, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Associativity", 0}, 1549 {ACPI_DMT_FLAGS4_12, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Write Policy", 0}, 1550 {ACPI_DMT_FLAGS16_16, ACPI_HMAT2_FLAG_OFFSET (CacheAttributes,0), "Cache Line Size", 0}, 1551 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (Reserved2), "Reserved2", 0}, 1552 {ACPI_DMT_UINT16, ACPI_HMAT2_OFFSET (NumberOfSMBIOSHandles), "SMBIOS Handle #", 0}, 1553 ACPI_DMT_TERMINATOR 1554 }; 1555 1556 ACPI_DMTABLE_INFO AcpiDmTableInfoHmat2a[] = 1557 { 1558 {ACPI_DMT_UINT16, 0, "SMBIOS Handle", DT_OPTIONAL}, 1559 ACPI_DMT_TERMINATOR 1560 }; 1561 1562 1563 /******************************************************************************* 1564 * 1565 * HPET - High Precision Event Timer table 1566 * 1567 ******************************************************************************/ 1568 1569 ACPI_DMTABLE_INFO AcpiDmTableInfoHpet[] = 1570 { 1571 {ACPI_DMT_UINT32, ACPI_HPET_OFFSET (Id), "Hardware Block ID", 0}, 1572 {ACPI_DMT_GAS, ACPI_HPET_OFFSET (Address), "Timer Block Register", 0}, 1573 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Sequence), "Sequence Number", 0}, 1574 {ACPI_DMT_UINT16, ACPI_HPET_OFFSET (MinimumTick), "Minimum Clock Ticks", 0}, 1575 {ACPI_DMT_UINT8, ACPI_HPET_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1576 {ACPI_DMT_FLAG0, ACPI_HPET_FLAG_OFFSET (Flags,0), "4K Page Protect", 0}, 1577 {ACPI_DMT_FLAG1, ACPI_HPET_FLAG_OFFSET (Flags,0), "64K Page Protect", 0}, 1578 ACPI_DMT_TERMINATOR 1579 }; 1580 /*! [End] no source code translation !*/ 1581