1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const Builtin::Info BuiltinInfo[]; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasMMA = false; 62 bool HasROPProtect = false; 63 bool HasPrivileged = false; 64 bool HasVSX = false; 65 bool HasP8Vector = false; 66 bool HasP8Crypto = false; 67 bool HasDirectMove = false; 68 bool HasHTM = false; 69 bool HasBPERMD = false; 70 bool HasExtDiv = false; 71 bool HasP9Vector = false; 72 bool HasSPE = false; 73 bool PairedVectorMemops = false; 74 bool HasP10Vector = false; 75 bool HasPCRelativeMemops = false; 76 bool HasPrefixInstrs = false; 77 78 protected: 79 std::string ABI; 80 81 public: PPCTargetInfo(const llvm::Triple & Triple,const TargetOptions &)82 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 83 : TargetInfo(Triple) { 84 SuitableAlign = 128; 85 SimdDefaultAlign = 128; 86 LongDoubleWidth = LongDoubleAlign = 128; 87 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 88 HasStrictFP = true; 89 } 90 91 // Set the language option for altivec based on our value. 92 void adjust(LangOptions &Opts) override; 93 94 // Note: GCC recognizes the following additional cpus: 95 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 96 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 97 bool isValidCPUName(StringRef Name) const override; 98 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 99 setCPU(const std::string & Name)100 bool setCPU(const std::string &Name) override { 101 bool CPUKnown = isValidCPUName(Name); 102 if (CPUKnown) { 103 CPU = Name; 104 105 // CPU identification. 106 ArchDefs = 107 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 108 .Case("440", ArchDefineName) 109 .Case("450", ArchDefineName | ArchDefine440) 110 .Case("601", ArchDefineName) 111 .Case("602", ArchDefineName | ArchDefinePpcgr) 112 .Case("603", ArchDefineName | ArchDefinePpcgr) 113 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 114 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 115 .Case("604", ArchDefineName | ArchDefinePpcgr) 116 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 117 .Case("620", ArchDefineName | ArchDefinePpcgr) 118 .Case("630", ArchDefineName | ArchDefinePpcgr) 119 .Case("7400", ArchDefineName | ArchDefinePpcgr) 120 .Case("7450", ArchDefineName | ArchDefinePpcgr) 121 .Case("750", ArchDefineName | ArchDefinePpcgr) 122 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 123 ArchDefinePpcsq) 124 .Case("a2", ArchDefineA2) 125 .Cases("power3", "pwr3", ArchDefinePpcgr) 126 .Cases("power4", "pwr4", 127 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 128 .Cases("power5", "pwr5", 129 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 130 ArchDefinePpcsq) 131 .Cases("power5x", "pwr5x", 132 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 133 ArchDefinePpcgr | ArchDefinePpcsq) 134 .Cases("power6", "pwr6", 135 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 136 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 137 .Cases("power6x", "pwr6x", 138 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 139 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 140 ArchDefinePpcsq) 141 .Cases("power7", "pwr7", 142 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 143 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 144 ArchDefinePpcsq) 145 // powerpc64le automatically defaults to at least power8. 146 .Cases("power8", "pwr8", "ppc64le", 147 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 148 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 149 ArchDefinePpcgr | ArchDefinePpcsq) 150 .Cases("power9", "pwr9", 151 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 152 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 153 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 154 .Cases("power10", "pwr10", 155 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 156 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 157 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 158 ArchDefinePpcsq) 159 .Case("future", 160 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 161 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 162 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 163 ArchDefinePpcgr | ArchDefinePpcsq) 164 .Cases("8548", "e500", ArchDefineE500) 165 .Default(ArchDefineNone); 166 } 167 return CPUKnown; 168 } 169 getABI()170 StringRef getABI() const override { return ABI; } 171 172 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 173 isCLZForZeroUndef()174 bool isCLZForZeroUndef() const override { return false; } 175 176 void getTargetDefines(const LangOptions &Opts, 177 MacroBuilder &Builder) const override; 178 179 bool 180 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 181 StringRef CPU, 182 const std::vector<std::string> &FeaturesVec) const override; 183 184 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 185 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 186 187 bool handleTargetFeatures(std::vector<std::string> &Features, 188 DiagnosticsEngine &Diags) override; 189 190 bool hasFeature(StringRef Feature) const override; 191 192 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 193 bool Enabled) const override; 194 195 ArrayRef<const char *> getGCCRegNames() const override; 196 197 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 198 199 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 200 validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info)201 bool validateAsmConstraint(const char *&Name, 202 TargetInfo::ConstraintInfo &Info) const override { 203 switch (*Name) { 204 default: 205 return false; 206 case 'O': // Zero 207 break; 208 case 'f': // Floating point register 209 // Don't use floating point registers on soft float ABI. 210 if (FloatABI == SoftFloat) 211 return false; 212 LLVM_FALLTHROUGH; 213 case 'b': // Base register 214 Info.setAllowsRegister(); 215 break; 216 // FIXME: The following are added to allow parsing. 217 // I just took a guess at what the actions should be. 218 // Also, is more specific checking needed? I.e. specific registers? 219 case 'd': // Floating point register (containing 64-bit value) 220 case 'v': // Altivec vector register 221 // Don't use floating point and altivec vector registers 222 // on soft float ABI 223 if (FloatABI == SoftFloat) 224 return false; 225 Info.setAllowsRegister(); 226 break; 227 case 'w': 228 switch (Name[1]) { 229 case 'd': // VSX vector register to hold vector double data 230 case 'f': // VSX vector register to hold vector float data 231 case 's': // VSX vector register to hold scalar double data 232 case 'w': // VSX vector register to hold scalar double data 233 case 'a': // Any VSX register 234 case 'c': // An individual CR bit 235 case 'i': // FP or VSX register to hold 64-bit integers data 236 break; 237 default: 238 return false; 239 } 240 Info.setAllowsRegister(); 241 Name++; // Skip over 'w'. 242 break; 243 case 'h': // `MQ', `CTR', or `LINK' register 244 case 'q': // `MQ' register 245 case 'c': // `CTR' register 246 case 'l': // `LINK' register 247 case 'x': // `CR' register (condition register) number 0 248 case 'y': // `CR' register (condition register) 249 case 'z': // `XER[CA]' carry bit (part of the XER register) 250 Info.setAllowsRegister(); 251 break; 252 case 'I': // Signed 16-bit constant 253 case 'J': // Unsigned 16-bit constant shifted left 16 bits 254 // (use `L' instead for SImode constants) 255 case 'K': // Unsigned 16-bit constant 256 case 'L': // Signed 16-bit constant shifted left 16 bits 257 case 'M': // Constant larger than 31 258 case 'N': // Exact power of 2 259 case 'P': // Constant whose negation is a signed 16-bit constant 260 case 'G': // Floating point constant that can be loaded into a 261 // register with one instruction per word 262 case 'H': // Integer/Floating point constant that can be loaded 263 // into a register using three instructions 264 break; 265 case 'm': // Memory operand. Note that on PowerPC targets, m can 266 // include addresses that update the base register. It 267 // is therefore only safe to use `m' in an asm statement 268 // if that asm statement accesses the operand exactly once. 269 // The asm statement must also use `%U<opno>' as a 270 // placeholder for the "update" flag in the corresponding 271 // load or store instruction. For example: 272 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 273 // is correct but: 274 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 275 // is not. Use es rather than m if you don't want the base 276 // register to be updated. 277 case 'e': 278 if (Name[1] != 's') 279 return false; 280 // es: A "stable" memory operand; that is, one which does not 281 // include any automodification of the base register. Unlike 282 // `m', this constraint can be used in asm statements that 283 // might access the operand several times, or that might not 284 // access it at all. 285 Info.setAllowsMemory(); 286 Name++; // Skip over 'e'. 287 break; 288 case 'Q': // Memory operand that is an offset from a register (it is 289 // usually better to use `m' or `es' in asm statements) 290 Info.setAllowsRegister(); 291 LLVM_FALLTHROUGH; 292 case 'Z': // Memory operand that is an indexed or indirect from a 293 // register (it is usually better to use `m' or `es' in 294 // asm statements) 295 Info.setAllowsMemory(); 296 break; 297 case 'R': // AIX TOC entry 298 case 'a': // Address operand that is an indexed or indirect from a 299 // register (`p' is preferable for asm statements) 300 case 'S': // Constant suitable as a 64-bit mask operand 301 case 'T': // Constant suitable as a 32-bit mask operand 302 case 'U': // System V Release 4 small data area reference 303 case 't': // AND masks that can be performed by two rldic{l, r} 304 // instructions 305 case 'W': // Vector constant that does not require memory 306 case 'j': // Vector constant that is all zeros. 307 break; 308 // End FIXME. 309 } 310 return true; 311 } 312 convertConstraint(const char * & Constraint)313 std::string convertConstraint(const char *&Constraint) const override { 314 std::string R; 315 switch (*Constraint) { 316 case 'e': 317 case 'w': 318 // Two-character constraint; add "^" hint for later parsing. 319 R = std::string("^") + std::string(Constraint, 2); 320 Constraint++; 321 break; 322 default: 323 return TargetInfo::convertConstraint(Constraint); 324 } 325 return R; 326 } 327 getClobbers()328 const char *getClobbers() const override { return ""; } getEHDataRegisterNumber(unsigned RegNo)329 int getEHDataRegisterNumber(unsigned RegNo) const override { 330 if (RegNo == 0) 331 return 3; 332 if (RegNo == 1) 333 return 4; 334 return -1; 335 } 336 hasSjLjLowering()337 bool hasSjLjLowering() const override { return true; } 338 getLongDoubleMangling()339 const char *getLongDoubleMangling() const override { 340 if (LongDoubleWidth == 64) 341 return "e"; 342 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 343 ? "g" 344 : "u9__ieee128"; 345 } getFloat128Mangling()346 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 347 hasExtIntType()348 bool hasExtIntType() const override { return true; } 349 isSPRegName(StringRef RegName)350 bool isSPRegName(StringRef RegName) const override { 351 return RegName.equals("r1") || RegName.equals("x1"); 352 } 353 }; 354 355 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 356 public: PPC32TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)357 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 358 : PPCTargetInfo(Triple, Opts) { 359 if (Triple.isOSAIX()) 360 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 361 else if (Triple.getArch() == llvm::Triple::ppcle) 362 resetDataLayout("e-m:e-p:32:32-i64:64-n32"); 363 else 364 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 365 366 switch (getTriple().getOS()) { 367 case llvm::Triple::Linux: 368 case llvm::Triple::FreeBSD: 369 case llvm::Triple::NetBSD: 370 SizeType = UnsignedInt; 371 PtrDiffType = SignedInt; 372 IntPtrType = SignedInt; 373 break; 374 case llvm::Triple::AIX: 375 SizeType = UnsignedLong; 376 PtrDiffType = SignedLong; 377 IntPtrType = SignedLong; 378 LongDoubleWidth = 64; 379 LongDoubleAlign = DoubleAlign = 32; 380 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 381 break; 382 default: 383 break; 384 } 385 386 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 387 Triple.isMusl()) { 388 LongDoubleWidth = LongDoubleAlign = 64; 389 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 390 } 391 392 // PPC32 supports atomics up to 4 bytes. 393 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 394 } 395 getBuiltinVaListKind()396 BuiltinVaListKind getBuiltinVaListKind() const override { 397 // This is the ELF definition, and is overridden by the Darwin sub-target 398 return TargetInfo::PowerABIBuiltinVaList; 399 } 400 }; 401 402 // Note: ABI differences may eventually require us to have a separate 403 // TargetInfo for little endian. 404 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 405 public: PPC64TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)406 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 407 : PPCTargetInfo(Triple, Opts) { 408 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 409 IntMaxType = SignedLong; 410 Int64Type = SignedLong; 411 std::string DataLayout = ""; 412 413 if (Triple.isOSAIX()) { 414 // TODO: Set appropriate ABI for AIX platform. 415 DataLayout = "E-m:a-i64:64-n32:64"; 416 LongDoubleWidth = 64; 417 LongDoubleAlign = DoubleAlign = 32; 418 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 419 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 420 DataLayout = "e-m:e-i64:64-n32:64"; 421 ABI = "elfv2"; 422 } else { 423 DataLayout = "E-m:e-i64:64-n32:64"; 424 ABI = "elfv1"; 425 } 426 427 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 428 LongDoubleWidth = LongDoubleAlign = 64; 429 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 430 } 431 432 if (Triple.isOSAIX() || Triple.isOSLinux()) 433 DataLayout += "-S128-v256:256:256-v512:512:512"; 434 resetDataLayout(DataLayout); 435 436 // PPC64 supports atomics up to 8 bytes. 437 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 438 } 439 getBuiltinVaListKind()440 BuiltinVaListKind getBuiltinVaListKind() const override { 441 return TargetInfo::CharPtrBuiltinVaList; 442 } 443 444 // PPC64 Linux-specific ABI options. setABI(const std::string & Name)445 bool setABI(const std::string &Name) override { 446 if (Name == "elfv1" || Name == "elfv2") { 447 ABI = Name; 448 return true; 449 } 450 return false; 451 } 452 checkCallingConvention(CallingConv CC)453 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 454 switch (CC) { 455 case CC_Swift: 456 return CCCR_OK; 457 default: 458 return CCCR_Warning; 459 } 460 } 461 }; 462 463 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 464 : public DarwinTargetInfo<PPC32TargetInfo> { 465 public: DarwinPPC32TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)466 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 467 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 468 HasAlignMac68kSupport = true; 469 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 470 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 471 LongLongAlign = 32; 472 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_"); 473 } 474 getBuiltinVaListKind()475 BuiltinVaListKind getBuiltinVaListKind() const override { 476 return TargetInfo::CharPtrBuiltinVaList; 477 } 478 }; 479 480 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 481 : public DarwinTargetInfo<PPC64TargetInfo> { 482 public: DarwinPPC64TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)483 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 484 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 485 HasAlignMac68kSupport = true; 486 resetDataLayout("E-m:o-i64:64-n32:64", "_"); 487 } 488 }; 489 490 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 491 public AIXTargetInfo<PPC32TargetInfo> { 492 public: 493 using AIXTargetInfo::AIXTargetInfo; getBuiltinVaListKind()494 BuiltinVaListKind getBuiltinVaListKind() const override { 495 return TargetInfo::CharPtrBuiltinVaList; 496 } 497 }; 498 499 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 500 public AIXTargetInfo<PPC64TargetInfo> { 501 public: 502 using AIXTargetInfo::AIXTargetInfo; 503 }; 504 505 } // namespace targets 506 } // namespace clang 507 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 508