1//------------------------------------------------------------------------------ 2// 3// Copyright (c) 2011, ARM Limited. All rights reserved. 4// 5// This program and the accompanying materials 6// are licensed and made available under the terms and conditions of the BSD License 7// which accompanies this distribution. The full text of the license may be found at 8// http://opensource.org/licenses/bsd-license.php 9// 10// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12// 13//------------------------------------------------------------------------------ 14 15 EXPORT ArmReadCntFrq 16 EXPORT ArmWriteCntFrq 17 EXPORT ArmReadCntPct 18 EXPORT ArmReadCntkCtl 19 EXPORT ArmWriteCntkCtl 20 EXPORT ArmReadCntpTval 21 EXPORT ArmWriteCntpTval 22 EXPORT ArmReadCntpCtl 23 EXPORT ArmWriteCntpCtl 24 EXPORT ArmReadCntvTval 25 EXPORT ArmWriteCntvTval 26 EXPORT ArmReadCntvCtl 27 EXPORT ArmWriteCntvCtl 28 EXPORT ArmReadCntvCt 29 EXPORT ArmReadCntpCval 30 EXPORT ArmWriteCntpCval 31 EXPORT ArmReadCntvCval 32 EXPORT ArmWriteCntvCval 33 EXPORT ArmReadCntvOff 34 EXPORT ArmWriteCntvOff 35 36 AREA ArmV7ArchTimerSupport, CODE, READONLY 37 PRESERVE8 38 39ArmReadCntFrq 40 mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ 41 bx lr 42 43ArmWriteCntFrq 44 mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ 45 bx lr 46 47ArmReadCntPct 48 mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register) 49 bx lr 50 51ArmReadCntkCtl 52 mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register) 53 bx lr 54 55ArmWriteCntkCtl 56 mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register) 57 bx lr 58 59ArmReadCntpTval 60 mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register) 61 bx lr 62 63ArmWriteCntpTval 64 mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register) 65 bx lr 66 67ArmReadCntpCtl 68 mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register) 69 bx lr 70 71ArmWriteCntpCtl 72 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register) 73 bx lr 74 75ArmReadCntvTval 76 mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register) 77 bx lr 78 79ArmWriteCntvTval 80 mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register) 81 bx lr 82 83ArmReadCntvCtl 84 mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register) 85 bx lr 86 87ArmWriteCntvCtl 88 mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register) 89 bx lr 90 91ArmReadCntvCt 92 mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register) 93 bx lr 94 95ArmReadCntpCval 96 mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register) 97 bx lr 98 99ArmWriteCntpCval 100 mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register) 101 bx lr 102 103ArmReadCntvCval 104 mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register) 105 bx lr 106 107ArmWriteCntvCval 108 mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register) 109 bx lr 110 111ArmReadCntvOff 112 mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register) 113 bx lr 114 115ArmWriteCntvOff 116 mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register) 117 bx lr 118 119 END 120