xref: /freebsd/sys/dev/bhnd/bcma/bcma_dmp.h (revision 2ff63af9)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5  * Copyright (c) 2010 Broadcom Corporation
6  *
7  * Portions of this file were derived from the aidmp.h header
8  * distributed with Broadcom's initial brcm80211 Linux driver release, as
9  * contributed to the Linux staging repository.
10  *
11  * Permission to use, copy, modify, and/or distribute this software for any
12  * purpose with or without fee is hereby granted, provided that the above
13  * copyright notice and this permission notice appear in all copies.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
18  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
20  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
21  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22  *
23  */
24 
25 #ifndef	_BCMA_BCMA_DMP_H_
26 #define	_BCMA_BCMA_DMP_H_
27 
28 /*
29  * PL-368 Device Management Plugin (DMP) Registers & Constants
30  *
31  * The "DMP" core used in Broadcom HND devices has been described
32  * by Broadcom engineers (and in published header files) as being
33  * ARM's PL-368 "Device Management Plugin" system IP, included with
34  * the CoreLink AMBA Designer tooling.
35  *
36  * Documentation for the PL-368 is not publicly available, however,
37  * and the only public reference by ARM to its existence appears to be
38  * in the proprietary "NIC-301 Interconnect Device Management (PL368)"
39  * errata publication, available to licensees as part of ARM's
40  * CoreLink Controllers and Peripherals Engineering Errata.
41  *
42  * As such, the exact interpretation of these register definitions is
43  * unconfirmed, and may be incorrect.
44  */
45 
46 #define	BCMA_DMP_GET_FLAG(_value, _flag)	\
47 	(((_value) & _flag) != 0)
48 #define	BCMA_DMP_GET_BITS(_value, _field)	\
49         ((_value & _field ## _MASK) >> _field ## _SHIFT)
50 #define	BHND_DMP_SET_BITS(_value, _field)	\
51 	(((_value) << _field ## _SHIFT) & _field ## _MASK)
52 
53 /* Out-of-band Router registers */
54 #define	BCMA_OOB_BUSCONFIG	0x020
55 #define	BCMA_OOB_STATUSA	0x100
56 #define	BCMA_OOB_STATUSB	0x104
57 #define	BCMA_OOB_STATUSC	0x108
58 #define	BCMA_OOB_STATUSD	0x10c
59 #define	BCMA_OOB_ENABLEA0	0x200
60 #define	BCMA_OOB_ENABLEA1	0x204
61 #define	BCMA_OOB_ENABLEA2	0x208
62 #define	BCMA_OOB_ENABLEA3	0x20c
63 #define	BCMA_OOB_ENABLEB0	0x280
64 #define	BCMA_OOB_ENABLEB1	0x284
65 #define	BCMA_OOB_ENABLEB2	0x288
66 #define	BCMA_OOB_ENABLEB3	0x28c
67 #define	BCMA_OOB_ENABLEC0	0x300
68 #define	BCMA_OOB_ENABLEC1	0x304
69 #define	BCMA_OOB_ENABLEC2	0x308
70 #define	BCMA_OOB_ENABLEC3	0x30c
71 #define	BCMA_OOB_ENABLED0	0x380
72 #define	BCMA_OOB_ENABLED1	0x384
73 #define	BCMA_OOB_ENABLED2	0x388
74 #define	BCMA_OOB_ENABLED3	0x38c
75 #define	BCMA_OOB_ITCR		0xf00
76 #define	BCMA_OOB_ITIPOOBA	0xf10
77 #define	BCMA_OOB_ITIPOOBB	0xf14
78 #define	BCMA_OOB_ITIPOOBC	0xf18
79 #define	BCMA_OOB_ITIPOOBD	0xf1c
80 #define	BCMA_OOB_ITOPOOBA	0xf30
81 #define	BCMA_OOB_ITOPOOBB	0xf34
82 #define	BCMA_OOB_ITOPOOBC	0xf38
83 #define	BCMA_OOB_ITOPOOBD	0xf3c
84 
85 /* Common definitions */
86 #define	BCMA_OOB_NUM_BANKS	4	/**< number of OOB banks (A, B, C, D) */
87 #define	BCMA_OOB_NUM_SEL	8	/**< number of OOB selectors per bank */
88 #define	BCMA_OOB_NUM_BUSLINES	32	/**< number of bus lines managed by OOB core */
89 
90 #define	BCMA_OOB_BANKA		0	/**< bank A index */
91 #define	BCMA_OOB_BANKB		1	/**< bank B index */
92 #define	BCMA_OOB_BANKC		2	/**< bank C index */
93 #define	BCMA_OOB_BANKD		3	/**< bank D index */
94 
95 /** OOB bank used for interrupt lines */
96 #define	BCMA_OOB_BANK_INTR	BCMA_OOB_BANKA
97 
98 /* DMP agent registers */
99 #define	BCMA_DMP_OOBSELINA30	0x000	/**< A0-A3 input selectors */
100 #define	BCMA_DMP_OOBSELINA74	0x004	/**< A4-A7 input selectors */
101 #define	BCMA_DMP_OOBSELINB30	0x020	/**< B0-B3 input selectors */
102 #define	BCMA_DMP_OOBSELINB74	0x024	/**< B4-B7 input selectors */
103 #define	BCMA_DMP_OOBSELINC30	0x040	/**< C0-C3 input selectors */
104 #define	BCMA_DMP_OOBSELINC74	0x044	/**< C4-C7 input selectors */
105 #define	BCMA_DMP_OOBSELIND30	0x060	/**< D0-D3 input selectors */
106 #define	BCMA_DMP_OOBSELIND74	0x064	/**< D4-D7 input selectors */
107 #define	BCMA_DMP_OOBSELOUTA30	0x100	/**< A0-A3 output selectors */
108 #define	BCMA_DMP_OOBSELOUTA74	0x104	/**< A4-A7 output selectors */
109 #define	BCMA_DMP_OOBSELOUTB30	0x120	/**< B0-B3 output selectors */
110 #define	BCMA_DMP_OOBSELOUTB74	0x124	/**< B4-B7 output selectors */
111 #define	BCMA_DMP_OOBSELOUTC30	0x140	/**< C0-C3 output selectors */
112 #define	BCMA_DMP_OOBSELOUTC74	0x144	/**< C4-C7 output selectors */
113 #define	BCMA_DMP_OOBSELOUTD30	0x160	/**< D0-D3 output selectors */
114 #define	BCMA_DMP_OOBSELOUTD74	0x164	/**< D4-D7 output selectors */
115 #define	BCMA_DMP_OOBSYNCA	0x200
116 #define	BCMA_DMP_OOBSELOUTAEN	0x204
117 #define	BCMA_DMP_OOBSYNCB	0x220
118 #define	BCMA_DMP_OOBSELOUTBEN	0x224
119 #define	BCMA_DMP_OOBSYNCC	0x240
120 #define	BCMA_DMP_OOBSELOUTCEN	0x244
121 #define	BCMA_DMP_OOBSYNCD	0x260
122 #define	BCMA_DMP_OOBSELOUTDEN	0x264
123 #define	BCMA_DMP_OOBAEXTWIDTH	0x300
124 #define	BCMA_DMP_OOBAINWIDTH	0x304
125 #define	BCMA_DMP_OOBAOUTWIDTH	0x308
126 #define	BCMA_DMP_OOBBEXTWIDTH	0x320
127 #define	BCMA_DMP_OOBBINWIDTH	0x324
128 #define	BCMA_DMP_OOBBOUTWIDTH	0x328
129 #define	BCMA_DMP_OOBCEXTWIDTH	0x340
130 #define	BCMA_DMP_OOBCINWIDTH	0x344
131 #define	BCMA_DMP_OOBCOUTWIDTH	0x348
132 #define	BCMA_DMP_OOBDEXTWIDTH	0x360
133 #define	BCMA_DMP_OOBDINWIDTH	0x364
134 #define	BCMA_DMP_OOBDOUTWIDTH	0x368
135 
136 #define	BCMA_DMP_OOBSEL(_base, _bank, _sel)	\
137     (_base + (_bank * 8) + (_sel >= 4 ? 4 : 0))
138 
139 #define	BCMA_DMP_OOBSELIN(_bank, _sel)		\
140 	BCMA_DMP_OOBSEL(BCMA_DMP_OOBSELINA30, _bank, _sel)
141 
142 #define	BCMA_DMP_OOBSELOUT(_bank, _sel)		\
143 	BCMA_DMP_OOBSEL(BCMA_DMP_OOBSELOUTA30, _bank, _sel)
144 
145 #define	BCMA_DMP_OOBSYNC(_bank)		(BCMA_DMP_OOBSYNCA + (_bank * 8))
146 #define	BCMA_DMP_OOBSELOUT_EN(_bank)	(BCMA_DMP_OOBSELOUTAEN + (_bank * 8))
147 #define	BCMA_DMP_OOB_EXTWIDTH(_bank)	(BCMA_DMP_OOBAEXTWIDTH + (_bank * 12))
148 #define	BCMA_DMP_OOB_INWIDTH(_bank)	(BCMA_DMP_OOBAINWIDTH + (_bank * 12))
149 #define	BCMA_DMP_OOB_OUTWIDTH(_bank)	(BCMA_DMP_OOBAOUTWIDTH + (_bank * 12))
150 
151 // This was inherited from Broadcom's aidmp.h header
152 // Is it required for any of our use-cases?
153 #if 0 /* defined(IL_BIGENDIAN) && defined(BCMHND74K) */
154 /* Selective swapped defines for those registers we need in
155  * big-endian code.
156  */
157 #define	BCMA_DMP_IOCTRLSET	0x404
158 #define	BCMA_DMP_IOCTRLCLEAR	0x400
159 #define	BCMA_DMP_IOCTRL		0x40c
160 #define	BCMA_DMP_IOSTATUS	0x504
161 #define	BCMA_DMP_RESETCTRL	0x804
162 #define	BCMA_DMP_RESETSTATUS	0x800
163 
164 #else				/* !IL_BIGENDIAN || !BCMHND74K */
165 
166 #define	BCMA_DMP_IOCTRLSET	0x400
167 #define	BCMA_DMP_IOCTRLCLEAR	0x404
168 #define	BCMA_DMP_IOCTRL		0x408
169 #define	BCMA_DMP_IOSTATUS	0x500
170 #define	BCMA_DMP_RESETCTRL	0x800
171 #define	BCMA_DMP_RESETSTATUS	0x804
172 
173 #endif				/* IL_BIGENDIAN && BCMHND74K */
174 
175 #define	BCMA_DMP_IOCTRLWIDTH	0x700
176 #define	BCMA_DMP_IOSTATUSWIDTH	0x704
177 
178 #define	BCMA_DMP_RESETREADID	0x808
179 #define	BCMA_DMP_RESETWRITEID	0x80c
180 #define	BCMA_DMP_ERRLOGCTRL	0xa00
181 #define	BCMA_DMP_ERRLOGDONE	0xa04
182 #define	BCMA_DMP_ERRLOGSTATUS	0xa08
183 #define	BCMA_DMP_ERRLOGADDRLO	0xa0c
184 #define	BCMA_DMP_ERRLOGADDRHI	0xa10
185 #define	BCMA_DMP_ERRLOGID	0xa14
186 #define	BCMA_DMP_ERRLOGUSER	0xa18
187 #define	BCMA_DMP_ERRLOGFLAGS	0xa1c
188 #define	BCMA_DMP_INTSTATUS	0xa00
189 #define	BCMA_DMP_CONFIG		0xe00
190 #define	BCMA_DMP_ITCR		0xf00
191 #define	BCMA_DMP_ITIPOOBA	0xf10
192 #define	BCMA_DMP_ITIPOOBB	0xf14
193 #define	BCMA_DMP_ITIPOOBC	0xf18
194 #define	BCMA_DMP_ITIPOOBD	0xf1c
195 #define	BCMA_DMP_ITIPOOBAOUT	0xf30
196 #define	BCMA_DMP_ITIPOOBBOUT	0xf34
197 #define	BCMA_DMP_ITIPOOBCOUT	0xf38
198 #define	BCMA_DMP_ITIPOOBDOUT	0xf3c
199 #define	BCMA_DMP_ITOPOOBA	0xf50
200 #define	BCMA_DMP_ITOPOOBB	0xf54
201 #define	BCMA_DMP_ITOPOOBC	0xf58
202 #define	BCMA_DMP_ITOPOOBD	0xf5c
203 #define	BCMA_DMP_ITOPOOBAIN	0xf70
204 #define	BCMA_DMP_ITOPOOBBIN	0xf74
205 #define	BCMA_DMP_ITOPOOBCIN	0xf78
206 #define	BCMA_DMP_ITOPOOBDIN	0xf7c
207 #define	BCMA_DMP_ITOPRESET	0xf90
208 #define	BCMA_DMP_PERIPHERIALID4	0xfd0
209 #define	BCMA_DMP_PERIPHERIALID5	0xfd4
210 #define	BCMA_DMP_PERIPHERIALID6	0xfd8
211 #define	BCMA_DMP_PERIPHERIALID7	0xfdc
212 #define	BCMA_DMP_PERIPHERIALID0	0xfe0
213 #define	BCMA_DMP_PERIPHERIALID1	0xfe4
214 #define	BCMA_DMP_PERIPHERIALID2	0xfe8
215 #define	BCMA_DMP_PERIPHERIALID3	0xfec
216 #define	BCMA_DMP_COMPONENTID0	0xff0
217 #define	BCMA_DMP_COMPONENTID1	0xff4
218 #define	BCMA_DMP_COMPONENTID2	0xff8
219 #define	BCMA_DMP_COMPONENTID3	0xffc
220 
221 /* OOBSEL(IN|OUT) */
222 #define	BCMA_DMP_OOBSEL_MASK		0xFF		/**< OOB selector mask */
223 #define	BCMA_DMP_OOBSEL_EN		(1<<7)		/**< OOB selector enable bit */
224 #define	BCMA_DMP_OOBSEL_SHIFT(_sel)	((_sel % 4) * 8)
225 #define	BCMA_DMP_OOBSEL_BUSLINE_MASK	0x7F		/**< OOB selector bus line mask */
226 #define	BCMA_DMP_OOBSEL_BUSLINE_SHIFT	0
227 
228 #define	BCMA_DMP_OOBSEL_0_MASK	BCMA_DMP_OOBSEL_MASK
229 #define	BCMA_DMP_OOBSEL_1_MASK	BCMA_DMP_OOBSEL_MASK
230 #define	BCMA_DMP_OOBSEL_2_MASK	BCMA_DMP_OOBSEL_MASK
231 #define	BCMA_DMP_OOBSEL_3_MASK	BCMA_DMP_OOBSEL_MASK
232 
233 #define	BCMA_DMP_OOBSEL_4_MASK	BCMA_DMP_OOBSEL_MASK
234 #define	BCMA_DMP_OOBSEL_5_MASK	BCMA_DMP_OOBSEL_MASK
235 #define	BCMA_DMP_OOBSEL_6_MASK	BCMA_DMP_OOBSEL_MASK
236 #define	BCMA_DMP_OOBSEL_7_MASK	BCMA_DMP_OOBSEL_MASK
237 
238 #define	BCMA_DMP_OOBSEL_0_SHIFT	BCMA_DMP_OOBSEL_SHIFT(0)
239 #define	BCMA_DMP_OOBSEL_1_SHIFT	BCMA_DMP_OOBSEL_SHIFT(1)
240 #define	BCMA_DMP_OOBSEL_2_SHIFT	BCMA_DMP_OOBSEL_SHIFT(2)
241 #define	BCMA_DMP_OOBSEL_3_SHIFT	BCMA_DMP_OOBSEL_SHIFT(3)
242 
243 #define	BCMA_DMP_OOBSEL_4_SHIFT	BCMA_DMP_OOBSEL_0_SHIFT
244 #define	BCMA_DMP_OOBSEL_5_SHIFT	BCMA_DMP_OOBSEL_1_SHIFT
245 #define	BCMA_DMP_OOBSEL_6_SHIFT	BCMA_DMP_OOBSEL_2_SHIFT
246 #define	BCMA_DMP_OOBSEL_7_SHIFT	BCMA_DMP_OOBSEL_3_SHIFT
247 
248 /* ioctrl */
249 #define	BCMA_DMP_IOCTRL_MASK	0x0000FFFF
250 
251 /* iostatus */
252 #define	BCMA_DMP_IOST_MASK	0x0000FFFF
253 
254 /* resetctrl */
255 #define	BCMA_DMP_RC_RESET	0x00000001
256 
257 /* config */
258 #define	BCMA_DMP_CFG_OOB	0x00000020
259 #define	BCMA_DMP_CFG_IOS	0x00000010
260 #define	BCMA_DMP_CFGIOC		0x00000008
261 #define	BCMA_DMP_CFGTO		0x00000004
262 #define	BCMA_DMP_CFGERRL	0x00000002
263 #define	BCMA_DMP_CFGRST		0x00000001
264 
265 #endif /* _BCMA_BCMA_DMP_H_ */
266