xref: /freebsd/sys/dev/bhnd/cores/pmu/bhnd_pmureg.h (revision 95ee2897)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5  * Copyright (c) 2010 Broadcom Corporation
6  * All rights reserved.
7  *
8  * This file is derived from the sbchipc.h header contributed by Broadcom
9  * to to the Linux staging repository, as well as later revisions of sbchipc.h
10  * distributed with the Asus RT-N16 firmware source code release.
11  *
12  * Permission to use, copy, modify, and/or distribute this software for any
13  * purpose with or without fee is hereby granted, provided that the above
14  * copyright notice and this permission notice appear in all copies.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
21  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
22  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23  */
24 
25 #ifndef _BHND_CORES_PMU_BHND_PMUREG_H_
26 #define	_BHND_CORES_PMU_BHND_PMUREG_H_
27 
28 #define BHND_PMU_GET_FLAG(_value, _flag)	\
29 	(((_value) & _flag) != 0)
30 #define	BHND_PMU_GET_BITS(_value, _field)	\
31 	(((_value) & _field ## _MASK) >> _field ## _SHIFT)
32 #define	BHND_PMU_SET_BITS(_value, _field)	\
33 	(((_value) << _field ## _SHIFT) & _field ## _MASK)
34 
35 #define	BHND_PMU_ILP_CLOCK	32000		/**< default ILP freq */
36 #define	BHND_PMU_ALP_CLOCK	20000000	/**< default ALP freq */
37 #define	BHND_PMU_HT_CLOCK	80000000	/**< default HT freq */
38 
39 /**
40  * Common per-core clock control/status register available on PMU-equipped
41  * devices.
42  */
43 #define BHND_CLK_CTL_ST			0x1e0		/**< clock control and status */
44 
45 /*
46  * BHND_CLK_CTL_ST register
47  *
48  * Clock Mode		Name	Description
49  * High Throughput	(HT)	Full bandwidth, low latency. Generally supplied
50  * 				from PLL.
51  * Active Low Power	(ALP)	Register access, low speed DMA.
52  * Idle Low Power	(ILP)	No interconnect activity, or if long latency
53  * 				is permitted.
54  */
55 #define	BHND_CCS_FORCEALP		0x00000001	/**< force ALP request */
56 #define	BHND_CCS_FORCEHT		0x00000002	/**< force HT request */
57 #define	BHND_CCS_FORCEILP		0x00000004	/**< force ILP request */
58 #define	BHND_CCS_FORCE_MASK		0x0000000F
59 
60 #define	BHND_CCS_ALPAREQ		0x00000008	/**< ALP Avail Request */
61 #define	BHND_CCS_HTAREQ			0x00000010	/**< HT Avail Request */
62 #define	BHND_CCS_AREQ_MASK		0x00000018
63 
64 #define	BHND_CCS_FORCEHWREQOFF		0x00000020	/**< Force HW Clock Request Off */
65 
66 #define	BHND_CCS_ERSRC_REQ_MASK		0x00000700	/**< external resource requests */
67 #define	BHND_CCS_ERSRC_REQ_SHIFT	8
68 #define	BHND_CCS_ERSRC_MAX		2		/**< maximum ERSRC value (corresponding to bits 0-2) */
69 
70 #define	BHND_CCS_ALPAVAIL		0x00010000	/**< ALP is available */
71 #define	BHND_CCS_HTAVAIL		0x00020000	/**< HT is available */
72 #define	BHND_CCS_AVAIL_MASK		0x00030000
73 
74 #define	BHND_CCS_BP_ON_APL		0x00040000	/**< RO: Backplane is running on ALP clock */
75 #define	BHND_CCS_BP_ON_HT		0x00080000	/**< RO: Backplane is running on HT clock */
76 #define	BHND_CCS_ERSRC_STS_MASK		0x07000000	/**< external resource status */
77 #define	BHND_CCS_ERSRC_STS_SHIFT	24
78 
79 #define	BHND_CCS0_HTAVAIL		0x00010000	/**< HT avail in chipc and pcmcia on 4328a0 */
80 #define	BHND_CCS0_ALPAVAIL		0x00020000	/**< ALP avail in chipc and pcmcia on 4328a0 */
81 
82 /* PMU registers */
83 #define	BHND_PMU_CTRL			0x600
84 #define	  BHND_PMU_CTRL_ILP_DIV_MASK	0xffff0000
85 #define	  BHND_PMU_CTRL_ILP_DIV_SHIFT	16
86 #define	  BHND_PMU_CTRL_PLL_PLLCTL_UPD	0x00000400	/* rev 2 */
87 #define	  BHND_PMU_CTRL_NOILP_ON_WAIT	0x00000200	/* rev 1 */
88 #define	  BHND_PMU_CTRL_HT_REQ_EN	0x00000100
89 #define	  BHND_PMU_CTRL_ALP_REQ_EN	0x00000080
90 #define	  BHND_PMU_CTRL_XTALFREQ_MASK	0x0000007c
91 #define	  BHND_PMU_CTRL_XTALFREQ_SHIFT	2
92 #define	  BHND_PMU_CTRL_ILP_DIV_EN	0x00000002
93 #define	  BHND_PMU_CTRL_LPO_SEL		0x00000001
94 #define	BHND_PMU_CAP			0x604
95 #define	  BHND_PMU_CAP_REV_MASK		0x000000ff
96 #define	  BHND_PMU_CAP_REV_SHIFT	0
97 #define	  BHND_PMU_CAP_RC_MASK		0x00001f00
98 #define	  BHND_PMU_CAP_RC_SHIFT		8
99 #define	  BHND_PMU_CAP_RC_MAX		\
100 	(BHND_PMU_CAP_RC_MASK >> BHND_PMU_CAP_RC_SHIFT)
101 #define	  BHND_PMU_CAP_TC_MASK		0x0001e000
102 #define	  BHND_PMU_CAP_TC_SHIFT		13
103 #define	  BHND_PMU_CAP_PC_MASK		0x001e0000
104 #define	  BHND_PMU_CAP_PC_SHIFT		17
105 #define	  BHND_PMU_CAP_VC_MASK		0x01e00000
106 #define	  BHND_PMU_CAP_VC_SHIFT		21
107 #define	  BHND_PMU_CAP_CC_MASK		0x1e000000
108 #define	  BHND_PMU_CAP_CC_SHIFT		25
109 #define	  BHND_PMU_CAP5_PC_MASK		0x003e0000	/* PMU corerev >= 5 */
110 #define	  BHND_PMU_CAP5_PC_SHIFT	17
111 #define	  BHND_PMU_CAP5_VC_MASK		0x07c00000
112 #define	  BHND_PMU_CAP5_VC_SHIFT	22
113 #define	  BHND_PMU_CAP5_CC_MASK		0xf8000000
114 #define	  BHND_PMU_CAP5_CC_SHIFT	27
115 #define	BHND_PMU_ST			0x608
116 #define	  BHND_PMU_ST_EXTLPOAVAIL	0x0100
117 #define	  BHND_PMU_ST_WDRESET		0x0080
118 #define	  BHND_PMU_ST_INTPEND		0x0040
119 #define	  BHND_PMU_ST_SBCLKST		0x0030
120 #define	  BHND_PMU_ST_SBCLKST_ILP	0x0010
121 #define	  BHND_PMU_ST_SBCLKST_ALP	0x0020
122 #define	  BHND_PMU_ST_SBCLKST_HT	0x0030
123 #define	  BHND_PMU_ST_ALPAVAIL		0x0008
124 #define	  BHND_PMU_ST_HTAVAIL		0x0004
125 #define	  BHND_PMU_ST_RESINIT		0x0003
126 #define	BHND_PMU_RES_STATE		0x60c
127 #define	BHND_PMU_RES_PENDING		0x610
128 #define	BHND_PMU_TIMER			0x614
129 #define	BHND_PMU_MIN_RES_MASK		0x618
130 #define	BHND_PMU_MAX_RES_MASK		0x61c
131 #define	BHND_PMU_RES_TABLE_SEL		0x620
132 #define	BHND_PMU_RES_DEP_MASK		0x624
133 #define	BHND_PMU_RES_UPDN_TIMER		0x628
134 #define	  BHND_PMU_RES_UPDN_UPTME_MASK	0xFF00
135 #define	  BHND_PMU_RES_UPDN_UPTME_SHIFT	8
136 #define	BHND_PMU_RES_TIMER		0x62C
137 #define	BHND_PMU_CLKSTRETCH		0x630
138 #define	  BHND_PMU_CSTRETCH_HT		0xffff0000
139 #define	  BHND_PMU_CSTRETCH_ALP		0x0000ffff
140 #define	BHND_PMU_WATCHDOG		0x634
141 #define	BHND_PMU_GPIOSEL		0x638		/* pmu rev >= 1 ? */
142 #define	BHND_PMU_GPIOEN			0x63C		/* pmu rev >= 1 ? */
143 #define	BHND_PMU_RES_REQ_TIMER_SEL	0x640
144 #define	BHND_PMU_RES_REQ_TIMER		0x644
145 #define	  BHND_PMU_RRQT_TIME_MASK	0x03ff
146 #define	  BHND_PMU_RRQT_INTEN		0x0400
147 #define	  BHND_PMU_RRQT_REQ_ACTIVE	0x0800
148 #define	  BHND_PMU_RRQT_ALP_REQ		0x1000
149 #define	  BHND_PMU_RRQT_HT_REQ		0x2000
150 #define	BHND_PMU_RES_REQ_MASK		0x648
151 #define	BHND_PMU_CHIP_CONTROL_ADDR	0x650
152 #define	BHND_PMU_CHIP_CONTROL_DATA	0x654
153 #define	BHND_PMU_REG_CONTROL_ADDR	0x658
154 #define	BHND_PMU_REG_CONTROL_DATA	0x65C
155 #define	BHND_PMU_PLL_CONTROL_ADDR 	0x660
156 #define	BHND_PMU_PLL_CONTROL_DATA 	0x664
157 #define	BHND_PMU_STRAPOPT		0x668		/* chipc rev >= 28 */
158 #define	BHND_PMU_XTALFREQ		0x66C		/* pmu rev >= 10 */
159 
160 /* PMU resource bit position */
161 #define	BHND_PMURES_BIT(bit)		(1 << (bit))
162 
163 /* PMU resource number limit */
164 #define	BHND_PMU_RESNUM_MAX		30
165 
166 /* PMU chip control0 register */
167 #define	BHND_PMU_CHIPCTL0		0
168 
169 /* PMU chip control1 register */
170 #define	BHND_PMU_CHIPCTL1		1
171 #define	BHND_PMU_CC1_RXC_DLL_BYPASS	0x00010000
172 
173 #define	BHND_PMU_CC1_IF_TYPE_MASK	0x00000030
174 #define	BHND_PMU_CC1_IF_TYPE_RMII	0x00000000
175 #define	BHND_PMU_CC1_IF_TYPE_MII	0x00000010
176 #define	BHND_PMU_CC1_IF_TYPE_RGMII	0x00000020
177 
178 #define	BHND_PMU_CC1_SW_TYPE_MASK	0x000000c0
179 #define	BHND_PMU_CC1_SW_TYPE_EPHY	0x00000000
180 #define	BHND_PMU_CC1_SW_TYPE_EPHYMII	0x00000040
181 #define	BHND_PMU_CC1_SW_TYPE_EPHYRMII	0x00000080
182 #define	BHND_PMU_CC1_SW_TYPE_RGMII	0x000000c0
183 
184 /* PMU corerev and chip specific PLL controls.
185  * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
186  * to differentiate different PLLs controlled by the same PMU rev.
187  */
188 
189 /* pllcontrol registers */
190 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
191 #define	BHND_PMU0_PLL0_PLLCTL0		0
192 #define	BHND_PMU0_PLL0_PC0_PDIV_MASK	1
193 #define	BHND_PMU0_PLL0_PC0_PDIV_FREQ	25000
194 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_MASK	0x00000038
195 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_SHIFT	3
196 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_BASE	8
197 
198 /* PC0_DIV_ARM for PLLOUT_ARM */
199 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_110MHZ	0
200 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ	1
201 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_88MHZ	2
202 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_80MHZ	3	/* Default */
203 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ	4
204 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ	5
205 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ	6
206 #define	BHND_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ	7
207 
208 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
209 #define	BHND_PMU0_PLL0_PLLCTL1		1
210 #define	BHND_PMU0_PLL0_PC1_WILD_INT_MASK	0xf0000000
211 #define	BHND_PMU0_PLL0_PC1_WILD_INT_SHIFT	28
212 #define	BHND_PMU0_PLL0_PC1_WILD_FRAC_MASK	0x0fffff00
213 #define	BHND_PMU0_PLL0_PC1_WILD_FRAC_SHIFT	8
214 #define	BHND_PMU0_PLL0_PC1_STOP_MOD		0x00000040
215 
216 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
217 #define	BHND_PMU0_PLL0_PLLCTL2		2
218 #define	BHND_PMU0_PLL0_PC2_WILD_INT_MASK	0xf0
219 #define	BHND_PMU0_PLL0_PC2_WILD_INT_SHIFT	4
220 
221 /* pllcontrol registers */
222 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
223 #define	BHND_PMU1_PLL0_PLLCTL0		0
224 #define	BHND_PMU1_PLL0_PC0_P1DIV_MASK		0x00f00000
225 #define	BHND_PMU1_PLL0_PC0_P1DIV_SHIFT		20
226 #define	BHND_PMU1_PLL0_PC0_P2DIV_MASK		0x0f000000
227 #define	BHND_PMU1_PLL0_PC0_P2DIV_SHIFT		24
228 #define	BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_MASK	0x10000000
229 #define	BHND_PMU1_PLL0_PC0_BYPASS_SDMOD_SHIFT	28
230 
231 /* m<x>div */
232 #define	BHND_PMU1_PLL0_PLLCTL1		1
233 #define	BHND_PMU1_PLL0_PC1_M1DIV_MASK	0x000000ff
234 #define	BHND_PMU1_PLL0_PC1_M1DIV_SHIFT	0
235 #define	BHND_PMU1_PLL0_PC1_M2DIV_MASK	0x0000ff00
236 #define	BHND_PMU1_PLL0_PC1_M2DIV_SHIFT	8
237 #define	BHND_PMU1_PLL0_PC1_M3DIV_MASK	0x00ff0000
238 #define	BHND_PMU1_PLL0_PC1_M3DIV_SHIFT	16
239 #define	BHND_PMU1_PLL0_PC1_M4DIV_MASK	0xff000000
240 #define	BHND_PMU1_PLL0_PC1_M4DIV_SHIFT	24
241 
242 #define	BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
243 #define	BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
244 #define	BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_VAL  (0xE << BHND_PMU_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
245 
246 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
247 #define	BHND_PMU1_PLL0_PLLCTL2		2
248 #define	BHND_PMU1_PLL0_PC2_M5DIV_MASK	0x000000ff
249 #define	BHND_PMU1_PLL0_PC2_M5DIV_SHIFT	0
250 #define	BHND_PMU1_PLL0_PC2_M6DIV_MASK	0x0000ff00
251 #define	BHND_PMU1_PLL0_PC2_M6DIV_SHIFT	8
252 #define	BHND_PMU1_PLL0_PC2_NDIV_MODE_MASK	0x000e0000
253 #define	BHND_PMU1_PLL0_PC2_NDIV_MODE_SHIFT	17
254 #define	BHND_PMU1_PLL0_PC2_NDIV_MODE_INT	0
255 #define	BHND_PMU1_PLL0_PC2_NDIV_MODE_MASH	1
256 #define	BHND_PMU1_PLL0_PC2_NDIV_MODE_MFB	2	/* recommended for 4319 */
257 #define	BHND_PMU1_PLL0_PC2_NDIV_INT_MASK	0x1ff00000
258 #define	BHND_PMU1_PLL0_PC2_NDIV_INT_SHIFT	20
259 
260 /* ndiv_frac */
261 #define	BHND_PMU1_PLL0_PLLCTL3		3
262 #define	BHND_PMU1_PLL0_PC3_NDIV_FRAC_MASK	0x00ffffff
263 #define	BHND_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT	0
264 
265 /* pll_ctrl */
266 #define	BHND_PMU1_PLL0_PLLCTL4			4
267 #define	BHND_PMU1_PLL0_PC4_KVCO_XS_MASK		0x38000000
268 #define	BHND_PMU1_PLL0_PC4_KVCO_XS_SHIFT	27
269 
270 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
271 #define	BHND_PMU1_PLL0_PLLCTL5			5
272 #define	BHND_PMU1_PLL0_PC5_CLK_DRV_MASK		0xffffff00
273 #define	BHND_PMU1_PLL0_PC5_CLK_DRV_SHIFT	8
274 #define	BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_MASK	0x0000003f
275 #define	BHND_PMU1_PLL0_PC5_PLL_CTRL_37_32_SHIFT	0
276 #define	BHND_PMU1_PLL0_PC5_VCO_RNG_MASK		0x000000C0
277 #define	BHND_PMU1_PLL0_PC5_VCO_RNG_SHIFT	6
278 
279 /* PMU rev 2 control words */
280 #define	BHND_PMU2_PHY_PLL_PLLCTL		4
281 #define	BHND_PMU2_SI_PLL_PLLCTL		10
282 
283 /* PMU rev 2 */
284 /* pllcontrol registers */
285 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
286 #define	BHND_PMU2_PLL_PLLCTL0		0
287 #define	BHND_PMU2_PLL_PC0_P1DIV_MASK 	0x00f00000
288 #define	BHND_PMU2_PLL_PC0_P1DIV_SHIFT	20
289 #define	BHND_PMU2_PLL_PC0_P2DIV_MASK 	0x0f000000
290 #define	BHND_PMU2_PLL_PC0_P2DIV_SHIFT	24
291 
292 /* m<x>div */
293 #define	BHND_PMU2_PLL_PLLCTL1		1
294 #define	BHND_PMU2_PLL_PC1_M1DIV_MASK 	0x000000ff
295 #define	BHND_PMU2_PLL_PC1_M1DIV_SHIFT	0
296 #define	BHND_PMU2_PLL_PC1_M2DIV_MASK 	0x0000ff00
297 #define	BHND_PMU2_PLL_PC1_M2DIV_SHIFT	8
298 #define	BHND_PMU2_PLL_PC1_M3DIV_MASK 	0x00ff0000
299 #define	BHND_PMU2_PLL_PC1_M3DIV_SHIFT	16
300 #define	BHND_PMU2_PLL_PC1_M4DIV_MASK 	0xff000000
301 #define	BHND_PMU2_PLL_PC1_M4DIV_SHIFT	24
302 
303 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
304 #define	BHND_PMU2_PLL_PLLCTL2		2
305 #define	BHND_PMU2_PLL_PC2_M5DIV_MASK 	0x000000ff
306 #define	BHND_PMU2_PLL_PC2_M5DIV_SHIFT	0
307 #define	BHND_PMU2_PLL_PC2_M6DIV_MASK 	0x0000ff00
308 #define	BHND_PMU2_PLL_PC2_M6DIV_SHIFT	8
309 #define	BHND_PMU2_PLL_PC2_NDIV_MODE_MASK	0x000e0000
310 #define	BHND_PMU2_PLL_PC2_NDIV_MODE_SHIFT	17
311 #define	BHND_PMU2_PLL_PC2_NDIV_INT_MASK	0x1ff00000
312 #define	BHND_PMU2_PLL_PC2_NDIV_INT_SHIFT	20
313 
314 /* ndiv_frac */
315 #define	BHND_PMU2_PLL_PLLCTL3		3
316 #define	BHND_PMU2_PLL_PC3_NDIV_FRAC_MASK	0x00ffffff
317 #define	BHND_PMU2_PLL_PC3_NDIV_FRAC_SHIFT	0
318 
319 /* pll_ctrl */
320 #define	BHND_PMU2_PLL_PLLCTL4		4
321 
322 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
323 #define	BHND_PMU2_PLL_PLLCTL5			5
324 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK		0x00000f00
325 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT	8
326 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK		0x0000f000
327 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT	12
328 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK		0x000f0000
329 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT	16
330 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK		0x00f00000
331 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT	20
332 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK		0x0f000000
333 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT	24
334 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK		0xf0000000
335 #define	BHND_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT	28
336 
337 /* PMU rev 5 (& 6) */
338 #define	BHND_PMU5_PLL_P1P2_OFF		0
339 #define	BHND_PMU5_PLL_P1_MASK		0x0f000000
340 #define	BHND_PMU5_PLL_P1_SHIFT		24
341 #define	BHND_PMU5_PLL_P2_MASK		0x00f00000
342 #define	BHND_PMU5_PLL_P2_SHIFT		20
343 #define	BHND_PMU5_PLL_M14_OFF		1
344 #define	BHND_PMU5_PLL_MDIV_MASK		0x000000ff
345 #define	BHND_PMU5_PLL_MDIV_WIDTH		8
346 #define	BHND_PMU5_PLL_NM5_OFF		2
347 #define	BHND_PMU5_PLL_NDIV_MASK		0xfff00000
348 #define	BHND_PMU5_PLL_NDIV_SHIFT		20
349 #define	BHND_PMU5_PLL_NDIV_MODE_MASK	0x000e0000
350 #define	BHND_PMU5_PLL_NDIV_MODE_SHIFT	17
351 #define	BHND_PMU5_PLL_FMAB_OFF		3
352 #define	BHND_PMU5_PLL_MRAT_MASK		0xf0000000
353 #define	BHND_PMU5_PLL_MRAT_SHIFT		28
354 #define	BHND_PMU5_PLL_ABRAT_MASK		0x08000000
355 #define	BHND_PMU5_PLL_ABRAT_SHIFT		27
356 #define	BHND_PMU5_PLL_FDIV_MASK		0x07ffffff
357 #define	BHND_PMU5_PLL_PLLCTL_OFF		4
358 #define	BHND_PMU5_PLL_PCHI_OFF		5
359 #define	BHND_PMU5_PLL_PCHI_MASK		0x0000003f
360 
361 /* pmu XtalFreqRatio */
362 #define	BHND_PMU_XTALFREQ_REG_ILPCTR_MASK	0x00001FFF
363 #define	BHND_PMU_XTALFREQ_REG_ILPCTR_SHIFT	0
364 #define	BHND_PMU_XTALFREQ_REG_MEASURE_MASK	0x80000000
365 #define	BHND_PMU_XTALFREQ_REG_MEASURE_SHIFT	31
366 
367 /* Divider allocation in 4716/47162/5356/5357 */
368 #define	BHND_PMU5_MAINPLL_CPU		1
369 #define	BHND_PMU5_MAINPLL_MEM		2
370 #define	BHND_PMU5_MAINPLL_SI		3
371 
372 /* PMU rev 6 (BCM4706/Northstar) */
373 #define	BHND_PMU4706_MAINPLL_PLL0		0
374 #define	BHND_PMU6_4706_PROCPLL_OFF		4	/* The CPU PLL */
375 #define	BHND_PMU6_4706_PROC_P1DIV_MASK		0x000f0000
376 #define	BHND_PMU6_4706_PROC_P1DIV_SHIFT		16
377 #define	BHND_PMU6_4706_PROC_P2DIV_MASK		0x0000f000
378 #define	BHND_PMU6_4706_PROC_P2DIV_SHIFT		12
379 #define	BHND_PMU6_4706_PROC_NDIV_INT_MASK	0x00000ff8
380 #define	BHND_PMU6_4706_PROC_NDIV_INT_SHIFT	3
381 #define	BHND_PMU6_4706_PROC_NDIV_MODE_MASK	0x00000007
382 #define	BHND_PMU6_4706_PROC_NDIV_MODE_SHIFT	0
383 
384 /* Divider allocation in 4706 */
385 #define	BHND_PMU6_MAINPLL_CPU		1
386 #define	BHND_PMU6_MAINPLL_MEM		2
387 #define	BHND_PMU6_MAINPLL_SI		3
388 
389 /* PMU7 (?) */
390 #define	BHND_PMU7_PLL_PLLCTL7		7
391 #define	BHND_PMU7_PLL_PLLCTL8		8
392 #define	BHND_PMU7_PLL_PLLCTL11		11
393 
394 /* PLL usage in 4716/47162 */
395 #define	BHND_PMU4716_MAINPLL_PLL0	12
396 
397 /* PLL usage in 5356/5357 */
398 #define	BHND_PMU5356_MAINPLL_PLL0	0
399 #define	BHND_PMU5357_MAINPLL_PLL0	0
400 
401 /* 4716/47162 PMU resources */
402 #define	BHND_PMU_RES4716_PROC_PLL_ON		0x00000040
403 #define	BHND_PMU_RES4716_PROC_HT_AVAIL		0x00000080
404 
405 /* 4716/4717/4718 chip-specific CHIPCTRL PMU register bits */
406 #define	BHND_PMU_CCTRL471X_I2S_PINS_ENABLE	0x0080	/* I2S pins off by default, shared with pflash */
407 
408 /* 5354 PMU resources */
409 #define	BHND_PMU_RES5354_EXT_SWITCHER_PWM	0	/* 0x00001 */
410 #define	BHND_PMU_RES5354_BB_SWITCHER_PWM	1	/* 0x00002 */
411 #define	BHND_PMU_RES5354_BB_SWITCHER_BURST	2	/* 0x00004 */
412 #define	BHND_PMU_RES5354_BB_EXT_SWITCHER_BURST	3	/* 0x00008 */
413 #define	BHND_PMU_RES5354_ILP_REQUEST		4	/* 0x00010 */
414 #define	BHND_PMU_RES5354_RADIO_SWITCHER_PWM	5	/* 0x00020 */
415 #define	BHND_PMU_RES5354_RADIO_SWITCHER_BURST	6	/* 0x00040 */
416 #define	BHND_PMU_RES5354_ROM_SWITCH		7	/* 0x00080 */
417 #define	BHND_PMU_RES5354_PA_REF_LDO		8	/* 0x00100 */
418 #define	BHND_PMU_RES5354_RADIO_LDO		9	/* 0x00200 */
419 #define	BHND_PMU_RES5354_AFE_LDO		10	/* 0x00400 */
420 #define	BHND_PMU_RES5354_PLL_LDO		11	/* 0x00800 */
421 #define	BHND_PMU_RES5354_BG_FILTBYP		12	/* 0x01000 */
422 #define	BHND_PMU_RES5354_TX_FILTBYP		13	/* 0x02000 */
423 #define	BHND_PMU_RES5354_RX_FILTBYP		14	/* 0x04000 */
424 #define	BHND_PMU_RES5354_XTAL_PU		15	/* 0x08000 */
425 #define	BHND_PMU_RES5354_XTAL_EN		16	/* 0x10000 */
426 #define	BHND_PMU_RES5354_BB_PLL_FILTBYP		17	/* 0x20000 */
427 #define	BHND_PMU_RES5354_RF_PLL_FILTBYP		18	/* 0x40000 */
428 #define	BHND_PMU_RES5354_BB_PLL_PU		19	/* 0x80000 */
429 
430 /* 5357 chip-specific CHIPCTRL register bits */
431 #define	BHND_PMU_CCTRL5357_EXTPA		(1<<14)	/* extPA in CHIPCTRL1, bit 14 */
432 #define	BHND_PMU_CCTRL5357_ANT_MUX_2o3		(1<<15)	/* 2o3 in CHIPCTRL1, bit 15 */
433 
434 /* 4328 PMU resources */
435 #define	BHND_PMU_RES4328_EXT_SWITCHER_PWM	0	/* 0x00001 */
436 #define	BHND_PMU_RES4328_BB_SWITCHER_PWM	1	/* 0x00002 */
437 #define	BHND_PMU_RES4328_BB_SWITCHER_BURST	2	/* 0x00004 */
438 #define	BHND_PMU_RES4328_BB_EXT_SWITCHER_BURST	3	/* 0x00008 */
439 #define	BHND_PMU_RES4328_ILP_REQUEST		4	/* 0x00010 */
440 #define	BHND_PMU_RES4328_RADIO_SWITCHER_PWM	5	/* 0x00020 */
441 #define	BHND_PMU_RES4328_RADIO_SWITCHER_BURST	6	/* 0x00040 */
442 #define	BHND_PMU_RES4328_ROM_SWITCH		7	/* 0x00080 */
443 #define	BHND_PMU_RES4328_PA_REF_LDO		8	/* 0x00100 */
444 #define	BHND_PMU_RES4328_RADIO_LDO		9	/* 0x00200 */
445 #define	BHND_PMU_RES4328_AFE_LDO		10	/* 0x00400 */
446 #define	BHND_PMU_RES4328_PLL_LDO		11	/* 0x00800 */
447 #define	BHND_PMU_RES4328_BG_FILTBYP		12	/* 0x01000 */
448 #define	BHND_PMU_RES4328_TX_FILTBYP		13	/* 0x02000 */
449 #define	BHND_PMU_RES4328_RX_FILTBYP		14	/* 0x04000 */
450 #define	BHND_PMU_RES4328_XTAL_PU		15	/* 0x08000 */
451 #define	BHND_PMU_RES4328_XTAL_EN		16	/* 0x10000 */
452 #define	BHND_PMU_RES4328_BB_PLL_FILTBYP		17	/* 0x20000 */
453 #define	BHND_PMU_RES4328_RF_PLL_FILTBYP		18	/* 0x40000 */
454 #define	BHND_PMU_RES4328_BB_PLL_PU		19	/* 0x80000 */
455 
456 /* 4325 A0/A1 PMU resources */
457 #define	BHND_PMU_RES4325_BUCK_BOOST_BURST	0	/* 0x00000001 */
458 #define	BHND_PMU_RES4325_CBUCK_BURST		1	/* 0x00000002 */
459 #define	BHND_PMU_RES4325_CBUCK_PWM		2	/* 0x00000004 */
460 #define	BHND_PMU_RES4325_CLDO_CBUCK_BURST	3	/* 0x00000008 */
461 #define	BHND_PMU_RES4325_CLDO_CBUCK_PWM		4	/* 0x00000010 */
462 #define	BHND_PMU_RES4325_BUCK_BOOST_PWM		5	/* 0x00000020 */
463 #define	BHND_PMU_RES4325_ILP_REQUEST		6	/* 0x00000040 */
464 #define	BHND_PMU_RES4325_ABUCK_BURST		7	/* 0x00000080 */
465 #define	BHND_PMU_RES4325_ABUCK_PWM		8	/* 0x00000100 */
466 #define	BHND_PMU_RES4325_LNLDO1_PU		9	/* 0x00000200 */
467 #define	BHND_PMU_RES4325_OTP_PU			10	/* 0x00000400 */
468 #define	BHND_PMU_RES4325_LNLDO3_PU		11	/* 0x00000800 */
469 #define	BHND_PMU_RES4325_LNLDO4_PU		12	/* 0x00001000 */
470 #define	BHND_PMU_RES4325_XTAL_PU		13	/* 0x00002000 */
471 #define	BHND_PMU_RES4325_ALP_AVAIL		14	/* 0x00004000 */
472 #define	BHND_PMU_RES4325_RX_PWRSW_PU		15	/* 0x00008000 */
473 #define	BHND_PMU_RES4325_TX_PWRSW_PU		16	/* 0x00010000 */
474 #define	BHND_PMU_RES4325_RFPLL_PWRSW_PU		17	/* 0x00020000 */
475 #define	BHND_PMU_RES4325_LOGEN_PWRSW_PU		18	/* 0x00040000 */
476 #define	BHND_PMU_RES4325_AFE_PWRSW_PU		19	/* 0x00080000 */
477 #define	BHND_PMU_RES4325_BBPLL_PWRSW_PU		20	/* 0x00100000 */
478 #define	BHND_PMU_RES4325_HT_AVAIL		21	/* 0x00200000 */
479 
480 /* 4325 B0/C0 PMU resources */
481 #define	BHND_PMU_RES4325B0_CBUCK_LPOM		1	/* 0x00000002 */
482 #define	BHND_PMU_RES4325B0_CBUCK_BURST		2	/* 0x00000004 */
483 #define	BHND_PMU_RES4325B0_CBUCK_PWM		3	/* 0x00000008 */
484 #define	BHND_PMU_RES4325B0_CLDO_PU		4	/* 0x00000010 */
485 
486 /* 4325 C1 PMU resources */
487 #define	BHND_PMU_RES4325C1_LNLDO2_PU		12	/* 0x00001000 */
488 
489 /* 4325 PMU resources */
490 #define	BHND_PMU_RES4329_RESERVED0		0	/* 0x00000001 */
491 #define	BHND_PMU_RES4329_CBUCK_LPOM		1	/* 0x00000002 */
492 #define	BHND_PMU_RES4329_CBUCK_BURST		2	/* 0x00000004 */
493 #define	BHND_PMU_RES4329_CBUCK_PWM		3	/* 0x00000008 */
494 #define	BHND_PMU_RES4329_CLDO_PU		4	/* 0x00000010 */
495 #define	BHND_PMU_RES4329_PALDO_PU		5	/* 0x00000020 */
496 #define	BHND_PMU_RES4329_ILP_REQUEST		6	/* 0x00000040 */
497 #define	BHND_PMU_RES4329_RESERVED7		7	/* 0x00000080 */
498 #define	BHND_PMU_RES4329_RESERVED8		8	/* 0x00000100 */
499 #define	BHND_PMU_RES4329_LNLDO1_PU		9	/* 0x00000200 */
500 #define	BHND_PMU_RES4329_OTP_PU			10	/* 0x00000400 */
501 #define	BHND_PMU_RES4329_RESERVED11		11	/* 0x00000800 */
502 #define	BHND_PMU_RES4329_LNLDO2_PU		12	/* 0x00001000 */
503 #define	BHND_PMU_RES4329_XTAL_PU		13	/* 0x00002000 */
504 #define	BHND_PMU_RES4329_ALP_AVAIL		14	/* 0x00004000 */
505 #define	BHND_PMU_RES4329_RX_PWRSW_PU		15	/* 0x00008000 */
506 #define	BHND_PMU_RES4329_TX_PWRSW_PU		16	/* 0x00010000 */
507 #define	BHND_PMU_RES4329_RFPLL_PWRSW_PU		17	/* 0x00020000 */
508 #define	BHND_PMU_RES4329_LOGEN_PWRSW_PU		18	/* 0x00040000 */
509 #define	BHND_PMU_RES4329_AFE_PWRSW_PU		19	/* 0x00080000 */
510 #define	BHND_PMU_RES4329_BBPLL_PWRSW_PU		20	/* 0x00100000 */
511 #define	BHND_PMU_RES4329_HT_AVAIL		21	/* 0x00200000 */
512 
513 /* 4312 PMU resources (all PMU chips with little memory constraint) */
514 #define	BHND_PMU_RES4312_SWITCHER_BURST		0	/* 0x00000001 */
515 #define	BHND_PMU_RES4312_SWITCHER_PWM    	1	/* 0x00000002 */
516 #define	BHND_PMU_RES4312_PA_REF_LDO		2	/* 0x00000004 */
517 #define	BHND_PMU_RES4312_CORE_LDO_BURST		3	/* 0x00000008 */
518 #define	BHND_PMU_RES4312_CORE_LDO_PWM		4	/* 0x00000010 */
519 #define	BHND_PMU_RES4312_RADIO_LDO		5	/* 0x00000020 */
520 #define	BHND_PMU_RES4312_ILP_REQUEST		6	/* 0x00000040 */
521 #define	BHND_PMU_RES4312_BG_FILTBYP		7	/* 0x00000080 */
522 #define	BHND_PMU_RES4312_TX_FILTBYP		8	/* 0x00000100 */
523 #define	BHND_PMU_RES4312_RX_FILTBYP		9	/* 0x00000200 */
524 #define	BHND_PMU_RES4312_XTAL_PU		10	/* 0x00000400 */
525 #define	BHND_PMU_RES4312_ALP_AVAIL		11	/* 0x00000800 */
526 #define	BHND_PMU_RES4312_BB_PLL_FILTBYP		12	/* 0x00001000 */
527 #define	BHND_PMU_RES4312_RF_PLL_FILTBYP		13	/* 0x00002000 */
528 #define	BHND_PMU_RES4312_HT_AVAIL		14	/* 0x00004000 */
529 
530 /* 4322 PMU resources */
531 #define	BHND_PMU_RES4322_RF_LDO			0
532 #define	BHND_PMU_RES4322_ILP_REQUEST		1
533 #define	BHND_PMU_RES4322_XTAL_PU		2
534 #define	BHND_PMU_RES4322_ALP_AVAIL		3
535 #define	BHND_PMU_RES4322_SI_PLL_ON		4
536 #define	BHND_PMU_RES4322_HT_SI_AVAIL		5
537 #define	BHND_PMU_RES4322_PHY_PLL_ON		6
538 #define	BHND_PMU_RES4322_HT_PHY_AVAIL		7
539 #define	BHND_PMU_RES4322_OTP_PU			8
540 
541 /* 43224 chip-specific CHIPCTRL register bits */
542 #define	BHND_PMU_CCTRL43224_GPIO_TOGGLE	0x8000
543 #define	BHND_PMU_CCTRL43224A0_12MA_LED_DRIVE	0x00F000F0	/* 12 mA drive strength */
544 #define	BHND_PMU_CCTRL43224B0_12MA_LED_DRIVE	0xF0		/* 12 mA drive strength for later 43224s */
545 
546 /* 43236 PMU resources */
547 #define	BHND_PMU_RES43236_REGULATOR		0
548 #define	BHND_PMU_RES43236_ILP_REQUEST		1
549 #define	BHND_PMU_RES43236_XTAL_PU		2
550 #define	BHND_PMU_RES43236_ALP_AVAIL		3
551 #define	BHND_PMU_RES43236_SI_PLL_ON		4
552 #define	BHND_PMU_RES43236_HT_SI_AVAIL		5
553 
554 /* 43236 chip-specific CHIPCTRL register bits */
555 #define	BHND_PMU_CCTRL43236_BT_COEXIST		(1<<0)	/* 0 disable */
556 #define	BHND_PMU_CCTRL43236_SECI		(1<<1)	/* 0 SECI is disabled (JATG functional) */
557 #define	BHND_PMU_CCTRL43236_EXT_LNA		(1<<2)	/* 0 disable */
558 #define	BHND_PMU_CCTRL43236_ANT_MUX_2o3		(1<<3)	/* 2o3 mux, chipcontrol bit 3 */
559 #define	BHND_PMU_CCTRL43236_GSIO		(1<<4)	/* 0 disable */
560 
561 /* 4331 PMU resources */
562 #define	BHND_PMU_RES4331_REGULATOR		0
563 #define	BHND_PMU_RES4331_ILP_REQUEST		1
564 #define	BHND_PMU_RES4331_XTAL_PU		2
565 #define	BHND_PMU_RES4331_ALP_AVAIL		3
566 #define	BHND_PMU_RES4331_SI_PLL_ON		4
567 #define	BHND_PMU_RES4331_HT_SI_AVAIL		5
568 
569 /* 4315 PMU resources */
570 #define	BHND_PMU_RES4315_CBUCK_LPOM		1	/* 0x00000002 */
571 #define	BHND_PMU_RES4315_CBUCK_BURST		2	/* 0x00000004 */
572 #define	BHND_PMU_RES4315_CBUCK_PWM		3	/* 0x00000008 */
573 #define	BHND_PMU_RES4315_CLDO_PU		4	/* 0x00000010 */
574 #define	BHND_PMU_RES4315_PALDO_PU		5	/* 0x00000020 */
575 #define	BHND_PMU_RES4315_ILP_REQUEST		6	/* 0x00000040 */
576 #define	BHND_PMU_RES4315_LNLDO1_PU		9	/* 0x00000200 */
577 #define	BHND_PMU_RES4315_OTP_PU			10	/* 0x00000400 */
578 #define	BHND_PMU_RES4315_LNLDO2_PU		12	/* 0x00001000 */
579 #define	BHND_PMU_RES4315_XTAL_PU		13	/* 0x00002000 */
580 #define	BHND_PMU_RES4315_ALP_AVAIL		14	/* 0x00004000 */
581 #define	BHND_PMU_RES4315_RX_PWRSW_PU		15	/* 0x00008000 */
582 #define	BHND_PMU_RES4315_TX_PWRSW_PU		16	/* 0x00010000 */
583 #define	BHND_PMU_RES4315_RFPLL_PWRSW_PU		17	/* 0x00020000 */
584 #define	BHND_PMU_RES4315_LOGEN_PWRSW_PU		18	/* 0x00040000 */
585 #define	BHND_PMU_RES4315_AFE_PWRSW_PU		19	/* 0x00080000 */
586 #define	BHND_PMU_RES4315_BBPLL_PWRSW_PU		20	/* 0x00100000 */
587 #define	BHND_PMU_RES4315_HT_AVAIL		21	/* 0x00200000 */
588 
589 /* 4319 PMU resources */
590 #define	BHND_PMU_RES4319_CBUCK_LPOM		1	/* 0x00000002 */
591 #define	BHND_PMU_RES4319_CBUCK_BURST		2	/* 0x00000004 */
592 #define	BHND_PMU_RES4319_CBUCK_PWM		3	/* 0x00000008 */
593 #define	BHND_PMU_RES4319_CLDO_PU		4	/* 0x00000010 */
594 #define	BHND_PMU_RES4319_PALDO_PU		5	/* 0x00000020 */
595 #define	BHND_PMU_RES4319_ILP_REQUEST		6	/* 0x00000040 */
596 #define	BHND_PMU_RES4319_LNLDO1_PU		9	/* 0x00000200 */
597 #define	BHND_PMU_RES4319_OTP_PU			10	/* 0x00000400 */
598 #define	BHND_PMU_RES4319_LNLDO2_PU		12	/* 0x00001000 */
599 #define	BHND_PMU_RES4319_XTAL_PU		13	/* 0x00002000 */
600 #define	BHND_PMU_RES4319_ALP_AVAIL		14	/* 0x00004000 */
601 #define	BHND_PMU_RES4319_RX_PWRSW_PU		15	/* 0x00008000 */
602 #define	BHND_PMU_RES4319_TX_PWRSW_PU		16	/* 0x00010000 */
603 #define	BHND_PMU_RES4319_RFPLL_PWRSW_PU		17	/* 0x00020000 */
604 #define	BHND_PMU_RES4319_LOGEN_PWRSW_PU		18	/* 0x00040000 */
605 #define	BHND_PMU_RES4319_AFE_PWRSW_PU		19	/* 0x00080000 */
606 #define	BHND_PMU_RES4319_BBPLL_PWRSW_PU		20	/* 0x00100000 */
607 #define	BHND_PMU_RES4319_HT_AVAIL		21	/* 0x00200000 */
608 
609 /* 4319 chip-specific CHIPCTL register bits */
610 #define	BHND_PMU1_PLL0_CHIPCTL0		0
611 #define	BHND_PMU1_PLL0_CHIPCTL1		1
612 #define	BHND_PMU1_PLL0_CHIPCTL2		2
613 #define	BHND_PMU_CCTRL4319USB_XTAL_SEL_MASK	0x00180000
614 #define	BHND_PMU_CCTRL4319USB_XTAL_SEL_SHIFT	19
615 #define	BHND_PMU_CCTRL4319USB_48MHZ_PLL_SEL	1
616 #define	BHND_PMU_CCTRL4319USB_24MHZ_PLL_SEL	2
617 
618 /* 4336 PMU resources  */
619 #define	BHND_PMU_RES4336_CBUCK_LPOM		0
620 #define	BHND_PMU_RES4336_CBUCK_BURST		1
621 #define	BHND_PMU_RES4336_CBUCK_LP_PWM		2
622 #define	BHND_PMU_RES4336_CBUCK_PWM		3
623 #define	BHND_PMU_RES4336_CLDO_PU		4
624 #define	BHND_PMU_RES4336_DIS_INT_RESET_PD	5
625 #define	BHND_PMU_RES4336_ILP_REQUEST		6
626 #define	BHND_PMU_RES4336_LNLDO_PU		7
627 #define	BHND_PMU_RES4336_LDO3P3_PU		8
628 #define	BHND_PMU_RES4336_OTP_PU			9
629 #define	BHND_PMU_RES4336_XTAL_PU		10
630 #define	BHND_PMU_RES4336_ALP_AVAIL		11
631 #define	BHND_PMU_RES4336_RADIO_PU		12
632 #define	BHND_PMU_RES4336_BG_PU			13
633 #define	BHND_PMU_RES4336_VREG1p4_PU_PU		14
634 #define	BHND_PMU_RES4336_AFE_PWRSW_PU		15
635 #define	BHND_PMU_RES4336_RX_PWRSW_PU		16
636 #define	BHND_PMU_RES4336_TX_PWRSW_PU		17
637 #define	BHND_PMU_RES4336_BB_PWRSW_PU		18
638 #define	BHND_PMU_RES4336_SYNTH_PWRSW_PU		19
639 #define	BHND_PMU_RES4336_MISC_PWRSW_PU		20
640 #define	BHND_PMU_RES4336_LOGEN_PWRSW_PU		21
641 #define	BHND_PMU_RES4336_BBPLL_PWRSW_PU		22
642 #define	BHND_PMU_RES4336_MACPHY_CLKAVAIL	23
643 #define	BHND_PMU_RES4336_HT_AVAIL		24
644 #define	BHND_PMU_RES4336_RSVD			25
645 
646 /* 4330 resources */
647 #define	BHND_PMU_RES4330_CBUCK_LPOM		0
648 #define	BHND_PMU_RES4330_CBUCK_BURST		1
649 #define	BHND_PMU_RES4330_CBUCK_LP_PWM		2
650 #define	BHND_PMU_RES4330_CBUCK_PWM		3
651 #define	BHND_PMU_RES4330_CLDO_PU		4
652 #define	BHND_PMU_RES4330_DIS_INT_RESET_PD	5
653 #define	BHND_PMU_RES4330_ILP_REQUEST		6
654 #define	BHND_PMU_RES4330_LNLDO_PU		7
655 #define	BHND_PMU_RES4330_LDO3P3_PU		8
656 #define	BHND_PMU_RES4330_OTP_PU			9
657 #define	BHND_PMU_RES4330_XTAL_PU		10
658 #define	BHND_PMU_RES4330_ALP_AVAIL		11
659 #define	BHND_PMU_RES4330_RADIO_PU		12
660 #define	BHND_PMU_RES4330_BG_PU			13
661 #define	BHND_PMU_RES4330_VREG1p4_PU_PU		14
662 #define	BHND_PMU_RES4330_AFE_PWRSW_PU		15
663 #define	BHND_PMU_RES4330_RX_PWRSW_PU		16
664 #define	BHND_PMU_RES4330_TX_PWRSW_PU		17
665 #define	BHND_PMU_RES4330_BB_PWRSW_PU		18
666 #define	BHND_PMU_RES4330_SYNTH_PWRSW_PU		19
667 #define	BHND_PMU_RES4330_MISC_PWRSW_PU		20
668 #define	BHND_PMU_RES4330_LOGEN_PWRSW_PU		21
669 #define	BHND_PMU_RES4330_BBPLL_PWRSW_PU		22
670 #define	BHND_PMU_RES4330_MACPHY_CLKAVAIL	23
671 #define	BHND_PMU_RES4330_HT_AVAIL		24
672 #define	BHND_PMU_RES4330_5gRX_PWRSW_PU		25
673 #define	BHND_PMU_RES4330_5gTX_PWRSW_PU		26
674 #define	BHND_PMU_RES4330_5g_LOGEN_PWRSW_PU	27
675 
676 /* 4313 resources */
677 #define	BHND_PMU_RES4313_BB_PU_RSRC		0
678 #define	BHND_PMU_RES4313_ILP_REQ_RSRC		1
679 #define	BHND_PMU_RES4313_XTAL_PU_RSRC		2
680 #define	BHND_PMU_RES4313_ALP_AVAIL_RSRC		3
681 #define	BHND_PMU_RES4313_RADIO_PU_RSRC		4
682 #define	BHND_PMU_RES4313_BG_PU_RSRC		5
683 #define	BHND_PMU_RES4313_VREG1P4_PU_RSRC	6
684 #define	BHND_PMU_RES4313_AFE_PWRSW_RSRC		7
685 #define	BHND_PMU_RES4313_RX_PWRSW_RSRC		8
686 #define	BHND_PMU_RES4313_TX_PWRSW_RSRC		9
687 #define	BHND_PMU_RES4313_BB_PWRSW_RSRC		10
688 #define	BHND_PMU_RES4313_SYNTH_PWRSW_RSRC	11
689 #define	BHND_PMU_RES4313_MISC_PWRSW_RSRC	12
690 #define	BHND_PMU_RES4313_BB_PLL_PWRSW_RSRC	13
691 #define	BHND_PMU_RES4313_HT_AVAIL_RSRC		14
692 #define	BHND_PMU_RES4313_MACPHY_CLK_AVAIL_RSRC	15
693 
694 /* 4313 chip-specific CHIPCTRL register bits */
695 #define	BHND_PMU_CCTRL4313_12MA_LED_DRIVE	0x00000007	/* 12 mA drive strengh for later 4313 */
696 
697 /* 43228 resources */
698 #define	BHND_PMU_RES43228_NOT_USED		0
699 #define	BHND_PMU_RES43228_ILP_REQUEST		1
700 #define	BHND_PMU_RES43228_XTAL_PU		2
701 #define	BHND_PMU_RES43228_ALP_AVAIL		3
702 #define	BHND_PMU_RES43228_PLL_EN		4
703 #define	BHND_PMU_RES43228_HT_PHY_AVAIL		5
704 
705 /*
706 * Maximum delay for the PMU state transition in us.
707 * This is an upper bound intended for spinwaits etc.
708 */
709 #define	BHND_PMU_MAX_TRANSITION_DLY		15000
710 
711 /* PMU resource up transition time in ILP cycles */
712 #define	BHND_PMURES_UP_TRANSITION		2
713 
714 #endif /* _BHND_CORES_PMU_BHND_PMUREG_H_ */
715