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Searched defs:BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT (Results 1 – 3 of 3) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h4135 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_sh_mask.h23027 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT … macro
H A Dnbio_7_0_sh_mask.h37759 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT … macro