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Searched defs:BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK (Results 1 – 2 of 2) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h246 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000L macro
H A Dbif_4_1_sh_mask.h585 #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000 macro