1 /////////////////////////////////////////////////////////////////////////
2 // $Id: bmi64.cc 14086 2021-01-30 08:35:35Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (c) 2011-2018 Stanislav Shwartsman
6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net]
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
21 /////////////////////////////////////////////////////////////////////////
22
23 #define NEED_CPU_REG_SHORTCUTS 1
24 #include "bochs.h"
25 #include "cpu.h"
26 #define LOG_THIS BX_CPU_THIS_PTR
27
28 #if BX_SUPPORT_X86_64
29
30 #if BX_SUPPORT_AVX
31
32 #include "scalar_arith.h"
33 #include "wide_int.h"
34
ANDN_GqBqEqR(bxInstruction_c * i)35 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ANDN_GqBqEqR(bxInstruction_c *i)
36 {
37 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
38 Bit64u op2_64 = BX_READ_64BIT_REG(i->src2());
39
40 op1_64 = ~op1_64 & op2_64;
41
42 SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
43
44 BX_WRITE_64BIT_REG(i->dst(), op1_64);
45
46 BX_NEXT_INSTR(i);
47 }
48
MULX_GqBqEqR(bxInstruction_c * i)49 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULX_GqBqEqR(bxInstruction_c *i)
50 {
51 Bit64u op1_64 = RDX;
52 Bit64u op2_64 = BX_READ_64BIT_REG(i->src2());
53
54 Bit128u product_128;
55
56 // product_128 = ((Bit128u) op1_64) * ((Bit128u) op2_64);
57 // product_64l = (Bit64u) (product_128 & 0xFFFFFFFFFFFFFFFF);
58 // product_64h = (Bit64u) (product_128 >> 64);
59
60 long_mul(&product_128,op1_64,op2_64);
61
62 BX_WRITE_64BIT_REG(i->src1(), product_128.lo);
63 BX_WRITE_64BIT_REG(i->dst(), product_128.hi);
64
65 BX_NEXT_INSTR(i);
66 }
67
BLSI_BqEqR(bxInstruction_c * i)68 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSI_BqEqR(bxInstruction_c *i)
69 {
70 Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
71 bool tmpCF = (op1_64 != 0);
72
73 op1_64 = (-op1_64) & op1_64;
74
75 SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
76 set_CF(tmpCF);
77
78 BX_WRITE_64BIT_REG(i->dst(), op1_64);
79
80 BX_NEXT_INSTR(i);
81 }
82
BLSMSK_BqEqR(bxInstruction_c * i)83 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSMSK_BqEqR(bxInstruction_c *i)
84 {
85 Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
86 bool tmpCF = (op1_64 == 0);
87
88 op1_64 = (op1_64-1) ^ op1_64;
89
90 SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
91 set_CF(tmpCF);
92
93 BX_WRITE_64BIT_REG(i->dst(), op1_64);
94
95 BX_NEXT_INSTR(i);
96 }
97
BLSR_BqEqR(bxInstruction_c * i)98 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BLSR_BqEqR(bxInstruction_c *i)
99 {
100 Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
101 bool tmpCF = (op1_64 == 0);
102
103 op1_64 = (op1_64-1) & op1_64;
104
105 SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
106 set_CF(tmpCF);
107
108 BX_WRITE_64BIT_REG(i->dst(), op1_64);
109
110 BX_NEXT_INSTR(i);
111 }
112
RORX_GqEqIbR(bxInstruction_c * i)113 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RORX_GqEqIbR(bxInstruction_c *i)
114 {
115 Bit64u op1_64 = BX_READ_64BIT_REG(i->src());
116
117 unsigned count = i->Ib() & 0x3f;
118 if (count) {
119 op1_64 = (op1_64 >> count) | (op1_64 << (64 - count));
120 }
121
122 BX_WRITE_64BIT_REG(i->dst(), op1_64);
123
124 BX_NEXT_INSTR(i);
125 }
126
SHRX_GqEqBqR(bxInstruction_c * i)127 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRX_GqEqBqR(bxInstruction_c *i)
128 {
129 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
130
131 unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
132 if (count)
133 op1_64 >>= count;
134
135 BX_WRITE_64BIT_REG(i->dst(), op1_64);
136
137 BX_NEXT_INSTR(i);
138 }
139
SARX_GqEqBqR(bxInstruction_c * i)140 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SARX_GqEqBqR(bxInstruction_c *i)
141 {
142 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
143
144 unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
145 if (count) {
146 /* count < 64, since only lower 6 bits used */
147 op1_64 = ((Bit64s) op1_64) >> count;
148 }
149
150 BX_WRITE_64BIT_REG(i->dst(), op1_64);
151
152 BX_NEXT_INSTR(i);
153 }
154
SHLX_GqEqBqR(bxInstruction_c * i)155 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLX_GqEqBqR(bxInstruction_c *i)
156 {
157 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
158
159 unsigned count = BX_READ_32BIT_REG(i->src2()) & 0x3f;
160 if (count)
161 op1_64 <<= count;
162
163 BX_WRITE_64BIT_REG(i->dst(), op1_64);
164
165 BX_NEXT_INSTR(i);
166 }
167
BEXTR_GqEqBqR(bxInstruction_c * i)168 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BEXTR_GqEqBqR(bxInstruction_c *i)
169 {
170 Bit16u control = BX_READ_16BIT_REG(i->src2());
171 unsigned start = control & 0xff;
172 unsigned len = control >> 8;
173
174 Bit64u op1_64 = bextrq(BX_READ_64BIT_REG(i->src1()), start, len);
175 SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
176 BX_WRITE_64BIT_REG(i->dst(), op1_64);
177
178 BX_NEXT_INSTR(i);
179 }
180
BZHI_GqEqBqR(bxInstruction_c * i)181 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BZHI_GqEqBqR(bxInstruction_c *i)
182 {
183 unsigned control = BX_READ_8BIT_REGL(i->src2());
184 bool tmpCF = 0;
185 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
186
187 if (control < 64) {
188 Bit64u mask = (BX_CONST64(1) << control) - 1;
189 op1_64 &= mask;
190 }
191 else {
192 tmpCF = 1;
193 }
194
195 SET_FLAGS_OSZAxC_LOGIC_64(op1_64); // keep PF unchanged
196 set_CF(tmpCF);
197
198 BX_WRITE_64BIT_REG(i->dst(), op1_64);
199
200 BX_NEXT_INSTR(i);
201 }
202
PEXT_GqBqEqR(bxInstruction_c * i)203 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXT_GqBqEqR(bxInstruction_c *i)
204 {
205 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
206 Bit64u op2_64 = BX_READ_64BIT_REG(i->src2()), result_64 = 0;
207
208 Bit64u wr_mask = 0x1;
209
210 for (; op2_64 != 0; op2_64 >>= 1)
211 {
212 if (op2_64 & 0x1) {
213 if (op1_64 & 0x1) result_64 |= wr_mask;
214 wr_mask <<= 1;
215 }
216 op1_64 >>= 1;
217 }
218
219 BX_WRITE_64BIT_REG(i->dst(), result_64);
220
221 BX_NEXT_INSTR(i);
222 }
223
PDEP_GqBqEqR(bxInstruction_c * i)224 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PDEP_GqBqEqR(bxInstruction_c *i)
225 {
226 Bit64u op1_64 = BX_READ_64BIT_REG(i->src1());
227 Bit64u op2_64 = BX_READ_64BIT_REG(i->src2()), result_64 = 0;
228
229 Bit64u wr_mask = 0x1;
230
231 for (; op2_64 != 0; op2_64 >>= 1)
232 {
233 if (op2_64 & 0x1) {
234 if (op1_64 & 0x1) result_64 |= wr_mask;
235 op1_64 >>= 1;
236 }
237 wr_mask <<= 1;
238 }
239
240 BX_WRITE_64BIT_REG(i->dst(), result_64);
241
242 BX_NEXT_INSTR(i);
243 }
244
245 #endif // BX_SUPPORT_AVX
246
ADCX_GqEqR(bxInstruction_c * i)247 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADCX_GqEqR(bxInstruction_c *i)
248 {
249 Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
250 Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
251 Bit64u sum_64 = op1_64 + op2_64 + getB_CF();
252
253 BX_WRITE_64BIT_REG(i->dst(), sum_64);
254
255 Bit64u carry_out = ADD_COUT_VEC(op1_64, op2_64, sum_64);
256 set_CF(carry_out >> 63);
257
258 BX_NEXT_INSTR(i);
259 }
260
ADOX_GqEqR(bxInstruction_c * i)261 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADOX_GqEqR(bxInstruction_c *i)
262 {
263 Bit64u op1_64 = BX_READ_64BIT_REG(i->dst());
264 Bit64u op2_64 = BX_READ_64BIT_REG(i->src());
265 Bit64u sum_64 = op1_64 + op2_64 + getB_OF();
266
267 BX_WRITE_64BIT_REG(i->dst(), sum_64);
268
269 Bit64u overflow = GET_ADD_OVERFLOW(op1_64, op2_64, sum_64, BX_CONST64(0x8000000000000000));
270 set_OF(!!overflow);
271
272 BX_NEXT_INSTR(i);
273 }
274
275 #endif
276