1 #ifndef UAE_CPUBOARD_H 2 #define UAE_CPUBOARD_H 3 4 #include "uae/types.h" 5 #ifdef FSUAE 6 #include "uae/memory.h" 7 #endif 8 9 extern addrbank *cpuboard_autoconfig_init(struct romconfig*); 10 extern bool cpuboard_maprom(void); 11 extern void cpuboard_map(void); 12 extern void cpuboard_reset(void); 13 extern void cpuboard_cleanup(void); 14 extern void cpuboard_init(void); 15 extern void cpuboard_clear(void); 16 extern void cpuboard_vsync(void); 17 extern void cpuboard_hsync(void); 18 extern void cpuboard_rethink(void); 19 extern bool cpuboard_is_ppcboard_irq(void); 20 extern int cpuboard_memorytype(struct uae_prefs *p); 21 extern int cpuboard_maxmemory(struct uae_prefs *p); 22 extern bool cpuboard_32bit(struct uae_prefs *p); 23 extern bool cpuboard_jitdirectompatible(struct uae_prefs *p); 24 extern bool is_ppc_cpu(struct uae_prefs *); 25 extern bool cpuboard_io_special(int addr, uae_u32 *val, int size, bool write); 26 extern void cpuboard_overlay_override(void); 27 extern void cpuboard_setboard(struct uae_prefs *p, int type, int subtype); 28 extern uaecptr cpuboard_get_reset_pc(uaecptr *stack); 29 extern void cpuboard_set_flash_unlocked(bool unlocked); 30 31 extern bool ppc_interrupt(int new_m68k_ipl); 32 33 extern void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32); 34 extern uae_u32 cyberstorm_scsi_ram_get(uaecptr addr); 35 extern int REGPARAM3 cyberstorm_scsi_ram_check(uaecptr addr, uae_u32 size) REGPARAM; 36 extern uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM; 37 38 void cyberstorm_irq(int level); 39 void cyberstorm_mk3_ppc_irq(int level); 40 void blizzardppc_irq(int level); 41 42 #define BOARD_MEMORY_Z2 1 43 #define BOARD_MEMORY_Z3 2 44 #define BOARD_MEMORY_HIGHMEM 3 45 #define BOARD_MEMORY_BLIZZARD_12xx 4 46 #define BOARD_MEMORY_BLIZZARD_PPC 5 47 #define BOARD_MEMORY_25BITMEM 6 48 #define BOARD_MEMORY_EMATRIX 7 49 50 #define ISCPUBOARD(type,subtype) (cpuboards[currprefs.cpuboard_type].id == type && (type < 0 || currprefs.cpuboard_subtype == subtype)) 51 52 #define BOARD_ACT 1 53 #define BOARD_ACT_SUB_APOLLO 0 54 55 #define BOARD_COMMODORE 2 56 #define BOARD_COMMODORE_SUB_A26x0 0 57 58 #define BOARD_DCE 3 59 60 #define BOARD_DKB 4 61 #define BOARD_DKB_SUB_12x0 0 62 #define BOARD_DKB_SUB_WILDFIRE 1 63 64 #define BOARD_GVP 5 65 #define BOARD_GVP_SUB_A3001SI 0 66 #define BOARD_GVP_SUB_A3001SII 1 67 #define BOARD_GVP_SUB_A530 2 68 #define BOARD_GVP_SUB_GFORCE030 3 69 #define BOARD_GVP_SUB_TEKMAGIC 4 70 71 #define BOARD_KUPKE 6 72 73 #define BOARD_MACROSYSTEM 7 74 #define BOARD_MACROSYSTEM_SUB_WARPENGINE_A4000 0 75 76 #define BOARD_MTEC 8 77 #define BOARD_MTEC_SUB_EMATRIX530 0 78 79 #define BOARD_BLIZZARD 9 80 #define BOARD_BLIZZARD_SUB_1230IV 0 81 #define BOARD_BLIZZARD_SUB_1260 1 82 #define BOARD_BLIZZARD_SUB_2060 2 83 #define BOARD_BLIZZARD_SUB_PPC 3 84 85 #define BOARD_CYBERSTORM 10 86 #define BOARD_CYBERSTORM_SUB_MK1 0 87 #define BOARD_CYBERSTORM_SUB_MK2 1 88 #define BOARD_CYBERSTORM_SUB_MK3 2 89 #define BOARD_CYBERSTORM_SUB_PPC 3 90 91 #define BOARD_RCS 11 92 #define BOARD_RCS_SUB_FUSIONFORTY 0 93 94 #define BOARD_IC 12 95 #define BOARD_IC_ACA500 0 96 97 #endif /* UAE_CPUBOARD_H */ 98