1 /* $OpenBSD: bwivar.h,v 1.31 2014/11/05 01:02:10 daniel Exp $ */
2
3 /*
4 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <sepherosa@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 * 3. Neither the name of The DragonFly Project nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific, prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.1 2007/09/08 06:15:54 sephe Exp $
37 */
38
39 #ifndef _IF_BWIVAR_H
40 #define _IF_BWIVAR_H
41
42 #define BWI_ALIGN 0x1000
43 #define BWI_RING_ALIGN BWI_ALIGN
44 #define BWI_BUS_SPACE_MAXADDR 0x3fffffff
45
46 #define BWI_TX_NRING 6
47 #define BWI_TXRX_NRING 6
48 #define BWI_TX_NDESC 128
49 #define BWI_RX_NDESC 64
50 #define BWI_TXSTATS_NDESC 64
51 #define BWI_TX_NSPRDESC 2
52 #define BWI_TX_DATA_RING 1
53
54 /* XXX Onoe/Sample/AMRR probably need different configuration */
55 #define BWI_SHRETRY 7
56 #define BWI_LGRETRY 4
57 #define BWI_SHRETRY_FB 3
58 #define BWI_LGRETRY_FB 2
59
60 #define BWI_LED_EVENT_NONE -1
61 #define BWI_LED_EVENT_POLL 0
62 #define BWI_LED_EVENT_TX 1
63 #define BWI_LED_EVENT_RX 2
64 #define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2)
65
66 enum bwi_txpwrcb_type {
67 BWI_TXPWR_INIT = 0,
68 BWI_TXPWR_FORCE = 1,
69 BWI_TXPWR_CALIB = 2
70 };
71
72 #define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
73
74 #define CSR_READ_4(sc, reg) \
75 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
76 #define CSR_READ_2(sc, reg) \
77 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
78
79 #define CSR_WRITE_4(sc, reg, val) \
80 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
81 #define CSR_WRITE_2(sc, reg, val) \
82 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
83
84 #define CSR_SETBITS_4(sc, reg, bits) \
85 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
86 #define CSR_SETBITS_2(sc, reg, bits) \
87 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
88
89 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
90 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
91 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
92 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
93
94 #define CSR_CLRBITS_4(sc, reg, bits) \
95 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
96 #define CSR_CLRBITS_2(sc, reg, bits) \
97 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
98
99 struct bwi_desc32 {
100 /* Little endian */
101 uint32_t ctrl;
102 uint32_t addr; /* BWI_DESC32_A_ */
103 } __packed;
104
105 #define BWI_DESC32_A_FUNC_TXRX 0x1
106 #define BWI_DESC32_A_FUNC_MASK 0xc0000000
107 #define BWI_DESC32_A_ADDR_MASK 0x3fffffff
108
109 #define BWI_DESC32_C_BUFLEN_MASK 0x00001fff
110 #define BWI_DESC32_C_ADDRHI_MASK 0x00030000
111 #define BWI_DESC32_C_EOR (1 << 28)
112 #define BWI_DESC32_C_INTR (1 << 29)
113 #define BWI_DESC32_C_FRAME_END (1 << 30)
114 #define BWI_DESC32_C_FRAME_START (1U << 31)
115
116 struct bwi_desc64 {
117 /* Little endian */
118 uint32_t ctrl0;
119 uint32_t ctrl1;
120 uint32_t addr_lo;
121 uint32_t addr_hi;
122 } __packed;
123
124 struct bwi_rxbuf_hdr {
125 /* Little endian */
126 uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */
127 uint8_t rxh_pad1[2];
128 uint16_t rxh_flags1;
129 uint8_t rxh_rssi;
130 uint8_t rxh_sq;
131 uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */
132 uint16_t rxh_flags3;
133 uint16_t rxh_flags2; /* BWI_RXH_F2_ */
134 uint16_t rxh_tsf;
135 uint8_t rxh_pad3[14]; /* Padded to 30bytes */
136 } __packed;
137
138 #define BWI_RXH_F1_BCM2053_RSSI (1 << 14)
139 #define BWI_RXH_F1_OFDM (1 << 0)
140
141 #define BWI_RXH_F2_TYPE2FRAME (1 << 2)
142
143 #define BWI_RXH_F3_BCM2050_RSSI (1 << 10)
144
145 #define BWI_RXH_PHYINFO_LNAGAIN (3 << 14)
146
147 struct bwi_txbuf_hdr {
148 /* Little endian */
149 uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */
150 uint8_t txh_fc[2];
151 uint16_t txh_unknown1;
152 uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */
153 uint8_t txh_ivs[16];
154 uint8_t txh_addr1[IEEE80211_ADDR_LEN];
155 uint16_t txh_unknown2;
156 uint8_t txh_rts_fb_plcp[4];
157 uint16_t txh_rts_fb_duration;
158 uint8_t txh_fb_plcp[4];
159 uint16_t txh_fb_duration;
160 uint8_t txh_pad2[2];
161 uint16_t txh_id; /* BWI_TXH_ID_ */
162 uint16_t txh_unknown3;
163 uint8_t txh_rts_plcp[6];
164 uint8_t txh_rts_fc[2];
165 uint16_t txh_rts_duration;
166 uint8_t txh_rts_ra[IEEE80211_ADDR_LEN];
167 uint8_t txh_rts_ta[IEEE80211_ADDR_LEN];
168 uint8_t txh_pad3[2];
169 uint8_t txh_plcp[6];
170 } __packed;
171
172 #define BWI_TXH_ID_RING_MASK 0xe000
173 #define BWI_TXH_ID_IDX_MASK 0x1fff
174
175 #define BWI_TXH_PHY_C_OFDM (1 << 0)
176 #define BWI_TXH_PHY_C_SHPREAMBLE (1 << 4)
177 #define BWI_TXH_PHY_C_ANTMODE_MASK 0x0300
178
179 #define BWI_TXH_MAC_C_ACK (1 << 0)
180 #define BWI_TXH_MAC_C_FIRST_FRAG (1 << 3)
181 #define BWI_TXH_MAC_C_HWSEQ (1 << 4)
182 #define BWI_TXH_MAC_C_FB_OFDM (1 << 8)
183
184 struct bwi_txstats {
185 /* Little endian */
186 uint8_t txs_pad1[4];
187 uint16_t txs_id;
188 uint8_t txs_flags;
189 uint8_t txs_retry_cnt;
190 uint8_t txs_pad2[2];
191 uint16_t txs_seq;
192 uint16_t txs_unknown;
193 uint8_t txs_pad3[2]; /* Padded to 16bytes */
194 } __packed;
195
196 struct bwi_ring_data {
197 uint32_t rdata_txrx_ctrl;
198 bus_size_t rdata_ring_sz;
199 bus_dmamap_t rdata_dmap;
200 bus_addr_t rdata_paddr;
201 void *rdata_desc;
202 };
203
204 struct bwi_txbuf {
205 struct mbuf *tb_mbuf;
206 bus_dmamap_t tb_dmap;
207
208 struct ieee80211_node *tb_ni;
209 int tb_rate_idx[2];
210 };
211
212 struct bwi_txbuf_data {
213 struct bwi_txbuf tbd_buf[BWI_TX_NDESC];
214 int tbd_used;
215 int tbd_idx;
216 };
217
218 struct bwi_rxbuf {
219 struct mbuf *rb_mbuf;
220 bus_addr_t rb_paddr;
221 bus_dmamap_t rb_dmap;
222 };
223
224 struct bwi_rxbuf_data {
225 struct bwi_rxbuf rbd_buf[BWI_RX_NDESC];
226 bus_dmamap_t rbd_tmp_dmap;
227 int rbd_idx;
228 };
229
230 struct bwi_txstats_data {
231 bus_dma_segment_t stats_ring_seg;
232 bus_dmamap_t stats_ring_dmap;
233 bus_addr_t stats_ring_paddr;
234 void *stats_ring;
235
236 bus_dma_segment_t stats_seg;
237 bus_dmamap_t stats_dmap;
238 bus_addr_t stats_paddr;
239 struct bwi_txstats *stats;
240
241 uint32_t stats_ctrl_base;
242 int stats_idx;
243 };
244
245 struct bwi_fwhdr {
246 /* Big endian */
247 uint8_t fw_type; /* BWI_FW_T_ */
248 uint8_t fw_gen; /* BWI_FW_GEN */
249 uint8_t fw_pad[2];
250 uint32_t fw_size;
251 #define fw_iv_cnt fw_size
252 } __packed;
253
254 #define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
255 #define BWI_FW_VERSION3 3
256 #define BWI_FW_VERSION4 4
257 #define BWI_FW_VERSION3_REVMAX 0x128
258 #define BWI_FW_T_UCODE 'u'
259 #define BWI_FW_T_PCM 'p'
260 #define BWI_FW_T_IV 'i'
261 #define BWI_FW_GEN_1 1
262 #define BWI_FW_IV_OFS_MASK 0x7fff
263 #define BWI_FW_IV_IS_32BIT (1 << 15)
264
265 struct fwheader {
266 char filename[64];
267 int filesize;
268 int fileoffset;
269 };
270
271 struct bwi_fw_iv {
272 /* Big endian */
273 uint16_t iv_ofs;
274 union {
275 uint32_t val32;
276 uint16_t val16;
277 } iv_val;
278 } __packed;
279
280 struct bwi_led {
281 uint8_t l_flags; /* BWI_LED_F_ */
282 uint8_t l_act; /* BWI_LED_ACT_ */
283 uint8_t l_mask;
284 };
285
286 #define BWI_LED_F_ACTLOW 0x1
287 #define BWI_LED_F_BLINK 0x2
288 #define BWI_LED_F_POLLABLE 0x4
289 #define BWI_LED_F_SLOW 0x8
290
291 enum bwi_clock_mode {
292 BWI_CLOCK_MODE_SLOW,
293 BWI_CLOCK_MODE_FAST,
294 BWI_CLOCK_MODE_DYN
295 };
296
297 struct bwi_regwin {
298 uint32_t rw_flags; /* BWI_REGWIN_F_ */
299 uint16_t rw_type; /* BWI_REGWIN_T_ */
300 uint8_t rw_id;
301 uint8_t rw_rev;
302 };
303
304 #define BWI_REGWIN_F_EXIST 0x1
305
306 #define BWI_CREATE_REGWIN(rw, id, type, rev) \
307 do { \
308 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \
309 (rw)->rw_type = (type); \
310 (rw)->rw_id = (id); \
311 (rw)->rw_rev = (rev); \
312 } while (0)
313
314 #define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
315 #define BWI_GPIO_REGWIN(sc) \
316 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
317 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
318
319 struct bwi_mac;
320
321 struct bwi_phy {
322 enum ieee80211_phymode phy_mode;
323 int phy_rev;
324 int phy_version;
325
326 uint32_t phy_flags; /* BWI_PHY_F_ */
327 uint16_t phy_tbl_ctrl;
328 uint16_t phy_tbl_data_lo;
329 uint16_t phy_tbl_data_hi;
330
331 void (*phy_init)(struct bwi_mac *);
332 };
333
334 #define BWI_PHY_F_CALIBRATED 0x1
335 #define BWI_PHY_F_LINKED 0x2
336 #define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
337
338 /* TX power control */
339 struct bwi_tpctl {
340 uint16_t bbp_atten; /* BBP attenuation: 4bits */
341 uint16_t rf_atten; /* RF attenuation */
342 uint16_t tp_ctrl1; /* ??: 3bits */
343 uint16_t tp_ctrl2; /* ??: 4bits */
344 };
345
346 #define BWI_RF_ATTEN_FACTOR 4
347 #define BWI_RF_ATTEN_MAX0 9
348 #define BWI_RF_ATTEN_MAX1 31
349 #define BWI_BBP_ATTEN_MAX 11
350 #define BWI_TPCTL1_MAX 7
351
352 struct bwi_rf_lo {
353 int8_t ctrl_lo;
354 int8_t ctrl_hi;
355 };
356
357 struct bwi_rf {
358 uint16_t rf_type; /* BWI_RF_T_ */
359 uint16_t rf_manu;
360 int rf_rev;
361
362 uint32_t rf_flags; /* BWI_RF_F_ */
363
364 #define BWI_RFLO_MAX 56
365 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX];
366 uint8_t rf_lo_used[8];
367
368 #define BWI_INVALID_NRSSI -1000
369 int16_t rf_nrssi[2]; /* Narrow RSSI */
370 int32_t rf_nrssi_slope;
371
372 #define BWI_NRSSI_TBLSZ 64
373 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ];
374
375 uint16_t rf_lo_gain; /* loopback gain */
376 uint16_t rf_rx_gain; /* TRSW RX gain */
377
378 uint16_t rf_calib; /* RF calibration value */
379 uint rf_curchan; /* current channel */
380
381 uint16_t rf_ctrl_rd;
382 int rf_ctrl_adj;
383 void (*rf_off)(struct bwi_mac *);
384 void (*rf_on)(struct bwi_mac *);
385
386 void (*rf_set_nrssi_thr)(struct bwi_mac *);
387 void (*rf_calc_nrssi_slope)(struct bwi_mac *);
388 int (*rf_calc_rssi)
389 (struct bwi_mac *,
390 const struct bwi_rxbuf_hdr *);
391
392 void (*rf_lo_update)(struct bwi_mac *);
393
394 #define BWI_TSSI_MAX 64
395 int8_t rf_txpower_map0[BWI_TSSI_MAX];
396 /* Indexed by TSSI */
397 int rf_idle_tssi0;
398
399 int8_t rf_txpower_map[BWI_TSSI_MAX];
400 int rf_idle_tssi;
401
402 int rf_base_tssi;
403
404 int rf_txpower_max; /* dBm */
405
406 int rf_ant_mode; /* BWI_ANT_MODE_ */
407 };
408
409 #define BWI_RF_F_INITED 0x1
410 #define BWI_RF_F_ON 0x2
411 #define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
412
413 #define BWI_ANT_MODE_0 0
414 #define BWI_ANT_MODE_1 1
415 #define BWI_ANT_MODE_UNKN 2
416 #define BWI_ANT_MODE_AUTO 3
417
418 struct fw_image;
419
420 struct bwi_mac {
421 struct bwi_regwin mac_regwin; /* MUST be first field */
422 #define mac_rw_flags mac_regwin.rw_flags
423 #define mac_type mac_regwin.rw_type
424 #define mac_id mac_regwin.rw_id
425 #define mac_rev mac_regwin.rw_rev
426 struct bwi_softc *mac_sc;
427
428 struct bwi_phy mac_phy; /* PHY I/F */
429 struct bwi_rf mac_rf; /* RF I/F */
430
431 struct bwi_tpctl mac_tpctl; /* TX power control */
432 uint32_t mac_flags; /* BWI_MAC_F_ */
433
434 uint8_t *mac_fw;
435 size_t mac_fw_size;
436 uint8_t *mac_ucode;
437 size_t mac_ucode_size;
438 uint8_t *mac_pcm;
439 size_t mac_pcm_size;
440 uint8_t *mac_iv;
441 size_t mac_iv_size;
442 uint8_t *mac_iv_ext;
443 size_t mac_iv_ext_size;
444 };
445
446 #define BWI_MAC_F_BSWAP 0x1
447 #define BWI_MAC_F_TPCTL_INITED 0x2
448 #define BWI_MAC_F_HAS_TXSTATS 0x4
449 #define BWI_MAC_F_INITED 0x8
450 #define BWI_MAC_F_ENABLED 0x10
451 #define BWI_MAC_F_LOCKED 0x20 /* for debug */
452 #define BWI_MAC_F_TPCTL_ERROR 0x40
453 #define BWI_MAC_F_PHYE_RESET 0x80
454
455 #define BWI_CREATE_MAC(mac, sc, id, rev) \
456 do { \
457 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
458 (id), BWI_REGWIN_T_MAC, (rev)); \
459 (mac)->mac_sc = (sc); \
460 } while (0)
461
462 #define BWI_MAC_MAX 2
463 #define BWI_LED_MAX 4
464
465 enum bwi_bus_space {
466 BWI_BUS_SPACE_30BIT = 1,
467 BWI_BUS_SPACE_32BIT,
468 BWI_BUS_SPACE_64BIT
469 };
470
471 #define BWI_TX_RADIOTAP_PRESENT \
472 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
473 (1 << IEEE80211_RADIOTAP_RATE) | \
474 (1 << IEEE80211_RADIOTAP_CHANNEL))
475
476 struct bwi_tx_radiotap_hdr {
477 struct ieee80211_radiotap_header wt_ihdr;
478 uint8_t wt_flags;
479 uint8_t wt_rate;
480 uint16_t wt_chan_freq;
481 uint16_t wt_chan_flags;
482 };
483
484 #define BWI_RX_RADIOTAP_PRESENT \
485 ((1 << IEEE80211_RADIOTAP_TSFT) | \
486 (1 << IEEE80211_RADIOTAP_FLAGS) | \
487 (1 << IEEE80211_RADIOTAP_RATE) | \
488 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
489 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
490 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
491
492 struct bwi_rx_radiotap_hdr {
493 struct ieee80211_radiotap_header wr_ihdr;
494 uint64_t wr_tsf;
495 uint8_t wr_flags;
496 uint8_t wr_rate;
497 uint16_t wr_chan_freq;
498 uint16_t wr_chan_flags;
499 int8_t wr_antsignal;
500 int8_t wr_antnoise;
501 /* TODO: sq */
502 };
503
504 struct bwi_node {
505 struct ieee80211_node ni;
506 struct ieee80211_amrr_node amn;
507 };
508
509 struct bwi_softc {
510 struct device sc_dev;
511 struct ieee80211com sc_ic;
512 uint32_t sc_flags; /* BWI_F_ */
513
514 uint32_t sc_cap; /* BWI_CAP_ */
515 uint16_t sc_bbp_id; /* BWI_BBPID_ */
516 uint8_t sc_bbp_rev;
517 uint8_t sc_bbp_pkg;
518
519 uint8_t sc_pci_revid;
520 uint16_t sc_pci_did;
521 uint16_t sc_pci_subvid;
522 uint16_t sc_pci_subdid;
523
524 uint16_t sc_card_flags; /* BWI_CARD_F_ */
525 uint16_t sc_pwron_delay;
526 int sc_locale;
527
528 bus_dma_tag_t sc_dmat;
529 bus_space_tag_t sc_mem_bt;
530 bus_space_handle_t sc_mem_bh;
531
532 struct timeout sc_scan_ch;
533 struct timeout sc_calib_ch;
534 struct timeout sc_amrr_ch;
535
536 struct ieee80211_amrr sc_amrr;
537
538 struct bwi_regwin *sc_cur_regwin;
539 struct bwi_regwin sc_com_regwin;
540 struct bwi_regwin sc_bus_regwin;
541
542 int sc_nmac;
543 struct bwi_mac sc_mac[BWI_MAC_MAX];
544
545 int sc_rx_rate;
546 int sc_tx_rate;
547 enum bwi_txpwrcb_type sc_txpwrcb_type;
548
549 int sc_led_blinking;
550 int sc_led_ticks;
551 struct bwi_led *sc_blink_led;
552 struct timeout sc_led_blink_next_ch;
553 struct timeout sc_led_blink_end_ch;
554 int sc_led_blink_offdur;
555 struct bwi_led sc_leds[BWI_LED_MAX];
556
557 enum bwi_bus_space sc_bus_space;
558
559 /* bounce buffers for 30 bit bus space devices */
560 caddr_t sc_bounce_tx_data[BWI_TX_NRING];
561 caddr_t sc_bounce_rx_data;
562
563 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING];
564 struct bwi_rxbuf_data sc_rx_bdata;
565
566 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING];
567 struct bwi_ring_data sc_rx_rdata;
568
569 struct bwi_txstats_data *sc_txstats;
570
571 int sc_tx_timer;
572
573 int (*sc_newstate)
574 (struct ieee80211com *,
575 enum ieee80211_state, int);
576
577 int (*sc_init_tx_ring)(struct bwi_softc *, int);
578 void (*sc_free_tx_ring)(struct bwi_softc *, int);
579
580 int (*sc_init_rx_ring)(struct bwi_softc *);
581 void (*sc_free_rx_ring)(struct bwi_softc *);
582 int (*sc_newbuf)(struct bwi_softc *, int, int);
583
584 int (*sc_init_txstats)(struct bwi_softc *);
585 void (*sc_free_txstats)(struct bwi_softc *);
586
587 void (*sc_setup_rxdesc)
588 (struct bwi_softc *, int, bus_addr_t, int);
589 int (*sc_rxeof)(struct bwi_softc *);
590
591 void (*sc_setup_txdesc)
592 (struct bwi_softc *, struct bwi_ring_data *,
593 int, bus_addr_t, int);
594 void (*sc_start_tx)
595 (struct bwi_softc *, uint32_t, int);
596
597 void (*sc_txeof_status)(struct bwi_softc *);
598
599 int (*sc_enable)(struct bwi_softc *);
600 void (*sc_disable)(struct bwi_softc *);
601
602 void (*sc_conf_write)(void *, uint32_t, uint32_t);
603 uint32_t (*sc_conf_read)(void *, uint32_t);
604
605 /* Sysctl variables */
606 int sc_fw_version; /* BWI_FW_VERSION[34] */
607 int sc_dwell_time; /* milliseconds */
608 int sc_led_idle;
609 int sc_led_blink;
610
611 #if NBPFILTER > 0
612 caddr_t sc_drvbpf;
613
614 union {
615 struct bwi_rx_radiotap_hdr th;
616 uint8_t pad[64];
617 } sc_rxtapu;
618 #define sc_rxtap sc_rxtapu.th
619 int sc_rxtap_len;
620
621 union {
622 struct bwi_tx_radiotap_hdr th;
623 uint8_t pad[64];
624 } sc_txtapu;
625 #define sc_txtap sc_txtapu.th
626 int sc_txtap_len;
627 #endif
628 };
629
630 #define BWI_F_BUS_INITED 0x1
631 #define BWI_F_PROMISC 0x2
632
633 #define MOBJ_WRITE_2(mac, objid, ofs, val) \
634 bwi_memobj_write_2((mac), (objid), (ofs), (val))
635 #define MOBJ_WRITE_4(mac, objid, ofs, val) \
636 bwi_memobj_write_4((mac), (objid), (ofs), (val))
637 #define MOBJ_READ_2(mac, objid, ofs) \
638 bwi_memobj_read_2((mac), (objid), (ofs))
639 #define MOBJ_READ_4(mac, objid, ofs) \
640 bwi_memobj_read_4((mac), (objid), (ofs))
641
642 #define MOBJ_SETBITS_4(mac, objid, ofs, bits) \
643 MOBJ_WRITE_4((mac), (objid), (ofs), \
644 MOBJ_READ_4((mac), (objid), (ofs)) | (bits))
645 #define MOBJ_CLRBITS_4(mac, objid, ofs, bits) \
646 MOBJ_WRITE_4((mac), (objid), (ofs), \
647 MOBJ_READ_4((mac), (objid), (ofs)) & ~(bits))
648
649 #define MOBJ_FILT_SETBITS_2(mac, objid, ofs, filt, bits) \
650 MOBJ_WRITE_2((mac), (objid), (ofs), \
651 (MOBJ_READ_2((mac), (objid), (ofs)) & (filt)) | (bits))
652
653 #define TMPLT_WRITE_4(mac, ofs, val) bwi_tmplt_write_4((mac), (ofs), (val))
654
655 #define HFLAGS_WRITE(mac, flags) bwi_hostflags_write((mac), (flags))
656 #define HFLAGS_READ(mac) bwi_hostflags_read((mac))
657 #define HFLAGS_CLRBITS(mac, bits) \
658 HFLAGS_WRITE((mac), HFLAGS_READ((mac)) | (bits))
659 #define HFLAGS_SETBITS(mac, bits) \
660 HFLAGS_WRITE((mac), HFLAGS_READ((mac)) & ~(bits))
661
662 /* PHY */
663
664 struct bwi_gains {
665 int16_t tbl_gain1;
666 int16_t tbl_gain2;
667 int16_t phy_gain;
668 };
669
670 static __inline void
bwi_phy_init(struct bwi_mac * _mac)671 bwi_phy_init(struct bwi_mac *_mac)
672 {
673 _mac->mac_phy.phy_init(_mac);
674 }
675
676 #define PHY_WRITE(mac, ctrl, val) bwi_phy_write((mac), (ctrl), (val))
677 #define PHY_READ(mac, ctrl) bwi_phy_read((mac), (ctrl))
678
679 #define PHY_SETBITS(mac, ctrl, bits) \
680 PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) | (bits))
681 #define PHY_CLRBITS(mac, ctrl, bits) \
682 PHY_WRITE((mac), (ctrl), PHY_READ((mac), (ctrl)) & ~(bits))
683 #define PHY_FILT_SETBITS(mac, ctrl, filt, bits) \
684 PHY_WRITE((mac), (ctrl), (PHY_READ((mac), (ctrl)) & (filt)) | (bits))
685
686 static __inline void
bwi_rf_off(struct bwi_mac * _mac)687 bwi_rf_off(struct bwi_mac *_mac)
688 {
689 _mac->mac_rf.rf_off(_mac);
690 /* TODO: LED */
691
692 _mac->mac_rf.rf_flags &= ~BWI_RF_F_ON;
693 }
694
695 static __inline void
bwi_rf_on(struct bwi_mac * _mac)696 bwi_rf_on(struct bwi_mac *_mac)
697 {
698 if (_mac->mac_rf.rf_flags & BWI_RF_F_ON)
699 return;
700
701 _mac->mac_rf.rf_on(_mac);
702 /* TODO: LED */
703
704 _mac->mac_rf.rf_flags |= BWI_RF_F_ON;
705 }
706
707 static __inline void
bwi_rf_calc_nrssi_slope(struct bwi_mac * _mac)708 bwi_rf_calc_nrssi_slope(struct bwi_mac *_mac)
709 {
710 _mac->mac_rf.rf_calc_nrssi_slope(_mac);
711 }
712
713 static __inline void
bwi_rf_set_nrssi_thr(struct bwi_mac * _mac)714 bwi_rf_set_nrssi_thr(struct bwi_mac *_mac)
715 {
716 _mac->mac_rf.rf_set_nrssi_thr(_mac);
717 }
718
719 static __inline int
bwi_rf_calc_rssi(struct bwi_mac * _mac,const struct bwi_rxbuf_hdr * _hdr)720 bwi_rf_calc_rssi(struct bwi_mac *_mac, const struct bwi_rxbuf_hdr *_hdr)
721 {
722 return (_mac->mac_rf.rf_calc_rssi(_mac, _hdr));
723 }
724
725 static __inline void
bwi_rf_lo_update(struct bwi_mac * _mac)726 bwi_rf_lo_update(struct bwi_mac *_mac)
727 {
728 _mac->mac_rf.rf_lo_update(_mac);
729 }
730
731 #define RF_WRITE(mac, ofs, val) bwi_rf_write((mac), (ofs), (val))
732 #define RF_READ(mac, ofs) bwi_rf_read((mac), (ofs))
733
734 #define RF_SETBITS(mac, ofs, bits) \
735 RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) | (bits))
736 #define RF_CLRBITS(mac, ofs, bits) \
737 RF_WRITE((mac), (ofs), RF_READ((mac), (ofs)) & ~(bits))
738 #define RF_FILT_SETBITS(mac, ofs, filt, bits) \
739 RF_WRITE((mac), (ofs), (RF_READ((mac), (ofs)) & (filt)) | (bits))
740
741 #endif /* !_IF_BWIVAR_H */
742
743 int bwi_intr(void *);
744 int bwi_attach(struct bwi_softc *);
745 int bwi_detach(void *);
746 int bwi_init(struct ifnet *);
747 int bwi_stop(struct bwi_softc *, int);
748