1 /** @file 2 Register names for PCH Smbus Device. 3 4 Conventions: 5 6 - Prefixes: 7 Definitions beginning with "R_" are registers 8 Definitions beginning with "B_" are bits within registers 9 Definitions beginning with "V_" are meaningful values within the bits 10 Definitions beginning with "S_" are register sizes 11 Definitions beginning with "N_" are the bit position 12 - In general, PCH registers are denoted by "_PCH_" in register names 13 - Registers / bits that are different between PCH generations are denoted by 14 "_PCH_[generation_name]_" in register/bit names. 15 - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. 16 Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. 17 e.g., "_PCH_H_", "_PCH_LP_" 18 Registers / bits names without _H_ or _LP_ apply for both H and LP. 19 - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" 20 at the end of the register/bit names 21 - Registers / bits of new devices introduced in a PCH generation will be just named 22 as "_PCH_" without [generation_name] inserted. 23 24 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 25 SPDX-License-Identifier: BSD-2-Clause-Patent 26 27 **/ 28 #ifndef _PCH_REGS_SMBUS_H_ 29 #define _PCH_REGS_SMBUS_H_ 30 31 // 32 // SMBus Controller Registers (D31:F4) 33 // 34 #define PCI_DEVICE_NUMBER_PCH_SMBUS 31 35 #define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 36 #define R_PCH_SMBUS_BASE 0x20 37 #define V_PCH_SMBUS_BASE_SIZE (1 << 5) 38 #define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 39 #define R_PCH_SMBUS_HOSTC 0x40 40 #define B_PCH_SMBUS_HOSTC_SPDWD BIT4 41 #define B_PCH_SMBUS_HOSTC_SSRESET BIT3 42 #define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 43 #define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 44 #define B_PCH_SMBUS_HOSTC_HST_EN BIT0 45 #define R_PCH_SMBUS_TCOBASE 0x50 46 #define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0 47 #define R_PCH_SMBUS_TCOCTL 0x54 48 #define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8 49 #define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 50 #define R_PCH_SMBUS_64 0x64 51 #define R_PCH_SMBUS_80 0x80 52 53 // 54 // SMBus I/O Registers 55 // 56 #define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W 57 #define B_PCH_SMBUS_HBSY 0x01 58 #define B_PCH_SMBUS_INTR 0x02 59 #define B_PCH_SMBUS_DERR 0x04 60 #define B_PCH_SMBUS_BERR 0x08 61 #define B_PCH_SMBUS_FAIL 0x10 62 #define B_PCH_SMBUS_SMBALERT_STS 0x20 63 #define B_PCH_SMBUS_IUS 0x40 64 #define B_PCH_SMBUS_BYTE_DONE_STS 0x80 65 #define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL) 66 #define B_PCH_SMBUS_HSTS_ALL 0xFF 67 #define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W 68 #define B_PCH_SMBUS_INTREN 0x01 69 #define B_PCH_SMBUS_KILL 0x02 70 #define B_PCH_SMBUS_SMB_CMD 0x1C 71 #define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 72 #define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 73 #define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 74 #define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C 75 #define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 76 #define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 77 #define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 78 #define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C 79 #define B_PCH_SMBUS_LAST_BYTE 0x20 80 #define B_PCH_SMBUS_START 0x40 81 #define B_PCH_SMBUS_PEC_EN 0x80 82 #define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W 83 #define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W 84 #define B_PCH_SMBUS_RW_SEL 0x01 85 #define B_PCH_SMBUS_READ 0x01 // RW 86 #define B_PCH_SMBUS_WRITE 0x00 // RW 87 #define B_PCH_SMBUS_ADDRESS 0xFE 88 #define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W 89 #define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W 90 #define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W 91 #define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W 92 #define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W 93 #define B_PCH_SMBUS_SLAVE_ADDR 0x7F 94 #define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W 95 #define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC 96 #define B_PCH_SMBUS_CRCE 0x01 97 #define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode 98 #define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W 99 #define B_PCH_SMBUS_AAC 0x01 100 #define B_PCH_SMBUS_E32B 0x02 101 #define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W 102 #define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 103 #define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 104 #define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 105 #define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W 106 #define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 107 #define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 108 #define B_PCH_SMBUS_SMBCLK_CTL 0x04 109 #define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC 110 #define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 111 #define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W 112 #define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 113 #define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 114 #define B_PCH_SMBUS_SMBALERT_DIS 0x04 115 #define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO 116 #define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE 117 #define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO 118 #define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO 119 120 // 121 // SMBus Private Config Registers 122 // (PID:SMB) 123 // 124 #define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register 125 #define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable 126 #define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select 127 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00 128 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01 129 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02 130 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled 131 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled 132 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled 133 #define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled 134 #define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode 135 #define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter 136 #define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch 137 #define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode 138 #define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up 139 #define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control 140 #define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable 141 #define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot 142 #define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable 143 #endif 144