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Searched defs:Banks (Results 1 – 25 of 38) sorted by relevance

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/dports/emulators/nestopia/nestopia-1.51.1/source/core/board/
H A DNstBoardMmc5.hpp361 struct Banks struct in Nes::Core::Boards::Mmc5
368 {
383 enum FetchMode
390 enum LastChr
396 class Wrk
412 uint nmt;
413 word chrA[8];
414 word chrB[4];
415 dword chrHigh;
418 uint security;
[all …]
H A DNstBoardJyCompany.hpp159 struct Banks struct in Nes::Core::Boards::JyCompany::Standard
165 uint prg[4];
166 uint chr[8];
167 uint nmt[4];
170 {
173 } exChr;
175 const byte* prg6;
176 uint chrLatch[2];
/dports/games/libretro-nestopia/nestopia-2b0315c/source/core/board/
H A DNstBoardMmc5.hpp361 struct Banks struct in Nes::Core::Boards::Mmc5
368 {
383 enum FetchMode
390 enum LastChr
396 class Wrk
412 uint nmt;
413 word chrA[8];
414 word chrB[4];
415 dword chrHigh;
418 uint security;
[all …]
H A DNstBoardJyCompany.hpp159 struct Banks struct in Nes::Core::Boards::JyCompany::Standard
165 uint prg[4];
166 uint chr[8];
167 uint nmt[4];
170 {
173 } exChr;
175 const byte* prg6;
176 uint chrLatch[2];
/dports/games/stendhal/stendhal-1.35/src/games/stendhal/server/entity/slot/
H A DBanks.java19 public enum Banks { enum
41 private Banks(final String slotName) { in Banks() method in Banks
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_flash_ex.c750 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) in FLASH_MassErase()
812 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) in FLASH_Erase_Sector()
853 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) in FLASH_OB_EnableWRP()
886 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) in FLASH_OB_DisableWRP()
1245 …B_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks) in FLASH_OB_PCROPConfig()
1480 …int32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks) in FLASH_OB_SecureAreaConfig()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
282 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
282 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
149 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
217 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
285 std::vector<RegisterBank> Banks; in run() local
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp131 const std::vector<RegisterBank> &Banks) { in emitHeader()
147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
284 std::vector<RegisterBank> Banks; in run() local
/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp127 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run() local
/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/
H A DRegisterBankEmitter.cpp131 const std::vector<RegisterBank> &Banks) { in emitHeader()
147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
284 std::vector<RegisterBank> Banks; in run() local
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32G4xx_HAL_Driver/src/
H A Dstm32g4xx_hal_flash_ex.c540 static void FLASH_MassErase(uint32_t Banks) in FLASH_MassErase()
585 void FLASH_PageErase(uint32_t Page, uint32_t Banks) in FLASH_PageErase()
/dports/games/supertuxkart/SuperTuxKart-1.2-src/lib/irrlicht/source/Irrlicht/
H A DCGUIEnvironment.h302 core::array<SSpriteBank> Banks; variable
/dports/x11-toolkits/irrlicht/irrlicht-1.8.5/source/Irrlicht/
H A DCGUIEnvironment.h303 core::array<SSpriteBank> Banks; variable
/dports/audio/samplv1-lv2/samplv1-samplv1_0_9_23/src/
H A Dsamplv1_programs.h94 typedef QMap<uint16_t, Bank *> Banks; typedef

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