1 /* 2 * Cisco router simulation platform. 3 * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) 4 * 5 * Generic Cisco MSFC1 routines and definitions (EEPROM,...). 6 */ 7 8 #ifndef __DEV_C6MSFC1_H__ 9 #define __DEV_C6MSFC1_H__ 10 11 #include <pthread.h> 12 13 #include "utils.h" 14 #include "net.h" 15 #include "device.h" 16 #include "pci_dev.h" 17 #include "nmc93cX6.h" 18 #include "dev_ds1620.h" 19 #include "net_io.h" 20 #include "vm.h" 21 22 /* Default MSFC1 parameters */ 23 #define C6MSFC1_DEFAULT_RAM_SIZE 256 24 #define C6MSFC1_DEFAULT_ROM_SIZE 4 25 #define C6MSFC1_DEFAULT_NVRAM_SIZE 128 26 #define C6MSFC1_DEFAULT_CONF_REG 0x2102 27 #define C6MSFC1_DEFAULT_CLOCK_DIV 4 28 #define C6MSFC1_DEFAULT_RAM_MMAP 1 29 30 /* EOBC + IBC */ 31 #define C6MSFC1_MAX_PA_BAYS 2 32 33 /* MSFC1 Timer IRQ (virtual) */ 34 #define C6MSFC1_VTIMER_IRQ 0 35 36 /* MSFC1 DUART Interrupt */ 37 #define C6MSFC1_DUART_IRQ 5 38 39 /* MSFC1 Network I/O Interrupt */ 40 #define C6MSFC1_NETIO_IRQ 2 41 42 /* MSFC1 PA Management Interrupt handler */ 43 #define C6MSFC1_PA_MGMT_IRQ 3 44 45 /* MSFC1 GT64k DMA/Timer Interrupt */ 46 #define C6MSFC1_GT64K_IRQ 4 47 48 /* MSFC1 Error/OIR Interrupt */ 49 #define C6MSFC1_OIR_IRQ 6 50 51 /* Network IRQ */ 52 #define C6MSFC1_NETIO_IRQ_BASE 32 53 #define C6MSFC1_NETIO_IRQ_END \ 54 (C6MSFC1_NETIO_IRQ_BASE + C6MSFC1_MAX_PA_BAYS - 1) 55 56 /* MSFC1 base ram limit (256 Mb) */ 57 #define C6MSFC1_BASE_RAM_LIMIT 256 58 59 /* MSFC1 common device addresses */ 60 #define C6MSFC1_GT64K_ADDR 0x14000000ULL 61 #define C6MSFC1_GT64K_SEC_ADDR 0x15000000ULL 62 #define C6MSFC1_BOOTFLASH_ADDR 0x1a000000ULL 63 #define C6MSFC1_NVRAM_ADDR 0x1e000000ULL 64 #define C6MSFC1_MPFPGA_ADDR 0x1e800000ULL 65 #define C6MSFC1_IOFPGA_ADDR 0x1e840000ULL 66 #define C6MSFC1_BITBUCKET_ADDR 0x1f000000ULL 67 #define C6MSFC1_ROM_ADDR 0x1fc00000ULL 68 #define C6MSFC1_IOMEM_ADDR 0x20000000ULL 69 #define C6MSFC1_SRAM_ADDR 0x4b000000ULL 70 #define C6MSFC1_BSWAP_ADDR 0xc0000000ULL 71 #define C6MSFC1_PCI_IO_ADDR 0x100000000ULL 72 73 /* SRAM size */ 74 #define C6MSFC1_SRAM_SIZE (4096*1024) 75 76 /* Reserved space for ROM in NVRAM */ 77 #define C6MSFC1_NVRAM_ROM_RES_SIZE 2048 78 79 /* MSFC1 physical address bus mask: keep only the lower 33 bits */ 80 #define C6MSFC1_ADDR_BUS_MASK 0x1ffffffffULL 81 82 /* MSFC1 ELF Platform ID */ 83 #define C6MSFC1_ELF_MACHINE_ID 0x19 84 85 /* 2 temperature sensors in a MSFC1: chassis inlet and oulet */ 86 #define C6MSFC1_TEMP_SENSORS 2 87 88 #define VM_C6MSFC1(vm) ((c6msfc1_t *)vm->hw_data) 89 90 /* MSFC1 router */ 91 typedef struct c6msfc1_router c6msfc1_t; 92 93 /* MSFC1 router */ 94 struct c6msfc1_router { 95 /* Chassis MAC address */ 96 n_eth_addr_t mac_addr; 97 98 /* Associated VM instance */ 99 vm_instance_t *vm; 100 101 /* Midplane FPGA */ 102 struct c6msfc1_mpfpga_data *mpfpga_data; 103 104 /* Midplane EEPROM can be modified to change the chassis MAC address... */ 105 struct cisco_eeprom cpu_eeprom,mp_eeprom; 106 107 /* EEPROMs for CPU and Midplane */ 108 struct nmc93cX6_group sys_eeprom_g1; 109 110 /* Temperature sensors */ 111 struct ds1620_data ds1620_sensors[C6MSFC1_TEMP_SENSORS]; 112 113 /* Slot of this MSFC */ 114 u_int msfc_slot; 115 }; 116 117 /* Initialize EEPROM groups */ 118 void c6msfc1_init_eeprom_groups(c6msfc1_t *router); 119 120 /* Get network IRQ for specified slot/port */ 121 u_int c6msfc1_net_irq_for_slot_port(u_int slot,u_int port); 122 123 /* Show the list of available PA drivers */ 124 void c6msfc1_pa_show_drivers(void); 125 126 /* Set chassis MAC address */ 127 int c6msfc1_midplane_set_mac_addr(c6msfc1_t *router,char *mac_addr); 128 129 /* Show MSFC1 hardware info */ 130 void c6msfc1_show_hardware(c6msfc1_t *router); 131 132 /* dev_c6msfc1_iofpga_init() */ 133 int dev_c6msfc1_iofpga_init(c6msfc1_t *router,m_uint64_t paddr,m_uint32_t len); 134 135 /* dev_mpfpga_init() */ 136 int dev_c6msfc1_mpfpga_init(c6msfc1_t *router,m_uint64_t paddr,m_uint32_t len); 137 138 /* Register the c6msfc1 platform */ 139 int c6msfc1_platform_register(void); 140 141 #endif 142