1 /* $NetBSD: pl310_reg.h,v 1.4 2014/03/22 17:12:20 reinoud Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_CORTEX_PL310_REG_H_ 32 #define _ARM_CORTEX_PL310_REG_H_ 33 34 /* 35 * ARM PL310 L2 Cache Controller 36 * Used by Cortex cores 37 */ 38 39 #define L2C_CACHE_ID 0x000 40 #define CACHE_ID_IMPL __BITS(31,24) 41 #define CACHE_ID_ID __BITS(15,10) 42 #define CACHE_ID_PART __BITS(9,6) 43 #define CACHE_ID_PART_PL310 3 44 #define CACHE_ID_REV __BITS(5,0) 45 #define CACHE_ID_REV_R3P3 9 46 #define CACHE_ID_REV_R3P2 8 47 48 #define L2C_CACHE_TYPE 0x004 49 #define CACHE_TYPE_DATA_BANKING __BIT(31) 50 #define CACHE_TYPE_CTYPE __BITS(28,25) 51 #define CACHE_TYPE_HARVARD __BIT(24) 52 #define CACHE_TYPE_DSIZE __BITS(23,12) 53 #define CACHE_TYPE_ISIZE __BITS(11,0) 54 #define CACHE_TYPE_xWAYSIZE __BITS(10,8) 55 #define CACHE_TYPE_xASSOC __BIT(6) 56 #define CACHE_TYPE_xLINESIZE __BITS(5,0) 57 58 #define L2C_CTL 0x100 59 #define CTL_ENABLE __BIT(1) 60 #define L2C_AUXCTL 0x104 61 #define AUXCTL_RSVD31 __BIT(31) 62 #define AUXCTL_EARLY_BRESP_EN __BIT(30) 63 #define AUXCTL_I_PREFETCH __BIT(29) 64 #define AUXCTL_D_PREFETCH __BIT(28) 65 #define AUXCTL_NS_INT_ACC_CTL __BIT(27) 66 #define AUXCTL_NS_INT_LOCK_EN __BIT(26) 67 #define AUXCTL_CACHE_REPL_RR __BIT(25) 68 #define AUXCTL_FORCE_WA __BITS(24,23) 69 #define AUXCTL_FORCE_WA_AWCACHE 0 70 #define AUXCTL_FORCE_WA_NEVER 1 71 #define AUXCTL_FORCE_WA_ALWAYS 2 72 #define AUXCTL_FORCE_WA_0 3 73 #define AUXCTL_SHARED_ATT_OVR __BIT(22) 74 #define AUXCTL_PARITY_EN __BIT(21) 75 #define AUXCTL_EVT_MON_BUS_EN __BIT(20) 76 #define AUXCTL_WAY_SIZE __BITS(19,17) 77 #define AUXCTL_WAY_SIZE_RSVD0 0 78 #define AUXCTL_WAY_SIZE_16KB 1 79 #define AUXCTL_WAY_SIZE_32KB 2 80 #define AUXCTL_WAY_SIZE_64KB 3 81 #define AUXCTL_WAY_SIZE_128KB 4 82 #define AUXCTL_WAY_SIZE_256KB 5 83 #define AUXCTL_WAY_SIZE_512KB 6 84 #define AUXCTL_WAY_SIZE_RSVD7 7 85 #define AUXCTL_ASSOCIATIVITY __BIT(16) 86 #define AUXCTL_SH_ATTR_INV_ENA __BIT(13) 87 #define AUXCTL_EXCL_CACHE_CFG __BIT(12) 88 #define AUXCTL_ST_BUF_DEV_LIM_EN __BIT(11) 89 #define AUXCTL_HIPRO_SO_DEV_EN __BIT(10) 90 #define AUXCTL_FULL_LINE_WR0 __BIT(0) 91 #define L2C_TAGRAM_CTL 0x108 92 #define L2C_DATARAM_CTL 0x10c 93 94 #define L2C_EV_CTR_CTL 0x200 95 #define L2C_EV_CTR1_CTL 0x204 96 #define L2C_EV_CTR0_CTL 0x208 97 #define L2C_EV_CTR1 0x20c 98 #define L2C_EV_CTR0 0x210 99 #define L2C_INT_MASK 0x214 100 #define L2C_INT_MASK_STS 0x218 101 #define L2C_INT_RAW_STS 0x21c 102 #define L2C_INT_CLR 0x220 103 104 #define L2C_CACHE_SYNC 0x730 105 #define L2C_INV_PA 0x770 106 #define L2C_INV_WAY 0x77c 107 #define L2C_CLEAN_PA 0x7b0 108 #define L2C_CLEAN_INDEX 0x7b8 109 #define L2C_CLEAN_WAY 0x7bc 110 #define L2C_CLEAN_INV_PA 0x7f0 111 #define L2C_CLEAN_INV_INDEX 0x7f8 112 #define L2C_CLEAN_INV_WAY 0x7fc 113 114 #define L2C_D_LOCKDOWN0 0x900 115 #define L2C_I_LOCKDOWN0 0x904 116 #define L2C_D_LOCKDOWN1 0x908 117 #define L2C_I_LOCKDOWN1 0x90c 118 #define L2C_D_LOCKDOWN2 0x910 119 #define L2C_I_LOCKDOWN2 0x914 120 #define L2C_D_LOCKDOWN3 0x918 121 #define L2C_I_LOCKDOWN3 0x91c 122 #define L2C_D_LOCKDOWN4 0x920 123 #define L2C_I_LOCKDOWN4 0x924 124 #define L2C_D_LOCKDOWN5 0x928 125 #define L2C_I_LOCKDOWN5 0x92c 126 #define L2C_D_LOCKDOWN6 0x930 127 #define L2C_I_LOCKDOWN6 0x934 128 #define L2C_D_LOCKDOWN7 0x938 129 #define L2C_I_LOCKDOWN7 0x93c 130 #define L2C_LOCK_LINE_EN 0x950 131 #define L2C_UNLOCK_WAY 0x954 132 133 #define L2C_ADDR_FILTER_START 0xc00 134 #define L2C_ADDR_FILTER_END 0xc04 135 136 #define L2C_DEBUG_CTL 0xf40 137 #define L2C_PREFETCH_CTL 0xf60 138 #define PREFETCHCTL_DBLLINEF_EN __BIT(30) 139 #define PREFETCHCTL_INSTRPREF_EN __BIT(29) 140 #define PREFETCHCTL_DATAPREF_EN __BIT(28) 141 #define PREFETCHCTL_DBLLINEF_WRAP_DA __BIT(27) 142 #define PREFETCHCTL_PREF_DROP_EN __BIT(24) 143 #define PREFETCHCTL_INCRDBL_LINEF_EN __BIT(23) 144 #define PREFETCHCTL_NOSAMEID_EXCL_SEQ_EN __BIT(21) 145 #define PREFETCHCTL_PREFETCH_OFFSET_0 0 146 #define PREFETCHCTL_PREFETCH_OFFSET_7 7 147 #define PREFETCHCTL_PREFETCH_OFFSET_15 15 148 #define PREFETCHCTL_PREFETCH_OFFSET_23 23 149 #define PREFETCHCTL_PREFETCH_OFFSET_31 31 150 151 #define L2C_POWER_CTL 0xf80 152 #define POWERCTL_DYNCLKGATE __BIT(1) 153 #define POWERCTL_STANDBY __BIT(0) 154 155 #endif /* _ARM_CORTEX_PL310_REG_H_ */ 156